251 			/* Enable the DPLL */  in oaktrail_crtc_dpms()
252 			temp = REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
254 				REG_WRITE_WITH_AUX(map->dpll, temp, i);  in oaktrail_crtc_dpms()
255 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
258 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
260 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
263 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
265 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
324 			temp = REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
326 				REG_WRITE_WITH_AUX(map->dpll,  in oaktrail_crtc_dpms()
328 				REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_dpms()
380 	u32 dpll = 0, fp = 0, dspcntr, pipeconf;  in oaktrail_crtc_mode_set()  local
509 	dpll = 0;		/*BIT16 = 0 for 100MHz reference */  in oaktrail_crtc_mode_set()
533 	dpll |= DPLL_VGA_MODE_DIS;  in oaktrail_crtc_mode_set()
536 	dpll |= DPLL_VCO_ENABLE;  in oaktrail_crtc_mode_set()
539 		dpll |= DPLLA_MODE_LVDS;  in oaktrail_crtc_mode_set()
541 		dpll |= DPLLB_MODE_DAC_SERIAL;  in oaktrail_crtc_mode_set()
547 		dpll |= DPLL_DVO_HIGH_SPEED;  in oaktrail_crtc_mode_set()
548 		dpll |=  in oaktrail_crtc_mode_set()
556 		dpll |= clock.p1 << 16; // dpll |= (1 << (clock.p1 - 1)) << 16;  in oaktrail_crtc_mode_set()
558 		dpll |= (1 << (clock.p1 - 2)) << 17;  in oaktrail_crtc_mode_set()
560 	dpll |= DPLL_VCO_ENABLE;  in oaktrail_crtc_mode_set()
562 	if (dpll & DPLL_VCO_ENABLE) {  in oaktrail_crtc_mode_set()
565 			REG_WRITE_WITH_AUX(map->dpll, dpll & ~DPLL_VCO_ENABLE, i);  in oaktrail_crtc_mode_set()
566 			REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()
574 		REG_WRITE_WITH_AUX(map->dpll, dpll, i);  in oaktrail_crtc_mode_set()
575 		REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()
580 		REG_WRITE_WITH_AUX(map->dpll, dpll, i);  in oaktrail_crtc_mode_set()
581 		REG_READ_WITH_AUX(map->dpll, i);  in oaktrail_crtc_mode_set()