Lines Matching +full:0 +full:x34

63 		return 0;  in edp_pipe_is_enabled()
66 		return 0;  in edp_pipe_is_enabled()
83 	return 0;  in pipe_is_enabled()
90 		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
92 		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
94 		0x01, 0x04,
96 		0xa5, 0x34, 0x20, 0x78, 0x23,
98 		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
100 		0x21, 0x08, 0x00,
102 		0x00, 0xc0, 0x00, 0xc0, 0x00, 0x40, 0x00, 0x80, 0x00, 0x00,
103 		0x00, 0x40, 0x00, 0x00, 0x00, 0x01,
105 		0x00, 0x00, 0x80, 0xa0, 0x70, 0xb0,
106 		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
108 		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
109 		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
111 		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
112 		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
114 		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
115 		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
117 		0x00,
119 		0xef,
124 		0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00,
126 		0x22, 0xf0, 0x54, 0x29, 0x00, 0x00, 0x00, 0x00, 0x04, 0x17,
128 		0x01, 0x04,
130 		0xa5, 0x34, 0x20, 0x78, 0x23,
132 		0xfc, 0x81, 0xa4, 0x55, 0x4d, 0x9d, 0x25, 0x12, 0x50, 0x54,
134 		0x21, 0x08, 0x00,
141 		0xd1, 0xc0, 0x81, 0xc0, 0x81, 0x40, 0x81, 0x80, 0x95, 0x00,
142 		0xa9, 0x40, 0xb3, 0x00, 0x01, 0x01,
144 		0x28, 0x3c, 0x80, 0xa0, 0x70, 0xb0,
145 		0x23, 0x40, 0x30, 0x20, 0x36, 0x00, 0x06, 0x44, 0x21, 0x00, 0x00, 0x1a,
147 		0x00, 0x00, 0x00, 0xfd, 0x00, 0x18, 0x3c, 0x18, 0x50, 0x11, 0x00, 0x0a,
148 		0x20, 0x20, 0x20, 0x20, 0x20, 0x20,
150 		0x00, 0x00, 0x00, 0xfc, 0x00, 0x48,
151 		0x50, 0x20, 0x5a, 0x52, 0x32, 0x34, 0x34, 0x30, 0x77, 0x0a, 0x20, 0x20,
153 		0x00, 0x00, 0x00, 0xff, 0x00, 0x43, 0x4e, 0x34, 0x33, 0x30, 0x34, 0x30,
154 		0x44, 0x58, 0x51, 0x0a, 0x20, 0x20,
156 		0x00,
158 		0x45,
162 #define DPCD_HEADER_SIZE        0xb
166 	0x12, 0x014, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00
231 		vgpu_vreg_t(vgpu, PIPE_DATA_M1(TRANSCODER_A)) |= 0x5b425e;  in emulate_monitor_status_change()
232 		vgpu_vreg_t(vgpu, PIPE_DATA_N1(TRANSCODER_A)) = 0x800000;  in emulate_monitor_status_change()
233 		vgpu_vreg_t(vgpu, PIPE_LINK_M1(TRANSCODER_A)) = 0x3cd6e;  in emulate_monitor_status_change()
234 		vgpu_vreg_t(vgpu, PIPE_LINK_N1(TRANSCODER_A)) = 0x80000;  in emulate_monitor_status_change()
380 	port->dpcd->data[DPCD_SINK_COUNT] = 0x1;  in setup_virtual_dp_monitor()
385 	return 0;  in setup_virtual_dp_monitor()
406 		for (pipe = 0; pipe < I915_MAX_PIPES; pipe++) {  in intel_gvt_check_vblank_emulation()