Lines Matching +full:0 +full:x234
33 #define RING_ELSP(engine) _MMIO((engine)->mmio_base + 0x230)
34 #define RING_EXECLIST_STATUS_LO(engine) _MMIO((engine)->mmio_base + 0x234)
35 #define RING_EXECLIST_STATUS_HI(engine) _MMIO((engine)->mmio_base + 0x234 + 4)
36 #define RING_CONTEXT_CONTROL(engine) _MMIO((engine)->mmio_base + 0x244)
38 #define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
41 #define RING_CONTEXT_STATUS_BUF_BASE(engine) _MMIO((engine)->mmio_base + 0x370)
42 #define RING_CONTEXT_STATUS_BUF_LO(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8)
43 #define RING_CONTEXT_STATUS_BUF_HI(engine, i) _MMIO((engine)->mmio_base + 0x370 + (i) * 8 + 4)
44 #define RING_CONTEXT_STATUS_PTR(engine) _MMIO((engine)->mmio_base + 0x3a0)
45 #define RING_EXECLIST_SQ_CONTENTS(engine) _MMIO((engine)->mmio_base + 0x510)
46 #define RING_EXECLIST_CONTROL(engine) _MMIO((engine)->mmio_base + 0x550)
47 #define EL_CTRL_LOAD (1 << 0)
51 * wraps to 0."
57 #define GEN8_CSB_PTR_MASK 0x7
59 #define GEN8_CSB_WRITE_PTR_MASK (GEN8_CSB_PTR_MASK << 0)
61 (((csb_status) & GEN8_CSB_WRITE_PTR_MASK) >> 0)
66 INTEL_CONTEXT_SCHEDULE_IN = 0,
88 #define LRC_GUCSHR_PN (0)