Lines Matching full:engine
153 *cs++ = i915_ggtt_offset(rq->engine->scratch) | in gen4_render_ring_flush()
162 *cs++ = i915_ggtt_offset(rq->engine->scratch) | in gen4_render_ring_flush()
216 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in intel_emit_post_sync_nonzero_flush()
250 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in gen6_render_ring_flush()
320 i915_ggtt_offset(rq->engine->scratch) + 2 * CACHELINE_BYTES; in gen7_render_ring_flush()
378 static void ring_setup_phys_status_page(struct intel_engine_cs *engine) in ring_setup_phys_status_page() argument
380 struct drm_i915_private *dev_priv = engine->i915; in ring_setup_phys_status_page()
389 static void intel_ring_setup_status_page(struct intel_engine_cs *engine) in intel_ring_setup_status_page() argument
391 struct drm_i915_private *dev_priv = engine->i915; in intel_ring_setup_status_page()
398 switch (engine->id) { in intel_ring_setup_status_page()
404 GEM_BUG_ON(engine->id); in intel_ring_setup_status_page()
419 mmio = RING_HWS_PGA_GEN6(engine->mmio_base); in intel_ring_setup_status_page()
421 mmio = RING_HWS_PGA(engine->mmio_base); in intel_ring_setup_status_page()
431 if (engine->id == RCS) in intel_ring_setup_status_page()
434 I915_WRITE(RING_HWSTAM(engine->mmio_base), mask); in intel_ring_setup_status_page()
437 I915_WRITE(mmio, engine->status_page.ggtt_offset); in intel_ring_setup_status_page()
442 i915_reg_t reg = RING_INSTPM(engine->mmio_base); in intel_ring_setup_status_page()
445 WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); in intel_ring_setup_status_page()
454 engine->name); in intel_ring_setup_status_page()
458 static bool stop_ring(struct intel_engine_cs *engine) in stop_ring() argument
460 struct drm_i915_private *dev_priv = engine->i915; in stop_ring()
463 I915_WRITE_MODE(engine, _MASKED_BIT_ENABLE(STOP_RING)); in stop_ring()
465 RING_MI_MODE(engine->mmio_base), in stop_ring()
470 engine->name); in stop_ring()
475 if (I915_READ_HEAD(engine) != I915_READ_TAIL(engine)) in stop_ring()
480 I915_WRITE_HEAD(engine, I915_READ_TAIL(engine)); in stop_ring()
482 I915_WRITE_HEAD(engine, 0); in stop_ring()
483 I915_WRITE_TAIL(engine, 0); in stop_ring()
486 I915_WRITE_CTL(engine, 0); in stop_ring()
488 return (I915_READ_HEAD(engine) & HEAD_ADDR) == 0; in stop_ring()
491 static int init_ring_common(struct intel_engine_cs *engine) in init_ring_common() argument
493 struct drm_i915_private *dev_priv = engine->i915; in init_ring_common()
494 struct intel_ring *ring = engine->buffer; in init_ring_common()
499 if (!stop_ring(engine)) { in init_ring_common()
503 engine->name, in init_ring_common()
504 I915_READ_CTL(engine), in init_ring_common()
505 I915_READ_HEAD(engine), in init_ring_common()
506 I915_READ_TAIL(engine), in init_ring_common()
507 I915_READ_START(engine)); in init_ring_common()
509 if (!stop_ring(engine)) { in init_ring_common()
512 engine->name, in init_ring_common()
513 I915_READ_CTL(engine), in init_ring_common()
514 I915_READ_HEAD(engine), in init_ring_common()
515 I915_READ_TAIL(engine), in init_ring_common()
516 I915_READ_START(engine)); in init_ring_common()
523 ring_setup_phys_status_page(engine); in init_ring_common()
525 intel_ring_setup_status_page(engine); in init_ring_common()
527 intel_engine_reset_breadcrumbs(engine); in init_ring_common()
530 I915_READ_HEAD(engine); in init_ring_common()
536 I915_WRITE_START(engine, i915_ggtt_offset(ring->vma)); in init_ring_common()
539 if (I915_READ_HEAD(engine)) in init_ring_common()
541 engine->name, I915_READ_HEAD(engine)); in init_ring_common()
548 I915_WRITE_HEAD(engine, ring->head); in init_ring_common()
549 I915_WRITE_TAIL(engine, ring->tail); in init_ring_common()
550 (void)I915_READ_TAIL(engine); in init_ring_common()
552 I915_WRITE_CTL(engine, RING_CTL_SIZE(ring->size) | RING_VALID); in init_ring_common()
555 if (intel_wait_for_register(dev_priv, RING_CTL(engine->mmio_base), in init_ring_common()
560 engine->name, in init_ring_common()
561 I915_READ_CTL(engine), in init_ring_common()
562 I915_READ_CTL(engine) & RING_VALID, in init_ring_common()
563 I915_READ_HEAD(engine), ring->head, in init_ring_common()
564 I915_READ_TAIL(engine), ring->tail, in init_ring_common()
565 I915_READ_START(engine), in init_ring_common()
572 I915_WRITE_MODE(engine, _MASKED_BIT_DISABLE(STOP_RING)); in init_ring_common()
580 static struct i915_request *reset_prepare(struct intel_engine_cs *engine) in reset_prepare() argument
582 intel_engine_stop_cs(engine); in reset_prepare()
584 if (engine->irq_seqno_barrier) in reset_prepare()
585 engine->irq_seqno_barrier(engine); in reset_prepare()
587 return i915_gem_find_active_request(engine); in reset_prepare()
604 static void reset_ring(struct intel_engine_cs *engine, struct i915_request *rq) in reset_ring() argument
606 GEM_TRACE("%s seqno=%x\n", engine->name, rq ? rq->global_seqno : 0); in reset_ring()
630 static void reset_finish(struct intel_engine_cs *engine) in reset_finish() argument
649 static int init_render_ring(struct intel_engine_cs *engine) in init_render_ring() argument
651 struct drm_i915_private *dev_priv = engine->i915; in init_render_ring()
652 int ret = init_ring_common(engine); in init_render_ring()
656 intel_whitelist_workarounds_apply(engine); in init_render_ring()
697 I915_WRITE_IMR(engine, ~engine->irq_keep_mask); in init_render_ring()
705 struct intel_engine_cs *engine; in gen6_signal() local
709 for_each_engine(engine, dev_priv, id) { in gen6_signal()
712 if (!(BIT(engine->hw_id) & GEN6_SEMAPHORES_MASK)) in gen6_signal()
715 mbox_reg = rq->engine->semaphore.mbox.signal[engine->hw_id]; in gen6_signal()
729 static void cancel_requests(struct intel_engine_cs *engine) in cancel_requests() argument
734 spin_lock_irqsave(&engine->timeline.lock, flags); in cancel_requests()
737 list_for_each_entry(request, &engine->timeline.requests, link) { in cancel_requests()
744 spin_unlock_irqrestore(&engine->timeline.lock, flags); in cancel_requests()
753 I915_WRITE_TAIL(request->engine, in i9xx_submit_request()
772 return i9xx_emit_breadcrumb(rq, rq->engine->semaphore.signal(rq, cs)); in gen6_sema_emit_breadcrumb()
781 u32 wait_mbox = signal->engine->semaphore.mbox.wait[rq->engine->hw_id]; in gen6_ring_sync_to()
804 gen5_seqno_barrier(struct intel_engine_cs *engine) in gen5_seqno_barrier() argument
822 gen6_seqno_barrier(struct intel_engine_cs *engine) in gen6_seqno_barrier() argument
824 struct drm_i915_private *dev_priv = engine->i915; in gen6_seqno_barrier()
842 POSTING_READ_FW(RING_ACTHD(engine->mmio_base)); in gen6_seqno_barrier()
847 gen5_irq_enable(struct intel_engine_cs *engine) in gen5_irq_enable() argument
849 gen5_enable_gt_irq(engine->i915, engine->irq_enable_mask); in gen5_irq_enable()
853 gen5_irq_disable(struct intel_engine_cs *engine) in gen5_irq_disable() argument
855 gen5_disable_gt_irq(engine->i915, engine->irq_enable_mask); in gen5_irq_disable()
859 i9xx_irq_enable(struct intel_engine_cs *engine) in i9xx_irq_enable() argument
861 struct drm_i915_private *dev_priv = engine->i915; in i9xx_irq_enable()
863 dev_priv->irq_mask &= ~engine->irq_enable_mask; in i9xx_irq_enable()
865 POSTING_READ_FW(RING_IMR(engine->mmio_base)); in i9xx_irq_enable()
869 i9xx_irq_disable(struct intel_engine_cs *engine) in i9xx_irq_disable() argument
871 struct drm_i915_private *dev_priv = engine->i915; in i9xx_irq_disable()
873 dev_priv->irq_mask |= engine->irq_enable_mask; in i9xx_irq_disable()
878 i8xx_irq_enable(struct intel_engine_cs *engine) in i8xx_irq_enable() argument
880 struct drm_i915_private *dev_priv = engine->i915; in i8xx_irq_enable()
882 dev_priv->irq_mask &= ~engine->irq_enable_mask; in i8xx_irq_enable()
884 POSTING_READ16(RING_IMR(engine->mmio_base)); in i8xx_irq_enable()
888 i8xx_irq_disable(struct intel_engine_cs *engine) in i8xx_irq_disable() argument
890 struct drm_i915_private *dev_priv = engine->i915; in i8xx_irq_disable()
892 dev_priv->irq_mask |= engine->irq_enable_mask; in i8xx_irq_disable()
912 gen6_irq_enable(struct intel_engine_cs *engine) in gen6_irq_enable() argument
914 struct drm_i915_private *dev_priv = engine->i915; in gen6_irq_enable()
916 I915_WRITE_IMR(engine, in gen6_irq_enable()
917 ~(engine->irq_enable_mask | in gen6_irq_enable()
918 engine->irq_keep_mask)); in gen6_irq_enable()
919 gen5_enable_gt_irq(dev_priv, engine->irq_enable_mask); in gen6_irq_enable()
923 gen6_irq_disable(struct intel_engine_cs *engine) in gen6_irq_disable() argument
925 struct drm_i915_private *dev_priv = engine->i915; in gen6_irq_disable()
927 I915_WRITE_IMR(engine, ~engine->irq_keep_mask); in gen6_irq_disable()
928 gen5_disable_gt_irq(dev_priv, engine->irq_enable_mask); in gen6_irq_disable()
932 hsw_vebox_irq_enable(struct intel_engine_cs *engine) in hsw_vebox_irq_enable() argument
934 struct drm_i915_private *dev_priv = engine->i915; in hsw_vebox_irq_enable()
936 I915_WRITE_IMR(engine, ~engine->irq_enable_mask); in hsw_vebox_irq_enable()
937 gen6_unmask_pm_irq(dev_priv, engine->irq_enable_mask); in hsw_vebox_irq_enable()
941 hsw_vebox_irq_disable(struct intel_engine_cs *engine) in hsw_vebox_irq_disable() argument
943 struct drm_i915_private *dev_priv = engine->i915; in hsw_vebox_irq_disable()
945 I915_WRITE_IMR(engine, ~0); in hsw_vebox_irq_disable()
946 gen6_mask_pm_irq(dev_priv, engine->irq_enable_mask); in hsw_vebox_irq_disable()
977 u32 *cs, cs_offset = i915_ggtt_offset(rq->engine->scratch); in i830_emit_bb_start()
1163 intel_engine_create_ring(struct intel_engine_cs *engine, in intel_engine_create_ring() argument
1172 GEM_BUG_ON(timeline == &engine->timeline); in intel_engine_create_ring()
1173 lockdep_assert_held(&engine->i915->drm.struct_mutex); in intel_engine_create_ring()
1188 if (IS_I830(engine->i915) || IS_I845G(engine->i915)) in intel_engine_create_ring()
1193 vma = intel_ring_create_vma(engine->i915, size); in intel_engine_create_ring()
1302 alloc_context_vma(struct intel_engine_cs *engine) in alloc_context_vma() argument
1304 struct drm_i915_private *i915 = engine->i915; in alloc_context_vma()
1309 obj = i915_gem_object_create(i915, engine->context_size); in alloc_context_vma()
1313 if (engine->default_state) { in alloc_context_vma()
1322 defaults = i915_gem_object_pin_map(engine->default_state, in alloc_context_vma()
1329 memcpy(vaddr, defaults, engine->context_size); in alloc_context_vma()
1331 i915_gem_object_unpin_map(engine->default_state); in alloc_context_vma()
1371 __ring_context_pin(struct intel_engine_cs *engine, in __ring_context_pin() argument
1377 if (!ce->state && engine->context_size) { in __ring_context_pin()
1380 vma = alloc_context_vma(engine); in __ring_context_pin()
1400 GEM_BUG_ON(!engine->buffer); in __ring_context_pin()
1401 ce->ring = engine->buffer; in __ring_context_pin()
1418 intel_ring_context_pin(struct intel_engine_cs *engine, in intel_ring_context_pin() argument
1421 struct intel_context *ce = to_intel_context(ctx, engine); in intel_ring_context_pin()
1431 return __ring_context_pin(engine, ctx, ce); in intel_ring_context_pin()
1434 static int intel_init_ring_buffer(struct intel_engine_cs *engine) in intel_init_ring_buffer() argument
1441 intel_engine_setup_common(engine); in intel_init_ring_buffer()
1443 timeline = i915_timeline_create(engine->i915, engine->name); in intel_init_ring_buffer()
1449 ring = intel_engine_create_ring(engine, timeline, 32 * PAGE_SIZE); in intel_init_ring_buffer()
1457 err = intel_ring_pin(ring, engine->i915, I915_GTT_PAGE_SIZE); in intel_init_ring_buffer()
1461 GEM_BUG_ON(engine->buffer); in intel_init_ring_buffer()
1462 engine->buffer = ring; in intel_init_ring_buffer()
1465 if (HAS_BROKEN_CS_TLB(engine->i915)) in intel_init_ring_buffer()
1467 err = intel_engine_create_scratch(engine, size); in intel_init_ring_buffer()
1471 err = intel_engine_init_common(engine); in intel_init_ring_buffer()
1478 intel_engine_cleanup_scratch(engine); in intel_init_ring_buffer()
1484 intel_engine_cleanup_common(engine); in intel_init_ring_buffer()
1488 void intel_engine_cleanup(struct intel_engine_cs *engine) in intel_engine_cleanup() argument
1490 struct drm_i915_private *dev_priv = engine->i915; in intel_engine_cleanup()
1493 (I915_READ_MODE(engine) & MODE_IDLE) == 0); in intel_engine_cleanup()
1495 intel_ring_unpin(engine->buffer); in intel_engine_cleanup()
1496 intel_ring_free(engine->buffer); in intel_engine_cleanup()
1498 if (engine->cleanup) in intel_engine_cleanup()
1499 engine->cleanup(engine); in intel_engine_cleanup()
1501 intel_engine_cleanup_common(engine); in intel_engine_cleanup()
1503 dev_priv->engine[engine->id] = NULL; in intel_engine_cleanup()
1504 kfree(engine); in intel_engine_cleanup()
1509 struct intel_engine_cs *engine; in intel_legacy_submission_resume() local
1513 for_each_engine(engine, dev_priv, id) in intel_legacy_submission_resume()
1514 intel_ring_reset(engine->buffer, 0); in intel_legacy_submission_resume()
1520 const struct intel_engine_cs * const engine = rq->engine; in load_pd_dir() local
1528 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_DCLV(engine)); in load_pd_dir()
1532 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); in load_pd_dir()
1542 const struct intel_engine_cs * const engine = rq->engine; in flush_pd_dir() local
1551 *cs++ = i915_mmio_reg_offset(RING_PP_DIR_BASE(engine)); in flush_pd_dir()
1552 *cs++ = i915_ggtt_offset(engine->scratch); in flush_pd_dir()
1562 struct intel_engine_cs *engine = rq->engine; in mi_set_context() local
1602 if (signaller == engine) in mi_set_context()
1628 engine)->state) | in mi_set_context()
1649 if (signaller == engine) in mi_set_context()
1661 *cs++ = i915_ggtt_offset(engine->scratch); in mi_set_context()
1702 struct intel_engine_cs *engine = rq->engine; in switch_context() local
1717 if (intel_engine_flag(engine) & ppgtt->pd_dirty_rings) { in switch_context()
1718 unwind_mm = intel_engine_flag(engine); in switch_context()
1725 GEM_BUG_ON(engine->id != RCS); in switch_context()
2001 * Bspec vol 1c.5 - video engine command streamer: in gen6_bsd_ring_flush()
2079 * Bspec vol 1c.3 - blitter engine command streamer: in gen6_ring_flush()
2096 struct intel_engine_cs *engine) in intel_ring_init_semaphores() argument
2104 engine->semaphore.sync_to = gen6_ring_sync_to; in intel_ring_init_semaphores()
2105 engine->semaphore.signal = gen6_signal; in intel_ring_init_semaphores()
2142 if (i == engine->hw_id) { in intel_ring_init_semaphores()
2146 wait_mbox = sem_data[engine->hw_id][i].wait_mbox; in intel_ring_init_semaphores()
2147 mbox_reg = sem_data[engine->hw_id][i].mbox_reg; in intel_ring_init_semaphores()
2150 engine->semaphore.mbox.wait[i] = wait_mbox; in intel_ring_init_semaphores()
2151 engine->semaphore.mbox.signal[i] = mbox_reg; in intel_ring_init_semaphores()
2156 struct intel_engine_cs *engine) in intel_ring_init_irq() argument
2159 engine->irq_enable = gen6_irq_enable; in intel_ring_init_irq()
2160 engine->irq_disable = gen6_irq_disable; in intel_ring_init_irq()
2161 engine->irq_seqno_barrier = gen6_seqno_barrier; in intel_ring_init_irq()
2163 engine->irq_enable = gen5_irq_enable; in intel_ring_init_irq()
2164 engine->irq_disable = gen5_irq_disable; in intel_ring_init_irq()
2165 engine->irq_seqno_barrier = gen5_seqno_barrier; in intel_ring_init_irq()
2167 engine->irq_enable = i9xx_irq_enable; in intel_ring_init_irq()
2168 engine->irq_disable = i9xx_irq_disable; in intel_ring_init_irq()
2170 engine->irq_enable = i8xx_irq_enable; in intel_ring_init_irq()
2171 engine->irq_disable = i8xx_irq_disable; in intel_ring_init_irq()
2175 static void i9xx_set_default_submission(struct intel_engine_cs *engine) in i9xx_set_default_submission() argument
2177 engine->submit_request = i9xx_submit_request; in i9xx_set_default_submission()
2178 engine->cancel_requests = cancel_requests; in i9xx_set_default_submission()
2180 engine->park = NULL; in i9xx_set_default_submission()
2181 engine->unpark = NULL; in i9xx_set_default_submission()
2184 static void gen6_bsd_set_default_submission(struct intel_engine_cs *engine) in gen6_bsd_set_default_submission() argument
2186 i9xx_set_default_submission(engine); in gen6_bsd_set_default_submission()
2187 engine->submit_request = gen6_bsd_submit_request; in gen6_bsd_set_default_submission()
2191 struct intel_engine_cs *engine) in intel_ring_default_vfuncs() argument
2196 intel_ring_init_irq(dev_priv, engine); in intel_ring_default_vfuncs()
2197 intel_ring_init_semaphores(dev_priv, engine); in intel_ring_default_vfuncs()
2199 engine->init_hw = init_ring_common; in intel_ring_default_vfuncs()
2200 engine->reset.prepare = reset_prepare; in intel_ring_default_vfuncs()
2201 engine->reset.reset = reset_ring; in intel_ring_default_vfuncs()
2202 engine->reset.finish = reset_finish; in intel_ring_default_vfuncs()
2204 engine->context_pin = intel_ring_context_pin; in intel_ring_default_vfuncs()
2205 engine->request_alloc = ring_request_alloc; in intel_ring_default_vfuncs()
2207 engine->emit_breadcrumb = i9xx_emit_breadcrumb; in intel_ring_default_vfuncs()
2208 engine->emit_breadcrumb_sz = i9xx_emit_breadcrumb_sz; in intel_ring_default_vfuncs()
2212 engine->emit_breadcrumb = gen6_sema_emit_breadcrumb; in intel_ring_default_vfuncs()
2215 engine->emit_breadcrumb_sz += num_rings * 3; in intel_ring_default_vfuncs()
2217 engine->emit_breadcrumb_sz++; in intel_ring_default_vfuncs()
2220 engine->set_default_submission = i9xx_set_default_submission; in intel_ring_default_vfuncs()
2223 engine->emit_bb_start = gen6_emit_bb_start; in intel_ring_default_vfuncs()
2225 engine->emit_bb_start = i965_emit_bb_start; in intel_ring_default_vfuncs()
2227 engine->emit_bb_start = i830_emit_bb_start; in intel_ring_default_vfuncs()
2229 engine->emit_bb_start = i915_emit_bb_start; in intel_ring_default_vfuncs()
2232 int intel_init_render_ring_buffer(struct intel_engine_cs *engine) in intel_init_render_ring_buffer() argument
2234 struct drm_i915_private *dev_priv = engine->i915; in intel_init_render_ring_buffer()
2237 intel_ring_default_vfuncs(dev_priv, engine); in intel_init_render_ring_buffer()
2240 engine->irq_keep_mask = GT_RENDER_L3_PARITY_ERROR_INTERRUPT; in intel_init_render_ring_buffer()
2242 engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT; in intel_init_render_ring_buffer()
2245 engine->init_context = intel_rcs_ctx_init; in intel_init_render_ring_buffer()
2246 engine->emit_flush = gen7_render_ring_flush; in intel_init_render_ring_buffer()
2248 engine->emit_flush = gen6_render_ring_flush; in intel_init_render_ring_buffer()
2250 engine->emit_flush = gen4_render_ring_flush; in intel_init_render_ring_buffer()
2253 engine->emit_flush = gen2_render_ring_flush; in intel_init_render_ring_buffer()
2255 engine->emit_flush = gen4_render_ring_flush; in intel_init_render_ring_buffer()
2256 engine->irq_enable_mask = I915_USER_INTERRUPT; in intel_init_render_ring_buffer()
2260 engine->emit_bb_start = hsw_emit_bb_start; in intel_init_render_ring_buffer()
2262 engine->init_hw = init_render_ring; in intel_init_render_ring_buffer()
2264 ret = intel_init_ring_buffer(engine); in intel_init_render_ring_buffer()
2271 int intel_init_bsd_ring_buffer(struct intel_engine_cs *engine) in intel_init_bsd_ring_buffer() argument
2273 struct drm_i915_private *dev_priv = engine->i915; in intel_init_bsd_ring_buffer()
2275 intel_ring_default_vfuncs(dev_priv, engine); in intel_init_bsd_ring_buffer()
2280 engine->set_default_submission = gen6_bsd_set_default_submission; in intel_init_bsd_ring_buffer()
2281 engine->emit_flush = gen6_bsd_ring_flush; in intel_init_bsd_ring_buffer()
2282 engine->irq_enable_mask = GT_BSD_USER_INTERRUPT; in intel_init_bsd_ring_buffer()
2284 engine->emit_flush = bsd_ring_flush; in intel_init_bsd_ring_buffer()
2286 engine->irq_enable_mask = ILK_BSD_USER_INTERRUPT; in intel_init_bsd_ring_buffer()
2288 engine->irq_enable_mask = I915_BSD_USER_INTERRUPT; in intel_init_bsd_ring_buffer()
2291 return intel_init_ring_buffer(engine); in intel_init_bsd_ring_buffer()
2294 int intel_init_blt_ring_buffer(struct intel_engine_cs *engine) in intel_init_blt_ring_buffer() argument
2296 struct drm_i915_private *dev_priv = engine->i915; in intel_init_blt_ring_buffer()
2298 intel_ring_default_vfuncs(dev_priv, engine); in intel_init_blt_ring_buffer()
2300 engine->emit_flush = gen6_ring_flush; in intel_init_blt_ring_buffer()
2301 engine->irq_enable_mask = GT_BLT_USER_INTERRUPT; in intel_init_blt_ring_buffer()
2303 return intel_init_ring_buffer(engine); in intel_init_blt_ring_buffer()
2306 int intel_init_vebox_ring_buffer(struct intel_engine_cs *engine) in intel_init_vebox_ring_buffer() argument
2308 struct drm_i915_private *dev_priv = engine->i915; in intel_init_vebox_ring_buffer()
2310 intel_ring_default_vfuncs(dev_priv, engine); in intel_init_vebox_ring_buffer()
2312 engine->emit_flush = gen6_ring_flush; in intel_init_vebox_ring_buffer()
2313 engine->irq_enable_mask = PM_VEBOX_USER_INTERRUPT; in intel_init_vebox_ring_buffer()
2314 engine->irq_enable = hsw_vebox_irq_enable; in intel_init_vebox_ring_buffer()
2315 engine->irq_disable = hsw_vebox_irq_disable; in intel_init_vebox_ring_buffer()
2317 return intel_init_ring_buffer(engine); in intel_init_vebox_ring_buffer()