Lines Matching +full:0 +full:x00000044
50 NON_BURST_SYNCH_PULSE = 0,
56 VID_DST_FORMAT_RGB565 = 0,
63 SWAP_RGB = 0,
72 TRIGGER_NONE = 0,
81 CMD_DST_FORMAT_RGB111 = 0,
90 LANE_SWAP_0123 = 0,
100 #define DSI_IRQ_CMD_DMA_DONE 0x00000001
101 #define DSI_IRQ_MASK_CMD_DMA_DONE 0x00000002
102 #define DSI_IRQ_CMD_MDP_DONE 0x00000100
103 #define DSI_IRQ_MASK_CMD_MDP_DONE 0x00000200
104 #define DSI_IRQ_VIDEO_DONE 0x00010000
105 #define DSI_IRQ_MASK_VIDEO_DONE 0x00020000
106 #define DSI_IRQ_BTA_DONE 0x00100000
107 #define DSI_IRQ_MASK_BTA_DONE 0x00200000
108 #define DSI_IRQ_ERROR 0x01000000
109 #define DSI_IRQ_MASK_ERROR 0x02000000
110 #define REG_DSI_6G_HW_VERSION 0x00000000
111 #define DSI_6G_HW_VERSION_MAJOR__MASK 0xf0000000
117 #define DSI_6G_HW_VERSION_MINOR__MASK 0x0fff0000
123 #define DSI_6G_HW_VERSION_STEP__MASK 0x0000ffff
124 #define DSI_6G_HW_VERSION_STEP__SHIFT 0
130 #define REG_DSI_CTRL 0x00000000
131 #define DSI_CTRL_ENABLE 0x00000001
132 #define DSI_CTRL_VID_MODE_EN 0x00000002
133 #define DSI_CTRL_CMD_MODE_EN 0x00000004
134 #define DSI_CTRL_LANE0 0x00000010
135 #define DSI_CTRL_LANE1 0x00000020
136 #define DSI_CTRL_LANE2 0x00000040
137 #define DSI_CTRL_LANE3 0x00000080
138 #define DSI_CTRL_CLK_EN 0x00000100
139 #define DSI_CTRL_ECC_CHECK 0x00100000
140 #define DSI_CTRL_CRC_CHECK 0x01000000
142 #define REG_DSI_STATUS0 0x00000004
143 #define DSI_STATUS0_CMD_MODE_ENGINE_BUSY 0x00000001
144 #define DSI_STATUS0_CMD_MODE_DMA_BUSY 0x00000002
145 #define DSI_STATUS0_CMD_MODE_MDP_BUSY 0x00000004
146 #define DSI_STATUS0_VIDEO_MODE_ENGINE_BUSY 0x00000008
147 #define DSI_STATUS0_DSI_BUSY 0x00000010
148 #define DSI_STATUS0_INTERLEAVE_OP_CONTENTION 0x80000000
150 #define REG_DSI_FIFO_STATUS 0x00000008
151 #define DSI_FIFO_STATUS_CMD_MDP_FIFO_UNDERFLOW 0x00000080
153 #define REG_DSI_VID_CFG0 0x0000000c
154 #define DSI_VID_CFG0_VIRT_CHANNEL__MASK 0x00000003
155 #define DSI_VID_CFG0_VIRT_CHANNEL__SHIFT 0
160 #define DSI_VID_CFG0_DST_FORMAT__MASK 0x00000030
166 #define DSI_VID_CFG0_TRAFFIC_MODE__MASK 0x00000300
172 #define DSI_VID_CFG0_BLLP_POWER_STOP 0x00001000
173 #define DSI_VID_CFG0_EOF_BLLP_POWER_STOP 0x00008000
174 #define DSI_VID_CFG0_HSA_POWER_STOP 0x00010000
175 #define DSI_VID_CFG0_HBP_POWER_STOP 0x00100000
176 #define DSI_VID_CFG0_HFP_POWER_STOP 0x01000000
177 #define DSI_VID_CFG0_PULSE_MODE_HSA_HE 0x10000000
179 #define REG_DSI_VID_CFG1 0x0000001c
180 #define DSI_VID_CFG1_R_SEL 0x00000001
181 #define DSI_VID_CFG1_G_SEL 0x00000010
182 #define DSI_VID_CFG1_B_SEL 0x00000100
183 #define DSI_VID_CFG1_RGB_SWAP__MASK 0x00007000
190 #define REG_DSI_ACTIVE_H 0x00000020
191 #define DSI_ACTIVE_H_START__MASK 0x00000fff
192 #define DSI_ACTIVE_H_START__SHIFT 0
197 #define DSI_ACTIVE_H_END__MASK 0x0fff0000
204 #define REG_DSI_ACTIVE_V 0x00000024
205 #define DSI_ACTIVE_V_START__MASK 0x00000fff
206 #define DSI_ACTIVE_V_START__SHIFT 0
211 #define DSI_ACTIVE_V_END__MASK 0x0fff0000
218 #define REG_DSI_TOTAL 0x00000028
219 #define DSI_TOTAL_H_TOTAL__MASK 0x00000fff
220 #define DSI_TOTAL_H_TOTAL__SHIFT 0
225 #define DSI_TOTAL_V_TOTAL__MASK 0x0fff0000
232 #define REG_DSI_ACTIVE_HSYNC 0x0000002c
233 #define DSI_ACTIVE_HSYNC_START__MASK 0x00000fff
234 #define DSI_ACTIVE_HSYNC_START__SHIFT 0
239 #define DSI_ACTIVE_HSYNC_END__MASK 0x0fff0000
246 #define REG_DSI_ACTIVE_VSYNC_HPOS 0x00000030
247 #define DSI_ACTIVE_VSYNC_HPOS_START__MASK 0x00000fff
248 #define DSI_ACTIVE_VSYNC_HPOS_START__SHIFT 0
253 #define DSI_ACTIVE_VSYNC_HPOS_END__MASK 0x0fff0000
260 #define REG_DSI_ACTIVE_VSYNC_VPOS 0x00000034
261 #define DSI_ACTIVE_VSYNC_VPOS_START__MASK 0x00000fff
262 #define DSI_ACTIVE_VSYNC_VPOS_START__SHIFT 0
267 #define DSI_ACTIVE_VSYNC_VPOS_END__MASK 0x0fff0000
274 #define REG_DSI_CMD_DMA_CTRL 0x00000038
275 #define DSI_CMD_DMA_CTRL_BROADCAST_EN 0x80000000
276 #define DSI_CMD_DMA_CTRL_FROM_FRAME_BUFFER 0x10000000
277 #define DSI_CMD_DMA_CTRL_LOW_POWER 0x04000000
279 #define REG_DSI_CMD_CFG0 0x0000003c
280 #define DSI_CMD_CFG0_DST_FORMAT__MASK 0x0000000f
281 #define DSI_CMD_CFG0_DST_FORMAT__SHIFT 0
286 #define DSI_CMD_CFG0_R_SEL 0x00000010
287 #define DSI_CMD_CFG0_G_SEL 0x00000100
288 #define DSI_CMD_CFG0_B_SEL 0x00001000
289 #define DSI_CMD_CFG0_INTERLEAVE_MAX__MASK 0x00f00000
295 #define DSI_CMD_CFG0_RGB_SWAP__MASK 0x00070000
302 #define REG_DSI_CMD_CFG1 0x00000040
303 #define DSI_CMD_CFG1_WR_MEM_START__MASK 0x000000ff
304 #define DSI_CMD_CFG1_WR_MEM_START__SHIFT 0
309 #define DSI_CMD_CFG1_WR_MEM_CONTINUE__MASK 0x0000ff00
315 #define DSI_CMD_CFG1_INSERT_DCS_COMMAND 0x00010000
317 #define REG_DSI_DMA_BASE 0x00000044
319 #define REG_DSI_DMA_LEN 0x00000048
321 #define REG_DSI_CMD_MDP_STREAM_CTRL 0x00000054
322 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__MASK 0x0000003f
323 #define DSI_CMD_MDP_STREAM_CTRL_DATA_TYPE__SHIFT 0
328 #define DSI_CMD_MDP_STREAM_CTRL_VIRTUAL_CHANNEL__MASK 0x00000300
334 #define DSI_CMD_MDP_STREAM_CTRL_WORD_COUNT__MASK 0xffff0000
341 #define REG_DSI_CMD_MDP_STREAM_TOTAL 0x00000058
342 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__MASK 0x00000fff
343 #define DSI_CMD_MDP_STREAM_TOTAL_H_TOTAL__SHIFT 0
348 #define DSI_CMD_MDP_STREAM_TOTAL_V_TOTAL__MASK 0x0fff0000
355 #define REG_DSI_ACK_ERR_STATUS 0x00000064
357 static inline uint32_t REG_DSI_RDBK(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK()
359 static inline uint32_t REG_DSI_RDBK_DATA(uint32_t i0) { return 0x00000068 + 0x4*i0; } in REG_DSI_RDBK_DATA()
361 #define REG_DSI_TRIG_CTRL 0x00000080
362 #define DSI_TRIG_CTRL_DMA_TRIGGER__MASK 0x00000007
363 #define DSI_TRIG_CTRL_DMA_TRIGGER__SHIFT 0
368 #define DSI_TRIG_CTRL_MDP_TRIGGER__MASK 0x00000070
374 #define DSI_TRIG_CTRL_STREAM__MASK 0x00000300
380 #define DSI_TRIG_CTRL_BLOCK_DMA_WITHIN_FRAME 0x00001000
381 #define DSI_TRIG_CTRL_TE 0x80000000
383 #define REG_DSI_TRIG_DMA 0x0000008c
385 #define REG_DSI_DLN0_PHY_ERR 0x000000b0
386 #define DSI_DLN0_PHY_ERR_DLN0_ERR_ESC 0x00000001
387 #define DSI_DLN0_PHY_ERR_DLN0_ERR_SYNC_ESC 0x00000010
388 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTROL 0x00000100
389 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP0 0x00001000
390 #define DSI_DLN0_PHY_ERR_DLN0_ERR_CONTENTION_LP1 0x00010000
392 #define REG_DSI_TIMEOUT_STATUS 0x000000bc
394 #define REG_DSI_CLKOUT_TIMING_CTRL 0x000000c0
395 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__MASK 0x0000003f
396 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_PRE__SHIFT 0
401 #define DSI_CLKOUT_TIMING_CTRL_T_CLK_POST__MASK 0x00003f00
408 #define REG_DSI_EOT_PACKET_CTRL 0x000000c8
409 #define DSI_EOT_PACKET_CTRL_TX_EOT_APPEND 0x00000001
410 #define DSI_EOT_PACKET_CTRL_RX_EOT_IGNORE 0x00000010
412 #define REG_DSI_LANE_CTRL 0x000000a8
413 #define DSI_LANE_CTRL_CLKLN_HS_FORCE_REQUEST 0x10000000
415 #define REG_DSI_LANE_SWAP_CTRL 0x000000ac
416 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__MASK 0x00000007
417 #define DSI_LANE_SWAP_CTRL_DLN_SWAP_SEL__SHIFT 0
423 #define REG_DSI_ERR_INT_MASK0 0x00000108
425 #define REG_DSI_INTR_CTRL 0x0000010c
427 #define REG_DSI_RESET 0x00000114
429 #define REG_DSI_CLK_CTRL 0x00000118
430 #define DSI_CLK_CTRL_AHBS_HCLK_ON 0x00000001
431 #define DSI_CLK_CTRL_AHBM_SCLK_ON 0x00000002
432 #define DSI_CLK_CTRL_PCLK_ON 0x00000004
433 #define DSI_CLK_CTRL_DSICLK_ON 0x00000008
434 #define DSI_CLK_CTRL_BYTECLK_ON 0x00000010
435 #define DSI_CLK_CTRL_ESCCLK_ON 0x00000020
436 #define DSI_CLK_CTRL_FORCE_ON_DYN_AHBM_HCLK 0x00000200
438 #define REG_DSI_CLK_STATUS 0x0000011c
439 #define DSI_CLK_STATUS_PLL_UNLOCKED 0x00010000
441 #define REG_DSI_PHY_RESET 0x00000128
442 #define DSI_PHY_RESET_RESET 0x00000001
444 #define REG_DSI_T_CLK_PRE_EXTEND 0x0000017c
445 #define DSI_T_CLK_PRE_EXTEND_INC_BY_2_BYTECLK 0x00000001
447 #define REG_DSI_RDBK_DATA_CTRL 0x000001d0
448 #define DSI_RDBK_DATA_CTRL_COUNT__MASK 0x00ff0000
454 #define DSI_RDBK_DATA_CTRL_CLR 0x00000001
456 #define REG_DSI_VERSION 0x000001f0
457 #define DSI_VERSION_MAJOR__MASK 0xff000000
464 #define REG_DSI_PHY_PLL_CTRL_0 0x00000200
465 #define DSI_PHY_PLL_CTRL_0_ENABLE 0x00000001
467 #define REG_DSI_PHY_PLL_CTRL_1 0x00000204
469 #define REG_DSI_PHY_PLL_CTRL_2 0x00000208
471 #define REG_DSI_PHY_PLL_CTRL_3 0x0000020c
473 #define REG_DSI_PHY_PLL_CTRL_4 0x00000210
475 #define REG_DSI_PHY_PLL_CTRL_5 0x00000214
477 #define REG_DSI_PHY_PLL_CTRL_6 0x00000218
479 #define REG_DSI_PHY_PLL_CTRL_7 0x0000021c
481 #define REG_DSI_PHY_PLL_CTRL_8 0x00000220
483 #define REG_DSI_PHY_PLL_CTRL_9 0x00000224
485 #define REG_DSI_PHY_PLL_CTRL_10 0x00000228
487 #define REG_DSI_PHY_PLL_CTRL_11 0x0000022c
489 #define REG_DSI_PHY_PLL_CTRL_12 0x00000230
491 #define REG_DSI_PHY_PLL_CTRL_13 0x00000234
493 #define REG_DSI_PHY_PLL_CTRL_14 0x00000238
495 #define REG_DSI_PHY_PLL_CTRL_15 0x0000023c
497 #define REG_DSI_PHY_PLL_CTRL_16 0x00000240
499 #define REG_DSI_PHY_PLL_CTRL_17 0x00000244
501 #define REG_DSI_PHY_PLL_CTRL_18 0x00000248
503 #define REG_DSI_PHY_PLL_CTRL_19 0x0000024c
505 #define REG_DSI_PHY_PLL_CTRL_20 0x00000250
507 #define REG_DSI_PHY_PLL_STATUS 0x00000280
508 #define DSI_PHY_PLL_STATUS_PLL_BUSY 0x00000001
510 #define REG_DSI_8x60_PHY_TPA_CTRL_1 0x00000258
512 #define REG_DSI_8x60_PHY_TPA_CTRL_2 0x0000025c
514 #define REG_DSI_8x60_PHY_TIMING_CTRL_0 0x00000260
516 #define REG_DSI_8x60_PHY_TIMING_CTRL_1 0x00000264
518 #define REG_DSI_8x60_PHY_TIMING_CTRL_2 0x00000268
520 #define REG_DSI_8x60_PHY_TIMING_CTRL_3 0x0000026c
522 #define REG_DSI_8x60_PHY_TIMING_CTRL_4 0x00000270
524 #define REG_DSI_8x60_PHY_TIMING_CTRL_5 0x00000274
526 #define REG_DSI_8x60_PHY_TIMING_CTRL_6 0x00000278
528 #define REG_DSI_8x60_PHY_TIMING_CTRL_7 0x0000027c
530 #define REG_DSI_8x60_PHY_TIMING_CTRL_8 0x00000280
532 #define REG_DSI_8x60_PHY_TIMING_CTRL_9 0x00000284
534 #define REG_DSI_8x60_PHY_TIMING_CTRL_10 0x00000288
536 #define REG_DSI_8x60_PHY_TIMING_CTRL_11 0x0000028c
538 #define REG_DSI_8x60_PHY_CTRL_0 0x00000290
540 #define REG_DSI_8x60_PHY_CTRL_1 0x00000294
542 #define REG_DSI_8x60_PHY_CTRL_2 0x00000298
544 #define REG_DSI_8x60_PHY_CTRL_3 0x0000029c
546 #define REG_DSI_8x60_PHY_STRENGTH_0 0x000002a0
548 #define REG_DSI_8x60_PHY_STRENGTH_1 0x000002a4
550 #define REG_DSI_8x60_PHY_STRENGTH_2 0x000002a8
552 #define REG_DSI_8x60_PHY_STRENGTH_3 0x000002ac
554 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_0 0x000002cc
556 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_1 0x000002d0
558 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_2 0x000002d4
560 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_3 0x000002d8
562 #define REG_DSI_8x60_PHY_REGULATOR_CTRL_4 0x000002dc
564 #define REG_DSI_8x60_PHY_CAL_HW_TRIGGER 0x000000f0
566 #define REG_DSI_8x60_PHY_CAL_CTRL 0x000000f4
568 #define REG_DSI_8x60_PHY_CAL_STATUS 0x000000fc
569 #define DSI_8x60_PHY_CAL_STATUS_CAL_BUSY 0x10000000
571 static inline uint32_t REG_DSI_28nm_8960_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN()
573 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_0()
575 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_1()
577 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_8960_PHY_LN_CFG_2()
579 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x0000000c + 0x… in REG_DSI_28nm_8960_PHY_LN_TEST_DATAPATH()
581 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x00000014 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_0()
583 static inline uint32_t REG_DSI_28nm_8960_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000018 + 0x40*… in REG_DSI_28nm_8960_PHY_LN_TEST_STR_1()
585 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_0 0x00000100
587 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_1 0x00000104
589 #define REG_DSI_28nm_8960_PHY_LNCK_CFG_2 0x00000108
591 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_DATAPATH 0x0000010c
593 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR0 0x00000114
595 #define REG_DSI_28nm_8960_PHY_LNCK_TEST_STR1 0x00000118
597 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_0 0x00000140
598 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
599 #define DSI_28nm_8960_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
605 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_1 0x00000144
606 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
607 #define DSI_28nm_8960_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
613 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_2 0x00000148
614 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
615 #define DSI_28nm_8960_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
621 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_3 0x0000014c
623 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_4 0x00000150
624 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
625 #define DSI_28nm_8960_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
631 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_5 0x00000154
632 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
633 #define DSI_28nm_8960_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
639 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_6 0x00000158
640 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
641 #define DSI_28nm_8960_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
647 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_7 0x0000015c
648 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
649 #define DSI_28nm_8960_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
655 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_8 0x00000160
656 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
657 #define DSI_28nm_8960_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
663 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_9 0x00000164
664 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
665 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
670 #define DSI_28nm_8960_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
677 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_10 0x00000168
678 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
679 #define DSI_28nm_8960_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
685 #define REG_DSI_28nm_8960_PHY_TIMING_CTRL_11 0x0000016c
686 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
687 #define DSI_28nm_8960_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
693 #define REG_DSI_28nm_8960_PHY_CTRL_0 0x00000170
695 #define REG_DSI_28nm_8960_PHY_CTRL_1 0x00000174
697 #define REG_DSI_28nm_8960_PHY_CTRL_2 0x00000178
699 #define REG_DSI_28nm_8960_PHY_CTRL_3 0x0000017c
701 #define REG_DSI_28nm_8960_PHY_STRENGTH_0 0x00000180
703 #define REG_DSI_28nm_8960_PHY_STRENGTH_1 0x00000184
705 #define REG_DSI_28nm_8960_PHY_STRENGTH_2 0x00000188
707 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_0 0x0000018c
709 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_1 0x00000190
711 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_2 0x00000194
713 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_3 0x00000198
715 #define REG_DSI_28nm_8960_PHY_BIST_CTRL_4 0x0000019c
717 #define REG_DSI_28nm_8960_PHY_LDO_CTRL 0x000001b0
719 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_0 0x00000000
721 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_1 0x00000004
723 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_2 0x00000008
725 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_3 0x0000000c
727 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_4 0x00000010
729 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CTRL_5 0x00000014
731 #define REG_DSI_28nm_8960_PHY_MISC_REGULATOR_CAL_PWR_CFG 0x00000018
733 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_TRIGGER 0x00000028
735 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_0 0x0000002c
737 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_1 0x00000030
739 #define REG_DSI_28nm_8960_PHY_MISC_CAL_SW_CFG_2 0x00000034
741 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_0 0x00000038
743 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_1 0x0000003c
745 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_2 0x00000040
747 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_3 0x00000044
749 #define REG_DSI_28nm_8960_PHY_MISC_CAL_HW_CFG_4 0x00000048
751 #define REG_DSI_28nm_8960_PHY_MISC_CAL_STATUS 0x00000050
752 #define DSI_28nm_8960_PHY_MISC_CAL_STATUS_CAL_BUSY 0x00000010
754 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_0 0x00000000
755 #define DSI_28nm_8960_PHY_PLL_CTRL_0_ENABLE 0x00000001
757 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_1 0x00000004
759 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_2 0x00000008
761 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_3 0x0000000c
763 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_4 0x00000010
765 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_5 0x00000014
767 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_6 0x00000018
769 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_7 0x0000001c
771 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_8 0x00000020
773 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_9 0x00000024
775 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_10 0x00000028
777 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_11 0x0000002c
779 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_12 0x00000030
781 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_13 0x00000034
783 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_14 0x00000038
785 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_15 0x0000003c
787 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_16 0x00000040
789 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_17 0x00000044
791 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_18 0x00000048
793 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_19 0x0000004c
795 #define REG_DSI_28nm_8960_PHY_PLL_CTRL_20 0x00000050
797 #define REG_DSI_28nm_8960_PHY_PLL_RDY 0x00000080
798 #define DSI_28nm_8960_PHY_PLL_RDY_PLL_RDY 0x00000001
800 static inline uint32_t REG_DSI_28nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN()
802 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_0()
804 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_1()
806 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_2()
808 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_3()
810 static inline uint32_t REG_DSI_28nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_CFG_4()
812 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_28nm_PHY_LN_TEST_DATAPATH()
814 static inline uint32_t REG_DSI_28nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_DEBUG_SEL()
816 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_0()
818 static inline uint32_t REG_DSI_28nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_28nm_PHY_LN_TEST_STR_1()
820 #define REG_DSI_28nm_PHY_LNCK_CFG_0 0x00000100
822 #define REG_DSI_28nm_PHY_LNCK_CFG_1 0x00000104
824 #define REG_DSI_28nm_PHY_LNCK_CFG_2 0x00000108
826 #define REG_DSI_28nm_PHY_LNCK_CFG_3 0x0000010c
828 #define REG_DSI_28nm_PHY_LNCK_CFG_4 0x00000110
830 #define REG_DSI_28nm_PHY_LNCK_TEST_DATAPATH 0x00000114
832 #define REG_DSI_28nm_PHY_LNCK_DEBUG_SEL 0x00000118
834 #define REG_DSI_28nm_PHY_LNCK_TEST_STR0 0x0000011c
836 #define REG_DSI_28nm_PHY_LNCK_TEST_STR1 0x00000120
838 #define REG_DSI_28nm_PHY_TIMING_CTRL_0 0x00000140
839 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
840 #define DSI_28nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
846 #define REG_DSI_28nm_PHY_TIMING_CTRL_1 0x00000144
847 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
848 #define DSI_28nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
854 #define REG_DSI_28nm_PHY_TIMING_CTRL_2 0x00000148
855 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
856 #define DSI_28nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
862 #define REG_DSI_28nm_PHY_TIMING_CTRL_3 0x0000014c
863 #define DSI_28nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
865 #define REG_DSI_28nm_PHY_TIMING_CTRL_4 0x00000150
866 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
867 #define DSI_28nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
873 #define REG_DSI_28nm_PHY_TIMING_CTRL_5 0x00000154
874 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
875 #define DSI_28nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
881 #define REG_DSI_28nm_PHY_TIMING_CTRL_6 0x00000158
882 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
883 #define DSI_28nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
889 #define REG_DSI_28nm_PHY_TIMING_CTRL_7 0x0000015c
890 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
891 #define DSI_28nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
897 #define REG_DSI_28nm_PHY_TIMING_CTRL_8 0x00000160
898 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
899 #define DSI_28nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
905 #define REG_DSI_28nm_PHY_TIMING_CTRL_9 0x00000164
906 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
907 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
912 #define DSI_28nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
919 #define REG_DSI_28nm_PHY_TIMING_CTRL_10 0x00000168
920 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
921 #define DSI_28nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
927 #define REG_DSI_28nm_PHY_TIMING_CTRL_11 0x0000016c
928 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
929 #define DSI_28nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
935 #define REG_DSI_28nm_PHY_CTRL_0 0x00000170
937 #define REG_DSI_28nm_PHY_CTRL_1 0x00000174
939 #define REG_DSI_28nm_PHY_CTRL_2 0x00000178
941 #define REG_DSI_28nm_PHY_CTRL_3 0x0000017c
943 #define REG_DSI_28nm_PHY_CTRL_4 0x00000180
945 #define REG_DSI_28nm_PHY_STRENGTH_0 0x00000184
947 #define REG_DSI_28nm_PHY_STRENGTH_1 0x00000188
949 #define REG_DSI_28nm_PHY_BIST_CTRL_0 0x000001b4
951 #define REG_DSI_28nm_PHY_BIST_CTRL_1 0x000001b8
953 #define REG_DSI_28nm_PHY_BIST_CTRL_2 0x000001bc
955 #define REG_DSI_28nm_PHY_BIST_CTRL_3 0x000001c0
957 #define REG_DSI_28nm_PHY_BIST_CTRL_4 0x000001c4
959 #define REG_DSI_28nm_PHY_BIST_CTRL_5 0x000001c8
961 #define REG_DSI_28nm_PHY_GLBL_TEST_CTRL 0x000001d4
962 #define DSI_28nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
964 #define REG_DSI_28nm_PHY_LDO_CNTRL 0x000001dc
966 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_0 0x00000000
968 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_1 0x00000004
970 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_2 0x00000008
972 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_3 0x0000000c
974 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_4 0x00000010
976 #define REG_DSI_28nm_PHY_REGULATOR_CTRL_5 0x00000014
978 #define REG_DSI_28nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
980 #define REG_DSI_28nm_PHY_PLL_REFCLK_CFG 0x00000000
981 #define DSI_28nm_PHY_PLL_REFCLK_CFG_DBLR 0x00000001
983 #define REG_DSI_28nm_PHY_PLL_POSTDIV1_CFG 0x00000004
985 #define REG_DSI_28nm_PHY_PLL_CHGPUMP_CFG 0x00000008
987 #define REG_DSI_28nm_PHY_PLL_VCOLPF_CFG 0x0000000c
989 #define REG_DSI_28nm_PHY_PLL_VREG_CFG 0x00000010
990 #define DSI_28nm_PHY_PLL_VREG_CFG_POSTDIV1_BYPASS_B 0x00000002
992 #define REG_DSI_28nm_PHY_PLL_PWRGEN_CFG 0x00000014
994 #define REG_DSI_28nm_PHY_PLL_DMUX_CFG 0x00000018
996 #define REG_DSI_28nm_PHY_PLL_AMUX_CFG 0x0000001c
998 #define REG_DSI_28nm_PHY_PLL_GLB_CFG 0x00000020
999 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRDN_B 0x00000001
1000 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_LDO_PWRDN_B 0x00000002
1001 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_PWRGEN_PWRDN_B 0x00000004
1002 #define DSI_28nm_PHY_PLL_GLB_CFG_PLL_ENABLE 0x00000008
1004 #define REG_DSI_28nm_PHY_PLL_POSTDIV2_CFG 0x00000024
1006 #define REG_DSI_28nm_PHY_PLL_POSTDIV3_CFG 0x00000028
1008 #define REG_DSI_28nm_PHY_PLL_LPFR_CFG 0x0000002c
1010 #define REG_DSI_28nm_PHY_PLL_LPFC1_CFG 0x00000030
1012 #define REG_DSI_28nm_PHY_PLL_LPFC2_CFG 0x00000034
1014 #define REG_DSI_28nm_PHY_PLL_SDM_CFG0 0x00000038
1015 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__MASK 0x0000003f
1016 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP_DIV__SHIFT 0
1021 #define DSI_28nm_PHY_PLL_SDM_CFG0_BYP 0x00000040
1023 #define REG_DSI_28nm_PHY_PLL_SDM_CFG1 0x0000003c
1024 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__MASK 0x0000003f
1025 #define DSI_28nm_PHY_PLL_SDM_CFG1_DC_OFFSET__SHIFT 0
1030 #define DSI_28nm_PHY_PLL_SDM_CFG1_DITHER_EN__MASK 0x00000040
1037 #define REG_DSI_28nm_PHY_PLL_SDM_CFG2 0x00000040
1038 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__MASK 0x000000ff
1039 #define DSI_28nm_PHY_PLL_SDM_CFG2_FREQ_SEED_7_0__SHIFT 0
1045 #define REG_DSI_28nm_PHY_PLL_SDM_CFG3 0x00000044
1046 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__MASK 0x000000ff
1047 #define DSI_28nm_PHY_PLL_SDM_CFG3_FREQ_SEED_15_8__SHIFT 0
1053 #define REG_DSI_28nm_PHY_PLL_SDM_CFG4 0x00000048
1055 #define REG_DSI_28nm_PHY_PLL_SSC_CFG0 0x0000004c
1057 #define REG_DSI_28nm_PHY_PLL_SSC_CFG1 0x00000050
1059 #define REG_DSI_28nm_PHY_PLL_SSC_CFG2 0x00000054
1061 #define REG_DSI_28nm_PHY_PLL_SSC_CFG3 0x00000058
1063 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG0 0x0000005c
1065 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG1 0x00000060
1067 #define REG_DSI_28nm_PHY_PLL_LKDET_CFG2 0x00000064
1069 #define REG_DSI_28nm_PHY_PLL_TEST_CFG 0x00000068
1070 #define DSI_28nm_PHY_PLL_TEST_CFG_PLL_SW_RESET 0x00000001
1072 #define REG_DSI_28nm_PHY_PLL_CAL_CFG0 0x0000006c
1074 #define REG_DSI_28nm_PHY_PLL_CAL_CFG1 0x00000070
1076 #define REG_DSI_28nm_PHY_PLL_CAL_CFG2 0x00000074
1078 #define REG_DSI_28nm_PHY_PLL_CAL_CFG3 0x00000078
1080 #define REG_DSI_28nm_PHY_PLL_CAL_CFG4 0x0000007c
1082 #define REG_DSI_28nm_PHY_PLL_CAL_CFG5 0x00000080
1084 #define REG_DSI_28nm_PHY_PLL_CAL_CFG6 0x00000084
1086 #define REG_DSI_28nm_PHY_PLL_CAL_CFG7 0x00000088
1088 #define REG_DSI_28nm_PHY_PLL_CAL_CFG8 0x0000008c
1090 #define REG_DSI_28nm_PHY_PLL_CAL_CFG9 0x00000090
1092 #define REG_DSI_28nm_PHY_PLL_CAL_CFG10 0x00000094
1094 #define REG_DSI_28nm_PHY_PLL_CAL_CFG11 0x00000098
1096 #define REG_DSI_28nm_PHY_PLL_EFUSE_CFG 0x0000009c
1098 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS_SEL 0x000000a0
1100 #define REG_DSI_28nm_PHY_PLL_CTRL_42 0x000000a4
1102 #define REG_DSI_28nm_PHY_PLL_CTRL_43 0x000000a8
1104 #define REG_DSI_28nm_PHY_PLL_CTRL_44 0x000000ac
1106 #define REG_DSI_28nm_PHY_PLL_CTRL_45 0x000000b0
1108 #define REG_DSI_28nm_PHY_PLL_CTRL_46 0x000000b4
1110 #define REG_DSI_28nm_PHY_PLL_CTRL_47 0x000000b8
1112 #define REG_DSI_28nm_PHY_PLL_CTRL_48 0x000000bc
1114 #define REG_DSI_28nm_PHY_PLL_STATUS 0x000000c0
1115 #define DSI_28nm_PHY_PLL_STATUS_PLL_RDY 0x00000001
1117 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS0 0x000000c4
1119 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS1 0x000000c8
1121 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS2 0x000000cc
1123 #define REG_DSI_28nm_PHY_PLL_DEBUG_BUS3 0x000000d0
1125 #define REG_DSI_28nm_PHY_PLL_CTRL_54 0x000000d4
1127 static inline uint32_t REG_DSI_20nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN()
1129 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_0(uint32_t i0) { return 0x00000000 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_0()
1131 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_1(uint32_t i0) { return 0x00000004 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_1()
1133 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_2(uint32_t i0) { return 0x00000008 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_2()
1135 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_3(uint32_t i0) { return 0x0000000c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_3()
1137 static inline uint32_t REG_DSI_20nm_PHY_LN_CFG_4(uint32_t i0) { return 0x00000010 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_CFG_4()
1139 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000014 + 0x40*i0… in REG_DSI_20nm_PHY_LN_TEST_DATAPATH()
1141 static inline uint32_t REG_DSI_20nm_PHY_LN_DEBUG_SEL(uint32_t i0) { return 0x00000018 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_DEBUG_SEL()
1143 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_0(uint32_t i0) { return 0x0000001c + 0x40*i0; } in REG_DSI_20nm_PHY_LN_TEST_STR_0()
1145 static inline uint32_t REG_DSI_20nm_PHY_LN_TEST_STR_1(uint32_t i0) { return 0x00000020 + 0x40*i0; } in REG_DSI_20nm_PHY_LN_TEST_STR_1()
1147 #define REG_DSI_20nm_PHY_LNCK_CFG_0 0x00000100
1149 #define REG_DSI_20nm_PHY_LNCK_CFG_1 0x00000104
1151 #define REG_DSI_20nm_PHY_LNCK_CFG_2 0x00000108
1153 #define REG_DSI_20nm_PHY_LNCK_CFG_3 0x0000010c
1155 #define REG_DSI_20nm_PHY_LNCK_CFG_4 0x00000110
1157 #define REG_DSI_20nm_PHY_LNCK_TEST_DATAPATH 0x00000114
1159 #define REG_DSI_20nm_PHY_LNCK_DEBUG_SEL 0x00000118
1161 #define REG_DSI_20nm_PHY_LNCK_TEST_STR0 0x0000011c
1163 #define REG_DSI_20nm_PHY_LNCK_TEST_STR1 0x00000120
1165 #define REG_DSI_20nm_PHY_TIMING_CTRL_0 0x00000140
1166 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__MASK 0x000000ff
1167 #define DSI_20nm_PHY_TIMING_CTRL_0_CLK_ZERO__SHIFT 0
1173 #define REG_DSI_20nm_PHY_TIMING_CTRL_1 0x00000144
1174 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__MASK 0x000000ff
1175 #define DSI_20nm_PHY_TIMING_CTRL_1_CLK_TRAIL__SHIFT 0
1181 #define REG_DSI_20nm_PHY_TIMING_CTRL_2 0x00000148
1182 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__MASK 0x000000ff
1183 #define DSI_20nm_PHY_TIMING_CTRL_2_CLK_PREPARE__SHIFT 0
1189 #define REG_DSI_20nm_PHY_TIMING_CTRL_3 0x0000014c
1190 #define DSI_20nm_PHY_TIMING_CTRL_3_CLK_ZERO_8 0x00000001
1192 #define REG_DSI_20nm_PHY_TIMING_CTRL_4 0x00000150
1193 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1194 #define DSI_20nm_PHY_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1200 #define REG_DSI_20nm_PHY_TIMING_CTRL_5 0x00000154
1201 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1202 #define DSI_20nm_PHY_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1208 #define REG_DSI_20nm_PHY_TIMING_CTRL_6 0x00000158
1209 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1210 #define DSI_20nm_PHY_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1216 #define REG_DSI_20nm_PHY_TIMING_CTRL_7 0x0000015c
1217 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1218 #define DSI_20nm_PHY_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1224 #define REG_DSI_20nm_PHY_TIMING_CTRL_8 0x00000160
1225 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1226 #define DSI_20nm_PHY_TIMING_CTRL_8_HS_RQST__SHIFT 0
1232 #define REG_DSI_20nm_PHY_TIMING_CTRL_9 0x00000164
1233 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1234 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_GO__SHIFT 0
1239 #define DSI_20nm_PHY_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1246 #define REG_DSI_20nm_PHY_TIMING_CTRL_10 0x00000168
1247 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1248 #define DSI_20nm_PHY_TIMING_CTRL_10_TA_GET__SHIFT 0
1254 #define REG_DSI_20nm_PHY_TIMING_CTRL_11 0x0000016c
1255 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1256 #define DSI_20nm_PHY_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1262 #define REG_DSI_20nm_PHY_CTRL_0 0x00000170
1264 #define REG_DSI_20nm_PHY_CTRL_1 0x00000174
1266 #define REG_DSI_20nm_PHY_CTRL_2 0x00000178
1268 #define REG_DSI_20nm_PHY_CTRL_3 0x0000017c
1270 #define REG_DSI_20nm_PHY_CTRL_4 0x00000180
1272 #define REG_DSI_20nm_PHY_STRENGTH_0 0x00000184
1274 #define REG_DSI_20nm_PHY_STRENGTH_1 0x00000188
1276 #define REG_DSI_20nm_PHY_BIST_CTRL_0 0x000001b4
1278 #define REG_DSI_20nm_PHY_BIST_CTRL_1 0x000001b8
1280 #define REG_DSI_20nm_PHY_BIST_CTRL_2 0x000001bc
1282 #define REG_DSI_20nm_PHY_BIST_CTRL_3 0x000001c0
1284 #define REG_DSI_20nm_PHY_BIST_CTRL_4 0x000001c4
1286 #define REG_DSI_20nm_PHY_BIST_CTRL_5 0x000001c8
1288 #define REG_DSI_20nm_PHY_GLBL_TEST_CTRL 0x000001d4
1289 #define DSI_20nm_PHY_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000001
1291 #define REG_DSI_20nm_PHY_LDO_CNTRL 0x000001dc
1293 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_0 0x00000000
1295 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_1 0x00000004
1297 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_2 0x00000008
1299 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_3 0x0000000c
1301 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_4 0x00000010
1303 #define REG_DSI_20nm_PHY_REGULATOR_CTRL_5 0x00000014
1305 #define REG_DSI_20nm_PHY_REGULATOR_CAL_PWR_CFG 0x00000018
1307 #define REG_DSI_14nm_PHY_CMN_REVISION_ID0 0x00000000
1309 #define REG_DSI_14nm_PHY_CMN_REVISION_ID1 0x00000004
1311 #define REG_DSI_14nm_PHY_CMN_REVISION_ID2 0x00000008
1313 #define REG_DSI_14nm_PHY_CMN_REVISION_ID3 0x0000000c
1315 #define REG_DSI_14nm_PHY_CMN_CLK_CFG0 0x00000010
1316 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_3_0__MASK 0x000000f0
1322 #define DSI_14nm_PHY_CMN_CLK_CFG0_DIV_CTRL_7_4__MASK 0x000000f0
1329 #define REG_DSI_14nm_PHY_CMN_CLK_CFG1 0x00000014
1330 #define DSI_14nm_PHY_CMN_CLK_CFG1_DSICLK_SEL 0x00000001
1332 #define REG_DSI_14nm_PHY_CMN_GLBL_TEST_CTRL 0x00000018
1333 #define DSI_14nm_PHY_CMN_GLBL_TEST_CTRL_BITCLK_HS_SEL 0x00000004
1335 #define REG_DSI_14nm_PHY_CMN_CTRL_0 0x0000001c
1337 #define REG_DSI_14nm_PHY_CMN_CTRL_1 0x00000020
1339 #define REG_DSI_14nm_PHY_CMN_HW_TRIGGER 0x00000024
1341 #define REG_DSI_14nm_PHY_CMN_SW_CFG0 0x00000028
1343 #define REG_DSI_14nm_PHY_CMN_SW_CFG1 0x0000002c
1345 #define REG_DSI_14nm_PHY_CMN_SW_CFG2 0x00000030
1347 #define REG_DSI_14nm_PHY_CMN_HW_CFG0 0x00000034
1349 #define REG_DSI_14nm_PHY_CMN_HW_CFG1 0x00000038
1351 #define REG_DSI_14nm_PHY_CMN_HW_CFG2 0x0000003c
1353 #define REG_DSI_14nm_PHY_CMN_HW_CFG3 0x00000040
1355 #define REG_DSI_14nm_PHY_CMN_HW_CFG4 0x00000044
1357 #define REG_DSI_14nm_PHY_CMN_PLL_CNTRL 0x00000048
1358 #define DSI_14nm_PHY_CMN_PLL_CNTRL_PLL_START 0x00000001
1360 #define REG_DSI_14nm_PHY_CMN_LDO_CNTRL 0x0000004c
1361 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__MASK 0x0000003f
1362 #define DSI_14nm_PHY_CMN_LDO_CNTRL_VREG_CTRL__SHIFT 0
1368 static inline uint32_t REG_DSI_14nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN()
1370 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG0()
1371 #define DSI_14nm_PHY_LN_CFG0_PREPARE_DLY__MASK 0x000000c0
1378 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG1()
1379 #define DSI_14nm_PHY_LN_CFG1_HALFBYTECLK_EN 0x00000001
1381 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG2()
1383 static inline uint32_t REG_DSI_14nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_14nm_PHY_LN_CFG3()
1385 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TEST_DATAPATH()
1387 static inline uint32_t REG_DSI_14nm_PHY_LN_TEST_STR(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_TEST_STR()
1389 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_4(uint32_t i0) { return 0x00000018 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_4()
1390 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__MASK 0x000000ff
1391 #define DSI_14nm_PHY_LN_TIMING_CTRL_4_HS_EXIT__SHIFT 0
1397 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_5(uint32_t i0) { return 0x0000001c + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_5()
1398 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__MASK 0x000000ff
1399 #define DSI_14nm_PHY_LN_TIMING_CTRL_5_HS_ZERO__SHIFT 0
1405 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_6(uint32_t i0) { return 0x00000020 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_6()
1406 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__MASK 0x000000ff
1407 #define DSI_14nm_PHY_LN_TIMING_CTRL_6_HS_PREPARE__SHIFT 0
1413 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_7(uint32_t i0) { return 0x00000024 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_7()
1414 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__MASK 0x000000ff
1415 #define DSI_14nm_PHY_LN_TIMING_CTRL_7_HS_TRAIL__SHIFT 0
1421 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_8(uint32_t i0) { return 0x00000028 + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_8()
1422 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__MASK 0x000000ff
1423 #define DSI_14nm_PHY_LN_TIMING_CTRL_8_HS_RQST__SHIFT 0
1429 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_9(uint32_t i0) { return 0x0000002c + 0x80*i0… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_9()
1430 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__MASK 0x00000007
1431 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_GO__SHIFT 0
1436 #define DSI_14nm_PHY_LN_TIMING_CTRL_9_TA_SURE__MASK 0x00000070
1443 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_10(uint32_t i0) { return 0x00000030 + 0x80*i… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_10()
1444 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__MASK 0x00000007
1445 #define DSI_14nm_PHY_LN_TIMING_CTRL_10_TA_GET__SHIFT 0
1451 static inline uint32_t REG_DSI_14nm_PHY_LN_TIMING_CTRL_11(uint32_t i0) { return 0x00000034 + 0x80*i… in REG_DSI_14nm_PHY_LN_TIMING_CTRL_11()
1452 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__MASK 0x000000ff
1453 #define DSI_14nm_PHY_LN_TIMING_CTRL_11_TRIG3_CMD__SHIFT 0
1459 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0(uint32_t i0) { return 0x00000038 + 0x80*… in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_0()
1461 static inline uint32_t REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1(uint32_t i0) { return 0x0000003c + 0x80*… in REG_DSI_14nm_PHY_LN_STRENGTH_CTRL_1()
1463 static inline uint32_t REG_DSI_14nm_PHY_LN_VREG_CNTRL(uint32_t i0) { return 0x00000064 + 0x80*i0; } in REG_DSI_14nm_PHY_LN_VREG_CNTRL()
1465 #define REG_DSI_14nm_PHY_PLL_IE_TRIM 0x00000000
1467 #define REG_DSI_14nm_PHY_PLL_IP_TRIM 0x00000004
1469 #define REG_DSI_14nm_PHY_PLL_IPTAT_TRIM 0x00000010
1471 #define REG_DSI_14nm_PHY_PLL_CLKBUFLR_EN 0x0000001c
1473 #define REG_DSI_14nm_PHY_PLL_SYSCLK_EN_RESET 0x00000028
1475 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL 0x0000002c
1477 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL2 0x00000030
1479 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL3 0x00000034
1481 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL4 0x00000038
1483 #define REG_DSI_14nm_PHY_PLL_RESETSM_CNTRL5 0x0000003c
1485 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF1 0x00000040
1487 #define REG_DSI_14nm_PHY_PLL_KVCO_DIV_REF2 0x00000044
1489 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT1 0x00000048
1491 #define REG_DSI_14nm_PHY_PLL_KVCO_COUNT2 0x0000004c
1493 #define REG_DSI_14nm_PHY_PLL_VREF_CFG1 0x0000005c
1495 #define REG_DSI_14nm_PHY_PLL_KVCO_CODE 0x00000058
1497 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF1 0x0000006c
1499 #define REG_DSI_14nm_PHY_PLL_VCO_DIV_REF2 0x00000070
1501 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT1 0x00000074
1503 #define REG_DSI_14nm_PHY_PLL_VCO_COUNT2 0x00000078
1505 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP1 0x0000007c
1507 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP2 0x00000080
1509 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP3 0x00000084
1511 #define REG_DSI_14nm_PHY_PLL_PLLLOCK_CMP_EN 0x00000088
1513 #define REG_DSI_14nm_PHY_PLL_PLL_VCO_TUNE 0x0000008c
1515 #define REG_DSI_14nm_PHY_PLL_DEC_START 0x00000090
1517 #define REG_DSI_14nm_PHY_PLL_SSC_EN_CENTER 0x00000094
1519 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER1 0x00000098
1521 #define REG_DSI_14nm_PHY_PLL_SSC_ADJ_PER2 0x0000009c
1523 #define REG_DSI_14nm_PHY_PLL_SSC_PER1 0x000000a0
1525 #define REG_DSI_14nm_PHY_PLL_SSC_PER2 0x000000a4
1527 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE1 0x000000a8
1529 #define REG_DSI_14nm_PHY_PLL_SSC_STEP_SIZE2 0x000000ac
1531 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START1 0x000000b4
1533 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START2 0x000000b8
1535 #define REG_DSI_14nm_PHY_PLL_DIV_FRAC_START3 0x000000bc
1537 #define REG_DSI_14nm_PHY_PLL_TXCLK_EN 0x000000c0
1539 #define REG_DSI_14nm_PHY_PLL_PLL_CRCTRL 0x000000c4
1541 #define REG_DSI_14nm_PHY_PLL_RESET_SM_READY_STATUS 0x000000cc
1543 #define REG_DSI_14nm_PHY_PLL_PLL_MISC1 0x000000e8
1545 #define REG_DSI_14nm_PHY_PLL_CP_SET_CUR 0x000000f0
1547 #define REG_DSI_14nm_PHY_PLL_PLL_ICPMSET 0x000000f4
1549 #define REG_DSI_14nm_PHY_PLL_PLL_ICPCSET 0x000000f8
1551 #define REG_DSI_14nm_PHY_PLL_PLL_ICP_SET 0x000000fc
1553 #define REG_DSI_14nm_PHY_PLL_PLL_LPF1 0x00000100
1555 #define REG_DSI_14nm_PHY_PLL_PLL_LPF2_POSTDIV 0x00000104
1557 #define REG_DSI_14nm_PHY_PLL_PLL_BANDGAP 0x00000108
1559 #define REG_DSI_10nm_PHY_CMN_REVISION_ID0 0x00000000
1561 #define REG_DSI_10nm_PHY_CMN_REVISION_ID1 0x00000004
1563 #define REG_DSI_10nm_PHY_CMN_REVISION_ID2 0x00000008
1565 #define REG_DSI_10nm_PHY_CMN_REVISION_ID3 0x0000000c
1567 #define REG_DSI_10nm_PHY_CMN_CLK_CFG0 0x00000010
1569 #define REG_DSI_10nm_PHY_CMN_CLK_CFG1 0x00000014
1571 #define REG_DSI_10nm_PHY_CMN_GLBL_CTRL 0x00000018
1573 #define REG_DSI_10nm_PHY_CMN_RBUF_CTRL 0x0000001c
1575 #define REG_DSI_10nm_PHY_CMN_VREG_CTRL 0x00000020
1577 #define REG_DSI_10nm_PHY_CMN_CTRL_0 0x00000024
1579 #define REG_DSI_10nm_PHY_CMN_CTRL_1 0x00000028
1581 #define REG_DSI_10nm_PHY_CMN_CTRL_2 0x0000002c
1583 #define REG_DSI_10nm_PHY_CMN_LANE_CFG0 0x00000030
1585 #define REG_DSI_10nm_PHY_CMN_LANE_CFG1 0x00000034
1587 #define REG_DSI_10nm_PHY_CMN_PLL_CNTRL 0x00000038
1589 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL0 0x00000098
1591 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL1 0x0000009c
1593 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL2 0x000000a0
1595 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL3 0x000000a4
1597 #define REG_DSI_10nm_PHY_CMN_LANE_CTRL4 0x000000a8
1599 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_0 0x000000ac
1601 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_1 0x000000b0
1603 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_2 0x000000b4
1605 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_3 0x000000b8
1607 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_4 0x000000bc
1609 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_5 0x000000c0
1611 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_6 0x000000c4
1613 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_7 0x000000c8
1615 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_8 0x000000cc
1617 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_9 0x000000d0
1619 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_10 0x000000d4
1621 #define REG_DSI_10nm_PHY_CMN_TIMING_CTRL_11 0x000000d8
1623 #define REG_DSI_10nm_PHY_CMN_PHY_STATUS 0x000000ec
1625 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS0 0x000000f4
1627 #define REG_DSI_10nm_PHY_CMN_LANE_STATUS1 0x000000f8
1629 static inline uint32_t REG_DSI_10nm_PHY_LN(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN()
1631 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG0(uint32_t i0) { return 0x00000000 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG0()
1633 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG1(uint32_t i0) { return 0x00000004 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG1()
1635 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG2(uint32_t i0) { return 0x00000008 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG2()
1637 static inline uint32_t REG_DSI_10nm_PHY_LN_CFG3(uint32_t i0) { return 0x0000000c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_CFG3()
1639 static inline uint32_t REG_DSI_10nm_PHY_LN_TEST_DATAPATH(uint32_t i0) { return 0x00000010 + 0x80*i0… in REG_DSI_10nm_PHY_LN_TEST_DATAPATH()
1641 static inline uint32_t REG_DSI_10nm_PHY_LN_PIN_SWAP(uint32_t i0) { return 0x00000014 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_PIN_SWAP()
1643 static inline uint32_t REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL(uint32_t i0) { return 0x00000018 + 0x80*i0… in REG_DSI_10nm_PHY_LN_HSTX_STR_CTRL()
1645 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL(uint32_t i0) { return 0x0000001c + 0x80*… in REG_DSI_10nm_PHY_LN_OFFSET_TOP_CTRL()
1647 static inline uint32_t REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL(uint32_t i0) { return 0x00000020 + 0x80*… in REG_DSI_10nm_PHY_LN_OFFSET_BOT_CTRL()
1649 static inline uint32_t REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL(uint32_t i0) { return 0x00000024 + 0x80*i0… in REG_DSI_10nm_PHY_LN_LPTX_STR_CTRL()
1651 static inline uint32_t REG_DSI_10nm_PHY_LN_LPRX_CTRL(uint32_t i0) { return 0x00000028 + 0x80*i0; } in REG_DSI_10nm_PHY_LN_LPRX_CTRL()
1653 static inline uint32_t REG_DSI_10nm_PHY_LN_TX_DCTRL(uint32_t i0) { return 0x0000002c + 0x80*i0; } in REG_DSI_10nm_PHY_LN_TX_DCTRL()
1655 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_ONE 0x00000000
1657 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_TWO 0x00000004
1659 #define REG_DSI_10nm_PHY_PLL_ANALOG_CONTROLS_THREE 0x00000010
1661 #define REG_DSI_10nm_PHY_PLL_DSM_DIVIDER 0x0000001c
1663 #define REG_DSI_10nm_PHY_PLL_FEEDBACK_DIVIDER 0x00000020
1665 #define REG_DSI_10nm_PHY_PLL_SYSTEM_MUXES 0x00000024
1667 #define REG_DSI_10nm_PHY_PLL_CMODE 0x0000002c
1669 #define REG_DSI_10nm_PHY_PLL_CALIBRATION_SETTINGS 0x00000030
1671 #define REG_DSI_10nm_PHY_PLL_BAND_SEL_CAL_SETTINGS_THREE 0x00000054
1673 #define REG_DSI_10nm_PHY_PLL_FREQ_DETECT_SETTINGS_ONE 0x00000064
1675 #define REG_DSI_10nm_PHY_PLL_PFILT 0x0000007c
1677 #define REG_DSI_10nm_PHY_PLL_IFILT 0x00000080
1679 #define REG_DSI_10nm_PHY_PLL_OUTDIV 0x00000094
1681 #define REG_DSI_10nm_PHY_PLL_CORE_OVERRIDE 0x000000a4
1683 #define REG_DSI_10nm_PHY_PLL_CORE_INPUT_OVERRIDE 0x000000a8
1685 #define REG_DSI_10nm_PHY_PLL_PLL_DIGITAL_TIMERS_TWO 0x000000b4
1687 #define REG_DSI_10nm_PHY_PLL_DECIMAL_DIV_START_1 0x000000cc
1689 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_LOW_1 0x000000d0
1691 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_MID_1 0x000000d4
1693 #define REG_DSI_10nm_PHY_PLL_FRAC_DIV_START_HIGH_1 0x000000d8
1695 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_LOW_1 0x0000010c
1697 #define REG_DSI_10nm_PHY_PLL_SSC_STEPSIZE_HIGH_1 0x00000110
1699 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_LOW_1 0x00000114
1701 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_PER_HIGH_1 0x00000118
1703 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_LOW_1 0x0000011c
1705 #define REG_DSI_10nm_PHY_PLL_SSC_DIV_ADJPER_HIGH_1 0x00000120
1707 #define REG_DSI_10nm_PHY_PLL_SSC_CONTROL 0x0000013c
1709 #define REG_DSI_10nm_PHY_PLL_PLL_OUTDIV_RATE 0x00000140
1711 #define REG_DSI_10nm_PHY_PLL_PLL_LOCKDET_RATE_1 0x00000144
1713 #define REG_DSI_10nm_PHY_PLL_PLL_PROP_GAIN_RATE_1 0x0000014c
1715 #define REG_DSI_10nm_PHY_PLL_PLL_BAND_SET_RATE_1 0x00000154
1717 #define REG_DSI_10nm_PHY_PLL_PLL_INT_GAIN_IFILT_BAND_1 0x0000015c
1719 #define REG_DSI_10nm_PHY_PLL_PLL_FL_INT_GAIN_PFILT_BAND_1 0x00000164
1721 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_OVERRIDE 0x00000180
1723 #define REG_DSI_10nm_PHY_PLL_PLL_LOCK_DELAY 0x00000184
1725 #define REG_DSI_10nm_PHY_PLL_CLOCK_INVERTERS 0x0000018c
1727 #define REG_DSI_10nm_PHY_PLL_COMMON_STATUS_ONE 0x000001a0