55 	int (*get_param)(struct msm_gpu *gpu, uint32_t param, uint64_t *value);
56 	int (*hw_init)(struct msm_gpu *gpu);
57 	int (*pm_suspend)(struct msm_gpu *gpu);
58 	int (*pm_resume)(struct msm_gpu *gpu);
59 	void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
61 	void (*flush)(struct msm_gpu *gpu, struct msm_ringbuffer *ring);
63 	struct msm_ringbuffer *(*active_ring)(struct msm_gpu *gpu);
64 	void (*recover)(struct msm_gpu *gpu);
65 	void (*destroy)(struct msm_gpu *gpu);
67 	/* show GPU status in debugfs: */
68 	void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state,
71 	int (*debugfs_init)(struct msm_gpu *gpu, struct drm_minor *minor);
73 	int (*gpu_busy)(struct msm_gpu *gpu, uint64_t *value);
74 	struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu);
102 	/* does gpu need hw_init? */
148 static inline bool msm_gpu_active(struct msm_gpu *gpu)  in msm_gpu_active()  argument
152 	for (i = 0; i < gpu->nr_rings; i++) {  in msm_gpu_active()
153 		struct msm_ringbuffer *ring = gpu->rb[i];  in msm_gpu_active()
216 static inline void gpu_write(struct msm_gpu *gpu, u32 reg, u32 data)  in gpu_write()  argument
218 	msm_writel(data, gpu->mmio + (reg << 2));  in gpu_write()
221 static inline u32 gpu_read(struct msm_gpu *gpu, u32 reg)  in gpu_read()  argument
223 	return msm_readl(gpu->mmio + (reg << 2));  in gpu_read()
226 static inline void gpu_rmw(struct msm_gpu *gpu, u32 reg, u32 mask, u32 or)  in gpu_rmw()  argument
228 	uint32_t val = gpu_read(gpu, reg);  in gpu_rmw()
231 	gpu_write(gpu, reg, val | or);  in gpu_rmw()
234 static inline u64 gpu_read64(struct msm_gpu *gpu, u32 lo, u32 hi)  in gpu_read64()  argument
240 	 * not quad word aligned and 2) the GPU hardware designers have a bit  in gpu_read64()
242 	 * spins. The longer a GPU family goes the higher the chance that  in gpu_read64()
252 	val = (u64) msm_readl(gpu->mmio + (lo << 2));  in gpu_read64()
253 	val |= ((u64) msm_readl(gpu->mmio + (hi << 2)) << 32);  in gpu_read64()
258 static inline void gpu_write64(struct msm_gpu *gpu, u32 lo, u32 hi, u64 val)  in gpu_write64()  argument
261 	msm_writel(lower_32_bits(val), gpu->mmio + (lo << 2));  in gpu_write64()
262 	msm_writel(upper_32_bits(val), gpu->mmio + (hi << 2));  in gpu_write64()
265 int msm_gpu_pm_suspend(struct msm_gpu *gpu);
266 int msm_gpu_pm_resume(struct msm_gpu *gpu);
268 int msm_gpu_hw_init(struct msm_gpu *gpu);
270 void msm_gpu_perfcntr_start(struct msm_gpu *gpu);
271 void msm_gpu_perfcntr_stop(struct msm_gpu *gpu);
272 int msm_gpu_perfcntr_sample(struct msm_gpu *gpu, uint32_t *activetime,
275 void msm_gpu_retire(struct msm_gpu *gpu);
276 void msm_gpu_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit,
280 		struct msm_gpu *gpu, const struct msm_gpu_funcs *funcs,
283 void msm_gpu_cleanup(struct msm_gpu *gpu);
295 static inline struct msm_gpu_state *msm_gpu_crashstate_get(struct msm_gpu *gpu)  in msm_gpu_crashstate_get()  argument
299 	mutex_lock(&gpu->dev->struct_mutex);  in msm_gpu_crashstate_get()
301 	if (gpu->crashstate) {  in msm_gpu_crashstate_get()
302 		kref_get(&gpu->crashstate->ref);  in msm_gpu_crashstate_get()
303 		state = gpu->crashstate;  in msm_gpu_crashstate_get()
306 	mutex_unlock(&gpu->dev->struct_mutex);  in msm_gpu_crashstate_get()
311 static inline void msm_gpu_crashstate_put(struct msm_gpu *gpu)  in msm_gpu_crashstate_put()  argument
313 	mutex_lock(&gpu->dev->struct_mutex);  in msm_gpu_crashstate_put()
315 	if (gpu->crashstate) {  in msm_gpu_crashstate_put()
316 		if (gpu->funcs->gpu_state_put(gpu->crashstate))  in msm_gpu_crashstate_put()
317 			gpu->crashstate = NULL;  in msm_gpu_crashstate_put()
320 	mutex_unlock(&gpu->dev->struct_mutex);  in msm_gpu_crashstate_put()