Lines Matching full:crtc
48 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y,
52 crtc_wr_cio_state(struct drm_crtc *crtc, struct nv04_crtc_reg *crtcstate, int index) in crtc_wr_cio_state() argument
54 NVWriteVgaCrtc(crtc->dev, nouveau_crtc(crtc)->index, index, in crtc_wr_cio_state()
55 crtcstate->CRTC[index]); in crtc_wr_cio_state()
58 static void nv_crtc_set_digital_vibrance(struct drm_crtc *crtc, int level) in nv_crtc_set_digital_vibrance() argument
60 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_set_digital_vibrance()
61 struct drm_device *dev = crtc->dev; in nv_crtc_set_digital_vibrance()
64 regp->CRTC[NV_CIO_CRE_CSB] = nv_crtc->saturation = level; in nv_crtc_set_digital_vibrance()
65 if (nv_crtc->saturation && nv_gf4_disp_arch(crtc->dev)) { in nv_crtc_set_digital_vibrance()
66 regp->CRTC[NV_CIO_CRE_CSB] = 0x80; in nv_crtc_set_digital_vibrance()
67 regp->CRTC[NV_CIO_CRE_5B] = nv_crtc->saturation << 2; in nv_crtc_set_digital_vibrance()
68 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_5B); in nv_crtc_set_digital_vibrance()
70 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_CSB); in nv_crtc_set_digital_vibrance()
73 static void nv_crtc_set_image_sharpening(struct drm_crtc *crtc, int level) in nv_crtc_set_image_sharpening() argument
75 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_set_image_sharpening()
76 struct drm_device *dev = crtc->dev; in nv_crtc_set_image_sharpening()
83 NVWriteRAMDAC(crtc->dev, nv_crtc->index, NV_PRAMDAC_634, regp->ramdac_634); in nv_crtc_set_image_sharpening()
112 static void nv_crtc_calc_state_ext(struct drm_crtc *crtc, struct drm_display_mode * mode, int dot_c… in nv_crtc_calc_state_ext() argument
114 struct drm_device *dev = crtc->dev; in nv_crtc_calc_state_ext()
118 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_calc_state_ext()
170 nv_crtc_dpms(struct drm_crtc *crtc, int mode) in nv_crtc_dpms() argument
172 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_dpms()
173 struct drm_device *dev = crtc->dev; in nv_crtc_dpms()
178 NV_DEBUG(drm, "Setting dpms mode %d on CRTC %d\n", mode, in nv_crtc_dpms()
232 nv_crtc_mode_set_vga(struct drm_crtc *crtc, struct drm_display_mode *mode) in nv_crtc_mode_set_vga() argument
234 struct drm_device *dev = crtc->dev; in nv_crtc_mode_set_vga()
235 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set_vga()
237 struct drm_framebuffer *fb = crtc->primary->fb; in nv_crtc_mode_set_vga()
259 if (encoder->crtc == crtc && in nv_crtc_mode_set_vga()
338 * CRTC in nv_crtc_mode_set_vga()
340 regp->CRTC[NV_CIO_CR_HDT_INDEX] = horizTotal; in nv_crtc_mode_set_vga()
341 regp->CRTC[NV_CIO_CR_HDE_INDEX] = horizDisplay; in nv_crtc_mode_set_vga()
342 regp->CRTC[NV_CIO_CR_HBS_INDEX] = horizBlankStart; in nv_crtc_mode_set_vga()
343 regp->CRTC[NV_CIO_CR_HBE_INDEX] = (1 << 7) | in nv_crtc_mode_set_vga()
345 regp->CRTC[NV_CIO_CR_HRS_INDEX] = horizStart; in nv_crtc_mode_set_vga()
346 regp->CRTC[NV_CIO_CR_HRE_INDEX] = XLATE(horizBlankEnd, 5, NV_CIO_CR_HRE_HBE_5) | in nv_crtc_mode_set_vga()
348 regp->CRTC[NV_CIO_CR_VDT_INDEX] = vertTotal; in nv_crtc_mode_set_vga()
349 regp->CRTC[NV_CIO_CR_OVL_INDEX] = XLATE(vertStart, 9, NV_CIO_CR_OVL_VRS_9) | in nv_crtc_mode_set_vga()
357 regp->CRTC[NV_CIO_CR_RSAL_INDEX] = 0x00; in nv_crtc_mode_set_vga()
358 …regp->CRTC[NV_CIO_CR_CELL_HT_INDEX] = ((mode->flags & DRM_MODE_FLAG_DBLSCAN) ? MASK(NV_CIO_CR_CELL… in nv_crtc_mode_set_vga()
361 regp->CRTC[NV_CIO_CR_CURS_ST_INDEX] = 0x00; in nv_crtc_mode_set_vga()
362 regp->CRTC[NV_CIO_CR_CURS_END_INDEX] = 0x00; in nv_crtc_mode_set_vga()
363 regp->CRTC[NV_CIO_CR_SA_HI_INDEX] = 0x00; in nv_crtc_mode_set_vga()
364 regp->CRTC[NV_CIO_CR_SA_LO_INDEX] = 0x00; in nv_crtc_mode_set_vga()
365 regp->CRTC[NV_CIO_CR_TCOFF_HI_INDEX] = 0x00; in nv_crtc_mode_set_vga()
366 regp->CRTC[NV_CIO_CR_TCOFF_LO_INDEX] = 0x00; in nv_crtc_mode_set_vga()
367 regp->CRTC[NV_CIO_CR_VRS_INDEX] = vertStart; in nv_crtc_mode_set_vga()
368 regp->CRTC[NV_CIO_CR_VRE_INDEX] = 1 << 5 | XLATE(vertEnd, 0, NV_CIO_CR_VRE_3_0); in nv_crtc_mode_set_vga()
369 regp->CRTC[NV_CIO_CR_VDE_INDEX] = vertDisplay; in nv_crtc_mode_set_vga()
370 /* framebuffer can be larger than crtc scanout area. */ in nv_crtc_mode_set_vga()
371 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = fb->pitches[0] / 8; in nv_crtc_mode_set_vga()
372 regp->CRTC[NV_CIO_CR_ULINE_INDEX] = 0x00; in nv_crtc_mode_set_vga()
373 regp->CRTC[NV_CIO_CR_VBS_INDEX] = vertBlankStart; in nv_crtc_mode_set_vga()
374 regp->CRTC[NV_CIO_CR_VBE_INDEX] = vertBlankEnd; in nv_crtc_mode_set_vga()
375 regp->CRTC[NV_CIO_CR_MODE_INDEX] = 0x43; in nv_crtc_mode_set_vga()
376 regp->CRTC[NV_CIO_CR_LCOMP_INDEX] = 0xff; in nv_crtc_mode_set_vga()
379 * Some extended CRTC registers (they are not saved with the rest of the vga regs). in nv_crtc_mode_set_vga()
382 /* framebuffer can be larger than crtc scanout area. */ in nv_crtc_mode_set_vga()
383 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = in nv_crtc_mode_set_vga()
385 regp->CRTC[NV_CIO_CRE_42] = in nv_crtc_mode_set_vga()
387 regp->CRTC[NV_CIO_CRE_RPC1_INDEX] = mode->crtc_hdisplay < 1280 ? in nv_crtc_mode_set_vga()
389 regp->CRTC[NV_CIO_CRE_LSR_INDEX] = XLATE(horizBlankEnd, 6, NV_CIO_CRE_LSR_HBE_6) | in nv_crtc_mode_set_vga()
394 regp->CRTC[NV_CIO_CRE_HEB__INDEX] = XLATE(horizStart, 8, NV_CIO_CRE_HEB_HRS_8) | in nv_crtc_mode_set_vga()
398 regp->CRTC[NV_CIO_CRE_EBR_INDEX] = XLATE(vertBlankStart, 11, NV_CIO_CRE_EBR_VBS_11) | in nv_crtc_mode_set_vga()
405 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = horizTotal; in nv_crtc_mode_set_vga()
406 regp->CRTC[NV_CIO_CRE_HEB__INDEX] |= XLATE(horizTotal, 8, NV_CIO_CRE_HEB_ILC_8); in nv_crtc_mode_set_vga()
408 regp->CRTC[NV_CIO_CRE_ILACE__INDEX] = 0xff; /* interlace off */ in nv_crtc_mode_set_vga()
450 * The clocks, CRTCs and outputs attached to this CRTC must be off.
456 nv_crtc_mode_set_regs(struct drm_crtc *crtc, struct drm_display_mode * mode) in nv_crtc_mode_set_regs() argument
458 struct drm_device *dev = crtc->dev; in nv_crtc_mode_set_regs()
460 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set_regs()
463 const struct drm_framebuffer *fb = crtc->primary->fb; in nv_crtc_mode_set_regs()
472 if (encoder->crtc != crtc) in nv_crtc_mode_set_regs()
489 regp->CRTC[NV_CIO_CRE_ENH_INDEX] = savep->CRTC[NV_CIO_CRE_ENH_INDEX] & ~(1<<5); in nv_crtc_mode_set_regs()
492 /* Except for rare conditions I2C is enabled on the primary crtc */ in nv_crtc_mode_set_regs()
496 /* Set overlay to desired crtc. */ in nv_crtc_mode_set_regs()
514 regp->CRTC[NV_CIO_CRE_53] = 0; in nv_crtc_mode_set_regs()
515 regp->CRTC[NV_CIO_CRE_54] = 0; in nv_crtc_mode_set_regs()
519 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x11; in nv_crtc_mode_set_regs()
521 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x88; in nv_crtc_mode_set_regs()
523 regp->CRTC[NV_CIO_CRE_SCRATCH3__INDEX] = 0x22; in nv_crtc_mode_set_regs()
527 regp->CRTC[NV_CIO_CRE_SCRATCH4__INDEX] = savep->CRTC[NV_CIO_CRE_SCRATCH4__INDEX]; in nv_crtc_mode_set_regs()
529 nv_crtc_set_digital_vibrance(crtc, nv_crtc->saturation); in nv_crtc_mode_set_regs()
537 regp->CRTC[NV_CIO_CRE_4B] = savep->CRTC[NV_CIO_CRE_4B] | 0x80; in nv_crtc_mode_set_regs()
539 /* The blob seems to take the current value from crtc 0, add 4 to that in nv_crtc_mode_set_regs()
540 * and reuse the old value for crtc 1 */ in nv_crtc_mode_set_regs()
541 …regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] = nv04_display(dev)->saved_reg.crtc_reg[0].CRTC[NV_CIO_CRE_TV… in nv_crtc_mode_set_regs()
543 regp->CRTC[NV_CIO_CRE_TVOUT_LATENCY] += 4; in nv_crtc_mode_set_regs()
547 regp->CRTC[NV_CIO_CRE_59] = off_chip_digital; in nv_crtc_mode_set_regs()
550 regp->CRTC[0x9f] = off_chip_digital ? 0x11 : 0x1; in nv_crtc_mode_set_regs()
569 regp->CRTC[NV_CIO_CRE_85] = 0xFF; in nv_crtc_mode_set_regs()
570 regp->CRTC[NV_CIO_CRE_86] = 0x1; in nv_crtc_mode_set_regs()
573 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] = (fb->format->depth + 1) / 8; in nv_crtc_mode_set_regs()
576 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (1 << 7); in nv_crtc_mode_set_regs()
595 nv_crtc_set_image_sharpening(crtc, nv_crtc->sharpness); in nv_crtc_mode_set_regs()
605 nv_crtc_swap_fbs(struct drm_crtc *crtc, struct drm_framebuffer *old_fb) in nv_crtc_swap_fbs() argument
607 struct nv04_display *disp = nv04_display(crtc->dev); in nv_crtc_swap_fbs()
608 struct nouveau_framebuffer *nvfb = nouveau_framebuffer(crtc->primary->fb); in nv_crtc_swap_fbs()
609 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_swap_fbs()
625 * The clocks, CRTCs and outputs attached to this CRTC must be off.
631 nv_crtc_mode_set(struct drm_crtc *crtc, struct drm_display_mode *mode, in nv_crtc_mode_set() argument
635 struct drm_device *dev = crtc->dev; in nv_crtc_mode_set()
636 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_mode_set()
640 NV_DEBUG(drm, "CTRC mode on CRTC %d:\n", nv_crtc->index); in nv_crtc_mode_set()
643 ret = nv_crtc_swap_fbs(crtc, old_fb); in nv_crtc_mode_set()
650 nv_crtc_mode_set_vga(crtc, adjusted_mode); in nv_crtc_mode_set()
654 nv_crtc_mode_set_regs(crtc, adjusted_mode); in nv_crtc_mode_set()
655 nv_crtc_calc_state_ext(crtc, mode, adjusted_mode->clock); in nv_crtc_mode_set()
659 static void nv_crtc_save(struct drm_crtc *crtc) in nv_crtc_save() argument
661 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_save()
662 struct drm_device *dev = crtc->dev; in nv_crtc_save()
668 if (nv_two_heads(crtc->dev)) in nv_crtc_save()
669 NVSetOwner(crtc->dev, nv_crtc->index); in nv_crtc_save()
671 nouveau_hw_save_state(crtc->dev, nv_crtc->index, saved); in nv_crtc_save()
675 crtc_state->CRTC[NV_CIO_CRE_LCD__INDEX] = crtc_saved->CRTC[NV_CIO_CRE_LCD__INDEX]; in nv_crtc_save()
680 static void nv_crtc_restore(struct drm_crtc *crtc) in nv_crtc_restore() argument
682 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_restore()
683 struct drm_device *dev = crtc->dev; in nv_crtc_restore()
685 uint8_t saved_cr21 = nv04_display(dev)->saved_reg.crtc_reg[head].CRTC[NV_CIO_CRE_21]; in nv_crtc_restore()
687 if (nv_two_heads(crtc->dev)) in nv_crtc_restore()
688 NVSetOwner(crtc->dev, head); in nv_crtc_restore()
690 nouveau_hw_load_state(crtc->dev, head, &nv04_display(dev)->saved_reg); in nv_crtc_restore()
691 nv_lock_vga_crtc_shadow(crtc->dev, head, saved_cr21); in nv_crtc_restore()
696 static void nv_crtc_prepare(struct drm_crtc *crtc) in nv_crtc_prepare() argument
698 struct drm_device *dev = crtc->dev; in nv_crtc_prepare()
700 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_prepare()
701 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; in nv_crtc_prepare()
706 drm_crtc_vblank_off(crtc); in nv_crtc_prepare()
707 funcs->dpms(crtc, DRM_MODE_DPMS_OFF); in nv_crtc_prepare()
719 static void nv_crtc_commit(struct drm_crtc *crtc) in nv_crtc_commit() argument
721 struct drm_device *dev = crtc->dev; in nv_crtc_commit()
722 const struct drm_crtc_helper_funcs *funcs = crtc->helper_private; in nv_crtc_commit()
723 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_commit()
726 nv04_crtc_mode_set_base(crtc, crtc->x, crtc->y, NULL); in nv_crtc_commit()
737 funcs->dpms(crtc, DRM_MODE_DPMS_ON); in nv_crtc_commit()
738 drm_crtc_vblank_on(crtc); in nv_crtc_commit()
741 static void nv_crtc_destroy(struct drm_crtc *crtc) in nv_crtc_destroy() argument
743 struct nv04_display *disp = nv04_display(crtc->dev); in nv_crtc_destroy()
744 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_destroy()
749 drm_crtc_cleanup(crtc); in nv_crtc_destroy()
762 nv_crtc_gamma_load(struct drm_crtc *crtc) in nv_crtc_gamma_load() argument
764 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_gamma_load()
771 r = crtc->gamma_store; in nv_crtc_gamma_load()
772 g = r + crtc->gamma_size; in nv_crtc_gamma_load()
773 b = g + crtc->gamma_size; in nv_crtc_gamma_load()
785 nv_crtc_disable(struct drm_crtc *crtc) in nv_crtc_disable() argument
787 struct nv04_display *disp = nv04_display(crtc->dev); in nv_crtc_disable()
788 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_disable()
795 nv_crtc_gamma_set(struct drm_crtc *crtc, u16 *r, u16 *g, u16 *b, in nv_crtc_gamma_set() argument
799 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv_crtc_gamma_set()
811 nv_crtc_gamma_load(crtc); in nv_crtc_gamma_set()
817 nv04_crtc_do_mode_set_base(struct drm_crtc *crtc, in nv04_crtc_do_mode_set_base() argument
821 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_do_mode_set_base()
822 struct drm_device *dev = crtc->dev; in nv04_crtc_do_mode_set_base()
832 if (!atomic && !crtc->primary->fb) { in nv04_crtc_do_mode_set_base()
844 drm_fb = crtc->primary->fb; in nv04_crtc_do_mode_set_base()
845 fb = nouveau_framebuffer(crtc->primary->fb); in nv04_crtc_do_mode_set_base()
852 nv_crtc_gamma_load(crtc); in nv04_crtc_do_mode_set_base()
856 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] &= ~3; in nv04_crtc_do_mode_set_base()
857 regp->CRTC[NV_CIO_CRE_PIXEL_INDEX] |= (drm_fb->format->depth + 1) / 8; in nv04_crtc_do_mode_set_base()
861 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_PIXEL_INDEX); in nv04_crtc_do_mode_set_base()
865 regp->CRTC[NV_CIO_CR_OFFSET_INDEX] = drm_fb->pitches[0] >> 3; in nv04_crtc_do_mode_set_base()
866 regp->CRTC[NV_CIO_CRE_RPC0_INDEX] = in nv04_crtc_do_mode_set_base()
868 regp->CRTC[NV_CIO_CRE_42] = in nv04_crtc_do_mode_set_base()
870 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_RPC0_INDEX); in nv04_crtc_do_mode_set_base()
871 crtc_wr_cio_state(crtc, regp, NV_CIO_CR_OFFSET_INDEX); in nv04_crtc_do_mode_set_base()
872 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_42); in nv04_crtc_do_mode_set_base()
880 nouveau_calc_arb(dev, crtc->mode.clock, drm_fb->format->cpp[0] * 8, in nv04_crtc_do_mode_set_base()
883 regp->CRTC[NV_CIO_CRE_FF_INDEX] = arb_burst; in nv04_crtc_do_mode_set_base()
884 regp->CRTC[NV_CIO_CRE_FFLWM__INDEX] = arb_lwm & 0xff; in nv04_crtc_do_mode_set_base()
885 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FF_INDEX); in nv04_crtc_do_mode_set_base()
886 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_FFLWM__INDEX); in nv04_crtc_do_mode_set_base()
889 regp->CRTC[NV_CIO_CRE_47] = arb_lwm >> 8; in nv04_crtc_do_mode_set_base()
890 crtc_wr_cio_state(crtc, regp, NV_CIO_CRE_47); in nv04_crtc_do_mode_set_base()
897 nv04_crtc_mode_set_base(struct drm_crtc *crtc, int x, int y, in nv04_crtc_mode_set_base() argument
900 int ret = nv_crtc_swap_fbs(crtc, old_fb); in nv04_crtc_mode_set_base()
903 return nv04_crtc_do_mode_set_base(crtc, old_fb, x, y, false); in nv04_crtc_mode_set_base()
907 nv04_crtc_mode_set_base_atomic(struct drm_crtc *crtc, in nv04_crtc_mode_set_base_atomic() argument
911 struct nouveau_drm *drm = nouveau_drm(crtc->dev); in nv04_crtc_mode_set_base_atomic()
919 return nv04_crtc_do_mode_set_base(crtc, fb, x, y, true); in nv04_crtc_mode_set_base_atomic()
983 nv04_crtc_cursor_set(struct drm_crtc *crtc, struct drm_file *file_priv, in nv04_crtc_cursor_set() argument
986 struct nouveau_drm *drm = nouveau_drm(crtc->dev); in nv04_crtc_cursor_set()
988 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_cursor_set()
1025 nv04_crtc_cursor_move(struct drm_crtc *crtc, int x, int y) in nv04_crtc_cursor_move() argument
1027 struct nouveau_crtc *nv_crtc = nouveau_crtc(crtc); in nv04_crtc_cursor_move()
1040 struct drm_crtc *crtc; in nouveau_crtc_set_config() local
1042 if (!set || !set->crtc) in nouveau_crtc_set_config()
1045 dev = set->crtc->dev; in nouveau_crtc_set_config()
1057 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { in nouveau_crtc_set_config()
1058 if (crtc->enabled) in nouveau_crtc_set_config()