Lines Matching full:dispc
21 #define DSS_SUBSYS_NAME "DISPC"
48 #include "dispc.h"
52 /* DISPC */
61 #define REG_GET(dispc, idx, start, end) \ argument
62 FLD_GET(dispc_read_reg(dispc, idx), start, end)
64 #define REG_FLD_MOD(dispc, idx, val, start, end) \ argument
65 dispc_write_reg(dispc, idx, \
66 FLD_MOD(dispc_read_reg(dispc, idx), val, start, end))
68 /* DISPC has feature id */
111 int (*calc_scaling)(struct dispc_device *dispc,
139 /* revert to the OMAP4 mechanism of DISPC Smart Standby operation */
229 /* DISPC register field id */
355 static unsigned long dispc_fclk_rate(struct dispc_device *dispc);
356 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc);
357 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc,
359 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc,
362 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc,
364 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc,
367 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask);
369 static inline void dispc_write_reg(struct dispc_device *dispc, u16 idx, u32 val) in dispc_write_reg() argument
371 __raw_writel(val, dispc->base + idx); in dispc_write_reg()
374 static inline u32 dispc_read_reg(struct dispc_device *dispc, u16 idx) in dispc_read_reg() argument
376 return __raw_readl(dispc->base + idx); in dispc_read_reg()
379 static u32 mgr_fld_read(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_read() argument
384 return REG_GET(dispc, rfld.reg, rfld.high, rfld.low); in mgr_fld_read()
387 static void mgr_fld_write(struct dispc_device *dispc, enum omap_channel channel, in mgr_fld_write() argument
395 spin_lock_irqsave(&dispc->control_lock, flags); in mgr_fld_write()
396 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
397 spin_unlock_irqrestore(&dispc->control_lock, flags); in mgr_fld_write()
399 REG_FLD_MOD(dispc, rfld.reg, val, rfld.high, rfld.low); in mgr_fld_write()
403 static int dispc_get_num_ovls(struct dispc_device *dispc) in dispc_get_num_ovls() argument
405 return dispc->feat->num_ovls; in dispc_get_num_ovls()
408 static int dispc_get_num_mgrs(struct dispc_device *dispc) in dispc_get_num_mgrs() argument
410 return dispc->feat->num_mgrs; in dispc_get_num_mgrs()
413 static void dispc_get_reg_field(struct dispc_device *dispc, in dispc_get_reg_field() argument
417 if (id >= dispc->feat->num_reg_fields) in dispc_get_reg_field()
420 *start = dispc->feat->reg_fields[id].start; in dispc_get_reg_field()
421 *end = dispc->feat->reg_fields[id].end; in dispc_get_reg_field()
424 static bool dispc_has_feature(struct dispc_device *dispc, in dispc_has_feature() argument
429 for (i = 0; i < dispc->feat->num_features; i++) { in dispc_has_feature()
430 if (dispc->feat->features[i] == id) in dispc_has_feature()
437 #define SR(dispc, reg) \ argument
438 dispc->ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(dispc, DISPC_##reg)
439 #define RR(dispc, reg) \ argument
440 dispc_write_reg(dispc, DISPC_##reg, dispc->ctx[DISPC_##reg / sizeof(u32)])
442 static void dispc_save_context(struct dispc_device *dispc) in dispc_save_context() argument
448 SR(dispc, IRQENABLE); in dispc_save_context()
449 SR(dispc, CONTROL); in dispc_save_context()
450 SR(dispc, CONFIG); in dispc_save_context()
451 SR(dispc, LINE_NUMBER); in dispc_save_context()
452 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_save_context()
453 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_save_context()
454 SR(dispc, GLOBAL_ALPHA); in dispc_save_context()
455 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_save_context()
456 SR(dispc, CONTROL2); in dispc_save_context()
457 SR(dispc, CONFIG2); in dispc_save_context()
459 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_save_context()
460 SR(dispc, CONTROL3); in dispc_save_context()
461 SR(dispc, CONFIG3); in dispc_save_context()
464 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_save_context()
465 SR(dispc, DEFAULT_COLOR(i)); in dispc_save_context()
466 SR(dispc, TRANS_COLOR(i)); in dispc_save_context()
467 SR(dispc, SIZE_MGR(i)); in dispc_save_context()
470 SR(dispc, TIMING_H(i)); in dispc_save_context()
471 SR(dispc, TIMING_V(i)); in dispc_save_context()
472 SR(dispc, POL_FREQ(i)); in dispc_save_context()
473 SR(dispc, DIVISORo(i)); in dispc_save_context()
475 SR(dispc, DATA_CYCLE1(i)); in dispc_save_context()
476 SR(dispc, DATA_CYCLE2(i)); in dispc_save_context()
477 SR(dispc, DATA_CYCLE3(i)); in dispc_save_context()
479 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_save_context()
480 SR(dispc, CPR_COEF_R(i)); in dispc_save_context()
481 SR(dispc, CPR_COEF_G(i)); in dispc_save_context()
482 SR(dispc, CPR_COEF_B(i)); in dispc_save_context()
486 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_save_context()
487 SR(dispc, OVL_BA0(i)); in dispc_save_context()
488 SR(dispc, OVL_BA1(i)); in dispc_save_context()
489 SR(dispc, OVL_POSITION(i)); in dispc_save_context()
490 SR(dispc, OVL_SIZE(i)); in dispc_save_context()
491 SR(dispc, OVL_ATTRIBUTES(i)); in dispc_save_context()
492 SR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_save_context()
493 SR(dispc, OVL_ROW_INC(i)); in dispc_save_context()
494 SR(dispc, OVL_PIXEL_INC(i)); in dispc_save_context()
495 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_save_context()
496 SR(dispc, OVL_PRELOAD(i)); in dispc_save_context()
498 SR(dispc, OVL_WINDOW_SKIP(i)); in dispc_save_context()
499 SR(dispc, OVL_TABLE_BA(i)); in dispc_save_context()
502 SR(dispc, OVL_FIR(i)); in dispc_save_context()
503 SR(dispc, OVL_PICTURE_SIZE(i)); in dispc_save_context()
504 SR(dispc, OVL_ACCU0(i)); in dispc_save_context()
505 SR(dispc, OVL_ACCU1(i)); in dispc_save_context()
508 SR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_save_context()
511 SR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_save_context()
514 SR(dispc, OVL_CONV_COEF(i, j)); in dispc_save_context()
516 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_save_context()
518 SR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_save_context()
521 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_save_context()
522 SR(dispc, OVL_BA0_UV(i)); in dispc_save_context()
523 SR(dispc, OVL_BA1_UV(i)); in dispc_save_context()
524 SR(dispc, OVL_FIR2(i)); in dispc_save_context()
525 SR(dispc, OVL_ACCU2_0(i)); in dispc_save_context()
526 SR(dispc, OVL_ACCU2_1(i)); in dispc_save_context()
529 SR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_save_context()
532 SR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_save_context()
535 SR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_save_context()
537 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_save_context()
538 SR(dispc, OVL_ATTRIBUTES2(i)); in dispc_save_context()
541 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_save_context()
542 SR(dispc, DIVISOR); in dispc_save_context()
544 dispc->ctx_valid = true; in dispc_save_context()
549 static void dispc_restore_context(struct dispc_device *dispc) in dispc_restore_context() argument
555 if (!dispc->ctx_valid) in dispc_restore_context()
558 /*RR(dispc, IRQENABLE);*/ in dispc_restore_context()
559 /*RR(dispc, CONTROL);*/ in dispc_restore_context()
560 RR(dispc, CONFIG); in dispc_restore_context()
561 RR(dispc, LINE_NUMBER); in dispc_restore_context()
562 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_restore_context()
563 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_restore_context()
564 RR(dispc, GLOBAL_ALPHA); in dispc_restore_context()
565 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
566 RR(dispc, CONFIG2); in dispc_restore_context()
567 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
568 RR(dispc, CONFIG3); in dispc_restore_context()
570 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_restore_context()
571 RR(dispc, DEFAULT_COLOR(i)); in dispc_restore_context()
572 RR(dispc, TRANS_COLOR(i)); in dispc_restore_context()
573 RR(dispc, SIZE_MGR(i)); in dispc_restore_context()
576 RR(dispc, TIMING_H(i)); in dispc_restore_context()
577 RR(dispc, TIMING_V(i)); in dispc_restore_context()
578 RR(dispc, POL_FREQ(i)); in dispc_restore_context()
579 RR(dispc, DIVISORo(i)); in dispc_restore_context()
581 RR(dispc, DATA_CYCLE1(i)); in dispc_restore_context()
582 RR(dispc, DATA_CYCLE2(i)); in dispc_restore_context()
583 RR(dispc, DATA_CYCLE3(i)); in dispc_restore_context()
585 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_restore_context()
586 RR(dispc, CPR_COEF_R(i)); in dispc_restore_context()
587 RR(dispc, CPR_COEF_G(i)); in dispc_restore_context()
588 RR(dispc, CPR_COEF_B(i)); in dispc_restore_context()
592 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_restore_context()
593 RR(dispc, OVL_BA0(i)); in dispc_restore_context()
594 RR(dispc, OVL_BA1(i)); in dispc_restore_context()
595 RR(dispc, OVL_POSITION(i)); in dispc_restore_context()
596 RR(dispc, OVL_SIZE(i)); in dispc_restore_context()
597 RR(dispc, OVL_ATTRIBUTES(i)); in dispc_restore_context()
598 RR(dispc, OVL_FIFO_THRESHOLD(i)); in dispc_restore_context()
599 RR(dispc, OVL_ROW_INC(i)); in dispc_restore_context()
600 RR(dispc, OVL_PIXEL_INC(i)); in dispc_restore_context()
601 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_restore_context()
602 RR(dispc, OVL_PRELOAD(i)); in dispc_restore_context()
604 RR(dispc, OVL_WINDOW_SKIP(i)); in dispc_restore_context()
605 RR(dispc, OVL_TABLE_BA(i)); in dispc_restore_context()
608 RR(dispc, OVL_FIR(i)); in dispc_restore_context()
609 RR(dispc, OVL_PICTURE_SIZE(i)); in dispc_restore_context()
610 RR(dispc, OVL_ACCU0(i)); in dispc_restore_context()
611 RR(dispc, OVL_ACCU1(i)); in dispc_restore_context()
614 RR(dispc, OVL_FIR_COEF_H(i, j)); in dispc_restore_context()
617 RR(dispc, OVL_FIR_COEF_HV(i, j)); in dispc_restore_context()
620 RR(dispc, OVL_CONV_COEF(i, j)); in dispc_restore_context()
622 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_restore_context()
624 RR(dispc, OVL_FIR_COEF_V(i, j)); in dispc_restore_context()
627 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_restore_context()
628 RR(dispc, OVL_BA0_UV(i)); in dispc_restore_context()
629 RR(dispc, OVL_BA1_UV(i)); in dispc_restore_context()
630 RR(dispc, OVL_FIR2(i)); in dispc_restore_context()
631 RR(dispc, OVL_ACCU2_0(i)); in dispc_restore_context()
632 RR(dispc, OVL_ACCU2_1(i)); in dispc_restore_context()
635 RR(dispc, OVL_FIR_COEF_H2(i, j)); in dispc_restore_context()
638 RR(dispc, OVL_FIR_COEF_HV2(i, j)); in dispc_restore_context()
641 RR(dispc, OVL_FIR_COEF_V2(i, j)); in dispc_restore_context()
643 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_restore_context()
644 RR(dispc, OVL_ATTRIBUTES2(i)); in dispc_restore_context()
647 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_restore_context()
648 RR(dispc, DIVISOR); in dispc_restore_context()
651 RR(dispc, CONTROL); in dispc_restore_context()
652 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_context()
653 RR(dispc, CONTROL2); in dispc_restore_context()
654 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_context()
655 RR(dispc, CONTROL3); in dispc_restore_context()
657 dispc_clear_irqstatus(dispc, DISPC_IRQ_SYNC_LOST_DIGIT); in dispc_restore_context()
663 RR(dispc, IRQENABLE); in dispc_restore_context()
671 int dispc_runtime_get(struct dispc_device *dispc) in dispc_runtime_get() argument
677 r = pm_runtime_get_sync(&dispc->pdev->dev); in dispc_runtime_get()
682 void dispc_runtime_put(struct dispc_device *dispc) in dispc_runtime_put() argument
688 r = pm_runtime_put_sync(&dispc->pdev->dev); in dispc_runtime_put()
692 static u32 dispc_mgr_get_vsync_irq(struct dispc_device *dispc, in dispc_mgr_get_vsync_irq() argument
698 static u32 dispc_mgr_get_framedone_irq(struct dispc_device *dispc, in dispc_mgr_get_framedone_irq() argument
701 if (channel == OMAP_DSS_CHANNEL_DIGIT && dispc->feat->no_framedone_tv) in dispc_mgr_get_framedone_irq()
707 static u32 dispc_mgr_get_sync_lost_irq(struct dispc_device *dispc, in dispc_mgr_get_sync_lost_irq() argument
713 static u32 dispc_wb_get_framedone_irq(struct dispc_device *dispc) in dispc_wb_get_framedone_irq() argument
718 static void dispc_mgr_enable(struct dispc_device *dispc, in dispc_mgr_enable() argument
721 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_ENABLE, enable); in dispc_mgr_enable()
723 mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_enable()
726 static bool dispc_mgr_is_enabled(struct dispc_device *dispc, in dispc_mgr_is_enabled() argument
729 return !!mgr_fld_read(dispc, channel, DISPC_MGR_FLD_ENABLE); in dispc_mgr_is_enabled()
732 static bool dispc_mgr_go_busy(struct dispc_device *dispc, in dispc_mgr_go_busy() argument
735 return mgr_fld_read(dispc, channel, DISPC_MGR_FLD_GO) == 1; in dispc_mgr_go_busy()
738 static void dispc_mgr_go(struct dispc_device *dispc, enum omap_channel channel) in dispc_mgr_go() argument
740 WARN_ON(!dispc_mgr_is_enabled(dispc, channel)); in dispc_mgr_go()
741 WARN_ON(dispc_mgr_go_busy(dispc, channel)); in dispc_mgr_go()
745 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_GO, 1); in dispc_mgr_go()
748 static bool dispc_wb_go_busy(struct dispc_device *dispc) in dispc_wb_go_busy() argument
750 return REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go_busy()
753 static void dispc_wb_go(struct dispc_device *dispc) in dispc_wb_go() argument
758 enable = REG_GET(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 0) == 1; in dispc_wb_go()
763 go = REG_GET(dispc, DISPC_CONTROL2, 6, 6) == 1; in dispc_wb_go()
769 REG_FLD_MOD(dispc, DISPC_CONTROL2, 1, 6, 6); in dispc_wb_go()
772 static void dispc_ovl_write_firh_reg(struct dispc_device *dispc, in dispc_ovl_write_firh_reg() argument
776 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H(plane, reg), value); in dispc_ovl_write_firh_reg()
779 static void dispc_ovl_write_firhv_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv_reg() argument
783 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV(plane, reg), value); in dispc_ovl_write_firhv_reg()
786 static void dispc_ovl_write_firv_reg(struct dispc_device *dispc, in dispc_ovl_write_firv_reg() argument
790 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V(plane, reg), value); in dispc_ovl_write_firv_reg()
793 static void dispc_ovl_write_firh2_reg(struct dispc_device *dispc, in dispc_ovl_write_firh2_reg() argument
799 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_H2(plane, reg), value); in dispc_ovl_write_firh2_reg()
802 static void dispc_ovl_write_firhv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firhv2_reg() argument
808 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_HV2(plane, reg), value); in dispc_ovl_write_firhv2_reg()
811 static void dispc_ovl_write_firv2_reg(struct dispc_device *dispc, in dispc_ovl_write_firv2_reg() argument
817 dispc_write_reg(dispc, DISPC_OVL_FIR_COEF_V2(plane, reg), value); in dispc_ovl_write_firv2_reg()
820 static void dispc_ovl_set_scale_coef(struct dispc_device *dispc, in dispc_ovl_set_scale_coef() argument
832 dev_err(&dispc->pdev->dev, "%s: failed to find scale coefs\n", in dispc_ovl_set_scale_coef()
850 dispc_ovl_write_firh_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
851 dispc_ovl_write_firhv_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
853 dispc_ovl_write_firh2_reg(dispc, plane, i, h); in dispc_ovl_set_scale_coef()
854 dispc_ovl_write_firhv2_reg(dispc, plane, i, hv); in dispc_ovl_set_scale_coef()
865 dispc_ovl_write_firv_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
867 dispc_ovl_write_firv2_reg(dispc, plane, i, v); in dispc_ovl_set_scale_coef()
882 static void dispc_ovl_write_color_conv_coef(struct dispc_device *dispc, in dispc_ovl_write_color_conv_coef() argument
888 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->rcr, ct->ry)); in dispc_ovl_write_color_conv_coef()
889 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->gy, ct->rcb)); in dispc_ovl_write_color_conv_coef()
890 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->gcb, ct->gcr)); in dispc_ovl_write_color_conv_coef()
891 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->bcr, ct->by)); in dispc_ovl_write_color_conv_coef()
892 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->bcb)); in dispc_ovl_write_color_conv_coef()
894 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_ovl_write_color_conv_coef()
899 static void dispc_wb_write_color_conv_coef(struct dispc_device *dispc, in dispc_wb_write_color_conv_coef() argument
906 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 0), CVAL(ct->yg, ct->yr)); in dispc_wb_write_color_conv_coef()
907 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 1), CVAL(ct->crr, ct->yb)); in dispc_wb_write_color_conv_coef()
908 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 2), CVAL(ct->crb, ct->crg)); in dispc_wb_write_color_conv_coef()
909 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 3), CVAL(ct->cbg, ct->cbr)); in dispc_wb_write_color_conv_coef()
910 dispc_write_reg(dispc, DISPC_OVL_CONV_COEF(plane, 4), CVAL(0, ct->cbb)); in dispc_wb_write_color_conv_coef()
912 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), ct->full_range, 11, 11); in dispc_wb_write_color_conv_coef()
917 static void dispc_setup_color_conv_coef(struct dispc_device *dispc) in dispc_setup_color_conv_coef() argument
920 int num_ovl = dispc_get_num_ovls(dispc); in dispc_setup_color_conv_coef()
939 dispc_ovl_write_color_conv_coef(dispc, i, &coefs_yuv2rgb_bt601_lim); in dispc_setup_color_conv_coef()
941 if (dispc->feat->has_writeback) in dispc_setup_color_conv_coef()
942 dispc_wb_write_color_conv_coef(dispc, &coefs_rgb2yuv_bt601_lim); in dispc_setup_color_conv_coef()
945 static void dispc_ovl_set_ba0(struct dispc_device *dispc, in dispc_ovl_set_ba0() argument
948 dispc_write_reg(dispc, DISPC_OVL_BA0(plane), paddr); in dispc_ovl_set_ba0()
951 static void dispc_ovl_set_ba1(struct dispc_device *dispc, in dispc_ovl_set_ba1() argument
954 dispc_write_reg(dispc, DISPC_OVL_BA1(plane), paddr); in dispc_ovl_set_ba1()
957 static void dispc_ovl_set_ba0_uv(struct dispc_device *dispc, in dispc_ovl_set_ba0_uv() argument
960 dispc_write_reg(dispc, DISPC_OVL_BA0_UV(plane), paddr); in dispc_ovl_set_ba0_uv()
963 static void dispc_ovl_set_ba1_uv(struct dispc_device *dispc, in dispc_ovl_set_ba1_uv() argument
966 dispc_write_reg(dispc, DISPC_OVL_BA1_UV(plane), paddr); in dispc_ovl_set_ba1_uv()
969 static void dispc_ovl_set_pos(struct dispc_device *dispc, in dispc_ovl_set_pos() argument
980 dispc_write_reg(dispc, DISPC_OVL_POSITION(plane), val); in dispc_ovl_set_pos()
983 static void dispc_ovl_set_input_size(struct dispc_device *dispc, in dispc_ovl_set_input_size() argument
990 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_input_size()
992 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_input_size()
995 static void dispc_ovl_set_output_size(struct dispc_device *dispc, in dispc_ovl_set_output_size() argument
1006 dispc_write_reg(dispc, DISPC_OVL_PICTURE_SIZE(plane), val); in dispc_ovl_set_output_size()
1008 dispc_write_reg(dispc, DISPC_OVL_SIZE(plane), val); in dispc_ovl_set_output_size()
1011 static void dispc_ovl_set_zorder(struct dispc_device *dispc, in dispc_ovl_set_zorder() argument
1018 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26); in dispc_ovl_set_zorder()
1021 static void dispc_ovl_enable_zorder_planes(struct dispc_device *dispc) in dispc_ovl_enable_zorder_planes() argument
1025 if (!dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_ovl_enable_zorder_planes()
1028 for (i = 0; i < dispc_get_num_ovls(dispc); i++) in dispc_ovl_enable_zorder_planes()
1029 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(i), 1, 25, 25); in dispc_ovl_enable_zorder_planes()
1032 static void dispc_ovl_set_pre_mult_alpha(struct dispc_device *dispc, in dispc_ovl_set_pre_mult_alpha() argument
1040 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28); in dispc_ovl_set_pre_mult_alpha()
1043 static void dispc_ovl_setup_global_alpha(struct dispc_device *dispc, in dispc_ovl_setup_global_alpha() argument
1055 REG_FLD_MOD(dispc, DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift); in dispc_ovl_setup_global_alpha()
1058 static void dispc_ovl_set_pix_inc(struct dispc_device *dispc, in dispc_ovl_set_pix_inc() argument
1061 dispc_write_reg(dispc, DISPC_OVL_PIXEL_INC(plane), inc); in dispc_ovl_set_pix_inc()
1064 static void dispc_ovl_set_row_inc(struct dispc_device *dispc, in dispc_ovl_set_row_inc() argument
1067 dispc_write_reg(dispc, DISPC_OVL_ROW_INC(plane), inc); in dispc_ovl_set_row_inc()
1070 static void dispc_ovl_set_color_mode(struct dispc_device *dispc, in dispc_ovl_set_color_mode() argument
1140 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), m, 4, 1); in dispc_ovl_set_color_mode()
1155 static void dispc_ovl_configure_burst_type(struct dispc_device *dispc, in dispc_ovl_configure_burst_type() argument
1159 if (dispc_has_feature(dispc, FEAT_BURST_2D) == 0) in dispc_ovl_configure_burst_type()
1163 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 1, 29, 29); in dispc_ovl_configure_burst_type()
1165 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), 0, 29, 29); in dispc_ovl_configure_burst_type()
1168 static void dispc_ovl_set_channel_out(struct dispc_device *dispc, in dispc_ovl_set_channel_out() argument
1190 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_channel_out()
1191 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_ovl_set_channel_out()
1206 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_ovl_set_channel_out()
1228 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_channel_out()
1231 static enum omap_channel dispc_ovl_get_channel_out(struct dispc_device *dispc, in dispc_ovl_get_channel_out() argument
1251 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_get_channel_out()
1256 if (!dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_ovl_get_channel_out()
1272 static void dispc_ovl_set_burst_size(struct dispc_device *dispc, in dispc_ovl_set_burst_size() argument
1280 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), burst_size, in dispc_ovl_set_burst_size()
1284 static void dispc_configure_burst_sizes(struct dispc_device *dispc) in dispc_configure_burst_sizes() argument
1290 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_configure_burst_sizes()
1291 dispc_ovl_set_burst_size(dispc, i, burst_size); in dispc_configure_burst_sizes()
1292 if (dispc->feat->has_writeback) in dispc_configure_burst_sizes()
1293 dispc_ovl_set_burst_size(dispc, OMAP_DSS_WB, burst_size); in dispc_configure_burst_sizes()
1296 static u32 dispc_ovl_get_burst_size(struct dispc_device *dispc, in dispc_ovl_get_burst_size() argument
1300 return dispc->feat->burst_size_unit * 8; in dispc_ovl_get_burst_size()
1303 static bool dispc_ovl_color_mode_supported(struct dispc_device *dispc, in dispc_ovl_color_mode_supported() argument
1309 modes = dispc->feat->supported_color_modes[plane]; in dispc_ovl_color_mode_supported()
1319 static const u32 *dispc_ovl_get_color_modes(struct dispc_device *dispc, in dispc_ovl_get_color_modes() argument
1322 return dispc->feat->supported_color_modes[plane]; in dispc_ovl_get_color_modes()
1325 static void dispc_mgr_enable_cpr(struct dispc_device *dispc, in dispc_mgr_enable_cpr() argument
1331 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_CPR, enable); in dispc_mgr_enable_cpr()
1334 static void dispc_mgr_set_cpr_coef(struct dispc_device *dispc, in dispc_mgr_set_cpr_coef() argument
1350 dispc_write_reg(dispc, DISPC_CPR_COEF_R(channel), coef_r); in dispc_mgr_set_cpr_coef()
1351 dispc_write_reg(dispc, DISPC_CPR_COEF_G(channel), coef_g); in dispc_mgr_set_cpr_coef()
1352 dispc_write_reg(dispc, DISPC_CPR_COEF_B(channel), coef_b); in dispc_mgr_set_cpr_coef()
1355 static void dispc_ovl_set_vid_color_conv(struct dispc_device *dispc, in dispc_ovl_set_vid_color_conv() argument
1362 val = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_vid_color_conv()
1364 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), val); in dispc_ovl_set_vid_color_conv()
1367 static void dispc_ovl_enable_replication(struct dispc_device *dispc, in dispc_ovl_enable_replication() argument
1379 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift); in dispc_ovl_enable_replication()
1382 static void dispc_mgr_set_size(struct dispc_device *dispc, in dispc_mgr_set_size() argument
1387 val = FLD_VAL(height - 1, dispc->feat->mgr_height_start, 16) | in dispc_mgr_set_size()
1388 FLD_VAL(width - 1, dispc->feat->mgr_width_start, 0); in dispc_mgr_set_size()
1390 dispc_write_reg(dispc, DISPC_SIZE_MGR(channel), val); in dispc_mgr_set_size()
1393 static void dispc_init_fifos(struct dispc_device *dispc) in dispc_init_fifos() argument
1401 unit = dispc->feat->buffer_size_unit; in dispc_init_fifos()
1403 dispc_get_reg_field(dispc, FEAT_REG_FIFOSIZE, &start, &end); in dispc_init_fifos()
1405 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_init_fifos()
1406 size = REG_GET(dispc, DISPC_OVL_FIFO_SIZE_STATUS(fifo), in dispc_init_fifos()
1409 dispc->fifo_size[fifo] = size; in dispc_init_fifos()
1415 dispc->fifo_assignment[fifo] = fifo; in dispc_init_fifos()
1425 if (dispc->feat->gfx_fifo_workaround) { in dispc_init_fifos()
1428 v = dispc_read_reg(dispc, DISPC_GLOBAL_BUFFER); in dispc_init_fifos()
1435 dispc_write_reg(dispc, DISPC_GLOBAL_BUFFER, v); in dispc_init_fifos()
1437 dispc->fifo_assignment[OMAP_DSS_GFX] = OMAP_DSS_WB; in dispc_init_fifos()
1438 dispc->fifo_assignment[OMAP_DSS_WB] = OMAP_DSS_GFX; in dispc_init_fifos()
1444 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_fifos()
1449 dispc_ovl_compute_fifo_thresholds(dispc, i, &low, &high, in dispc_init_fifos()
1452 dispc_ovl_set_fifo_threshold(dispc, i, low, high); in dispc_init_fifos()
1455 if (dispc->feat->has_writeback) { in dispc_init_fifos()
1460 dispc_ovl_compute_fifo_thresholds(dispc, OMAP_DSS_WB, in dispc_init_fifos()
1464 dispc_ovl_set_fifo_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_fifos()
1468 static u32 dispc_ovl_get_fifo_size(struct dispc_device *dispc, in dispc_ovl_get_fifo_size() argument
1474 for (fifo = 0; fifo < dispc->feat->num_fifos; ++fifo) { in dispc_ovl_get_fifo_size()
1475 if (dispc->fifo_assignment[fifo] == plane) in dispc_ovl_get_fifo_size()
1476 size += dispc->fifo_size[fifo]; in dispc_ovl_get_fifo_size()
1482 void dispc_ovl_set_fifo_threshold(struct dispc_device *dispc, in dispc_ovl_set_fifo_threshold() argument
1489 unit = dispc->feat->buffer_size_unit; in dispc_ovl_set_fifo_threshold()
1497 dispc_get_reg_field(dispc, FEAT_REG_FIFOHIGHTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1499 dispc_get_reg_field(dispc, FEAT_REG_FIFOLOWTHRESHOLD, in dispc_ovl_set_fifo_threshold()
1504 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1506 REG_GET(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1510 dispc_write_reg(dispc, DISPC_OVL_FIFO_THRESHOLD(plane), in dispc_ovl_set_fifo_threshold()
1519 if (dispc_has_feature(dispc, FEAT_PRELOAD) && in dispc_ovl_set_fifo_threshold()
1520 dispc->feat->set_max_preload && plane != OMAP_DSS_WB) in dispc_ovl_set_fifo_threshold()
1521 dispc_write_reg(dispc, DISPC_OVL_PRELOAD(plane), in dispc_ovl_set_fifo_threshold()
1525 void dispc_enable_fifomerge(struct dispc_device *dispc, bool enable) in dispc_enable_fifomerge() argument
1527 if (!dispc_has_feature(dispc, FEAT_FIFO_MERGE)) { in dispc_enable_fifomerge()
1533 REG_FLD_MOD(dispc, DISPC_CONFIG, enable ? 1 : 0, 14, 14); in dispc_enable_fifomerge()
1536 void dispc_ovl_compute_fifo_thresholds(struct dispc_device *dispc, in dispc_ovl_compute_fifo_thresholds() argument
1545 unsigned int buf_unit = dispc->feat->buffer_size_unit; in dispc_ovl_compute_fifo_thresholds()
1549 burst_size = dispc_ovl_get_burst_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1550 ovl_fifo_size = dispc_ovl_get_fifo_size(dispc, plane); in dispc_ovl_compute_fifo_thresholds()
1554 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) in dispc_ovl_compute_fifo_thresholds()
1555 total_fifo_size += dispc_ovl_get_fifo_size(dispc, i); in dispc_ovl_compute_fifo_thresholds()
1566 if (manual_update && dispc_has_feature(dispc, FEAT_OMAP3_DSI_FIFO_BUG)) { in dispc_ovl_compute_fifo_thresholds()
1583 static void dispc_ovl_set_mflag(struct dispc_device *dispc, in dispc_ovl_set_mflag() argument
1593 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable, bit, bit); in dispc_ovl_set_mflag()
1596 static void dispc_ovl_set_mflag_threshold(struct dispc_device *dispc, in dispc_ovl_set_mflag_threshold() argument
1600 dispc_write_reg(dispc, DISPC_OVL_MFLAG_THRESHOLD(plane), in dispc_ovl_set_mflag_threshold()
1604 static void dispc_init_mflag(struct dispc_device *dispc) in dispc_init_mflag() argument
1618 dispc_write_reg(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE, in dispc_init_mflag()
1622 for (i = 0; i < dispc_get_num_ovls(dispc); ++i) { in dispc_init_mflag()
1623 u32 size = dispc_ovl_get_fifo_size(dispc, i); in dispc_init_mflag()
1624 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1627 dispc_ovl_set_mflag(dispc, i, true); in dispc_init_mflag()
1638 dispc_ovl_set_mflag_threshold(dispc, i, low, high); in dispc_init_mflag()
1641 if (dispc->feat->has_writeback) { in dispc_init_mflag()
1642 u32 size = dispc_ovl_get_fifo_size(dispc, OMAP_DSS_WB); in dispc_init_mflag()
1643 u32 unit = dispc->feat->buffer_size_unit; in dispc_init_mflag()
1646 dispc_ovl_set_mflag(dispc, OMAP_DSS_WB, true); in dispc_init_mflag()
1657 dispc_ovl_set_mflag_threshold(dispc, OMAP_DSS_WB, low, high); in dispc_init_mflag()
1661 static void dispc_ovl_set_fir(struct dispc_device *dispc, in dispc_ovl_set_fir() argument
1671 dispc_get_reg_field(dispc, FEAT_REG_FIRHINC, in dispc_ovl_set_fir()
1673 dispc_get_reg_field(dispc, FEAT_REG_FIRVINC, in dispc_ovl_set_fir()
1678 dispc_write_reg(dispc, DISPC_OVL_FIR(plane), val); in dispc_ovl_set_fir()
1681 dispc_write_reg(dispc, DISPC_OVL_FIR2(plane), val); in dispc_ovl_set_fir()
1685 static void dispc_ovl_set_vid_accu0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu0() argument
1692 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu0()
1694 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu0()
1700 dispc_write_reg(dispc, DISPC_OVL_ACCU0(plane), val); in dispc_ovl_set_vid_accu0()
1703 static void dispc_ovl_set_vid_accu1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu1() argument
1710 dispc_get_reg_field(dispc, FEAT_REG_HORIZONTALACCU, in dispc_ovl_set_vid_accu1()
1712 dispc_get_reg_field(dispc, FEAT_REG_VERTICALACCU, in dispc_ovl_set_vid_accu1()
1718 dispc_write_reg(dispc, DISPC_OVL_ACCU1(plane), val); in dispc_ovl_set_vid_accu1()
1721 static void dispc_ovl_set_vid_accu2_0(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_0() argument
1728 dispc_write_reg(dispc, DISPC_OVL_ACCU2_0(plane), val); in dispc_ovl_set_vid_accu2_0()
1731 static void dispc_ovl_set_vid_accu2_1(struct dispc_device *dispc, in dispc_ovl_set_vid_accu2_1() argument
1738 dispc_write_reg(dispc, DISPC_OVL_ACCU2_1(plane), val); in dispc_ovl_set_vid_accu2_1()
1741 static void dispc_ovl_set_scale_param(struct dispc_device *dispc, in dispc_ovl_set_scale_param() argument
1753 dispc_ovl_set_scale_coef(dispc, plane, fir_hinc, fir_vinc, five_taps, in dispc_ovl_set_scale_param()
1755 dispc_ovl_set_fir(dispc, plane, fir_hinc, fir_vinc, color_comp); in dispc_ovl_set_scale_param()
1758 static void dispc_ovl_set_accu_uv(struct dispc_device *dispc, in dispc_ovl_set_accu_uv() argument
1843 dispc_ovl_set_vid_accu2_0(dispc, plane, h_accu2_0, v_accu2_0); in dispc_ovl_set_accu_uv()
1844 dispc_ovl_set_vid_accu2_1(dispc, plane, h_accu2_1, v_accu2_1); in dispc_ovl_set_accu_uv()
1847 static void dispc_ovl_set_scaling_common(struct dispc_device *dispc, in dispc_ovl_set_scaling_common() argument
1859 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_common()
1862 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_ovl_set_scaling_common()
1871 if (dispc_has_feature(dispc, FEAT_RESIZECONF)) { in dispc_ovl_set_scaling_common()
1878 if (dispc_has_feature(dispc, FEAT_LINEBUFFERSPLIT)) { in dispc_ovl_set_scaling_common()
1883 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_ovl_set_scaling_common()
1898 dispc_ovl_set_vid_accu0(dispc, plane, 0, accu0); in dispc_ovl_set_scaling_common()
1899 dispc_ovl_set_vid_accu1(dispc, plane, 0, accu1); in dispc_ovl_set_scaling_common()
1902 static void dispc_ovl_set_scaling_uv(struct dispc_device *dispc, in dispc_ovl_set_scaling_uv() argument
1914 if (!dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) in dispc_ovl_set_scaling_uv()
1920 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1925 dispc_ovl_set_accu_uv(dispc, plane, orig_width, orig_height, out_width, in dispc_ovl_set_scaling_uv()
1968 dispc_ovl_set_scale_param(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling_uv()
1973 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), in dispc_ovl_set_scaling_uv()
1977 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5); in dispc_ovl_set_scaling_uv()
1979 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6); in dispc_ovl_set_scaling_uv()
1982 static void dispc_ovl_set_scaling(struct dispc_device *dispc, in dispc_ovl_set_scaling() argument
1992 dispc_ovl_set_scaling_common(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
1996 dispc_ovl_set_scaling_uv(dispc, plane, orig_width, orig_height, in dispc_ovl_set_scaling()
2001 static void dispc_ovl_set_rotation_attrs(struct dispc_device *dispc, in dispc_ovl_set_rotation_attrs() argument
2058 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12); in dispc_ovl_set_rotation_attrs()
2059 if (dispc_has_feature(dispc, FEAT_ROWREPEATENABLE)) in dispc_ovl_set_rotation_attrs()
2060 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2063 if (dispc_ovl_color_mode_supported(dispc, plane, DRM_FORMAT_NV12)) { in dispc_ovl_set_rotation_attrs()
2070 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), in dispc_ovl_set_rotation_attrs()
2192 * So, atleast DS-2 lines must have already been fetched by DISPC in check_horiz_timing_omap3()
2308 static int dispc_ovl_calc_scaling_24xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_24xx() argument
2322 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_24xx()
2329 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_24xx()
2332 *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_24xx()
2357 static int dispc_ovl_calc_scaling_34xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_34xx() argument
2370 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_34xx()
2387 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in dispc_ovl_calc_scaling_34xx()
2401 !*core_clk || *core_clk > dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling_34xx()
2445 static int dispc_ovl_calc_scaling_44xx(struct dispc_device *dispc, in dispc_ovl_calc_scaling_44xx() argument
2459 const int maxsinglelinewidth = dispc->feat->max_line_width; in dispc_ovl_calc_scaling_44xx()
2460 const int maxdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling_44xx()
2465 in_width_max = dispc_core_clk_rate(dispc) in dispc_ovl_calc_scaling_44xx()
2504 *core_clk = dispc->feat->calc_core_clk(pclk, in_width, in_height, in dispc_ovl_calc_scaling_44xx()
2512 static int dispc_ovl_calc_scaling(struct dispc_device *dispc, in dispc_ovl_calc_scaling() argument
2524 int maxhdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2525 int maxvdownscale = dispc->feat->max_downscale; in dispc_ovl_calc_scaling()
2560 dispc_has_feature(dispc, FEAT_BURST_2D)) ? in dispc_ovl_calc_scaling()
2573 ret = dispc->feat->calc_scaling(dispc, pclk, lclk, vm, width, height, in dispc_ovl_calc_scaling()
2593 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2595 if (!core_clk || core_clk > dispc_core_clk_rate(dispc)) { in dispc_ovl_calc_scaling()
2599 core_clk, dispc_core_clk_rate(dispc)); in dispc_ovl_calc_scaling()
2608 static int dispc_ovl_setup_common(struct dispc_device *dispc, in dispc_ovl_setup_common() argument
2633 unsigned long pclk = dispc_plane_pclk_rate(dispc, plane); in dispc_ovl_setup_common()
2634 unsigned long lclk = dispc_plane_lclk_rate(dispc, plane); in dispc_ovl_setup_common()
2666 if (!dispc_ovl_color_mode_supported(dispc, plane, fourcc)) in dispc_ovl_setup_common()
2669 r = dispc_ovl_calc_scaling(dispc, plane, pclk, lclk, caps, vm, in_width, in dispc_ovl_setup_common()
2734 dispc_ovl_set_color_mode(dispc, plane, fourcc); in dispc_ovl_setup_common()
2736 dispc_ovl_configure_burst_type(dispc, plane, rotation_type); in dispc_ovl_setup_common()
2738 if (dispc->feat->reverse_ilace_field_order) in dispc_ovl_setup_common()
2741 dispc_ovl_set_ba0(dispc, plane, paddr + offset0); in dispc_ovl_setup_common()
2742 dispc_ovl_set_ba1(dispc, plane, paddr + offset1); in dispc_ovl_setup_common()
2745 dispc_ovl_set_ba0_uv(dispc, plane, p_uv_addr + offset0); in dispc_ovl_setup_common()
2746 dispc_ovl_set_ba1_uv(dispc, plane, p_uv_addr + offset1); in dispc_ovl_setup_common()
2749 if (dispc->feat->last_pixel_inc_missing) in dispc_ovl_setup_common()
2752 dispc_ovl_set_row_inc(dispc, plane, row_inc); in dispc_ovl_setup_common()
2753 dispc_ovl_set_pix_inc(dispc, plane, pix_inc); in dispc_ovl_setup_common()
2758 dispc_ovl_set_pos(dispc, plane, caps, pos_x, pos_y); in dispc_ovl_setup_common()
2760 dispc_ovl_set_input_size(dispc, plane, in_width, in_height); in dispc_ovl_setup_common()
2763 dispc_ovl_set_scaling(dispc, plane, in_width, in_height, in dispc_ovl_setup_common()
2766 dispc_ovl_set_output_size(dispc, plane, out_width, out_height); in dispc_ovl_setup_common()
2767 dispc_ovl_set_vid_color_conv(dispc, plane, cconv); in dispc_ovl_setup_common()
2770 dispc_ovl_set_rotation_attrs(dispc, plane, rotation, rotation_type, in dispc_ovl_setup_common()
2773 dispc_ovl_set_zorder(dispc, plane, caps, zorder); in dispc_ovl_setup_common()
2774 dispc_ovl_set_pre_mult_alpha(dispc, plane, caps, pre_mult_alpha); in dispc_ovl_setup_common()
2775 dispc_ovl_setup_global_alpha(dispc, plane, caps, global_alpha); in dispc_ovl_setup_common()
2777 dispc_ovl_enable_replication(dispc, plane, caps, replication); in dispc_ovl_setup_common()
2782 static int dispc_ovl_setup(struct dispc_device *dispc, in dispc_ovl_setup() argument
2789 enum omap_overlay_caps caps = dispc->feat->overlay_caps[plane]; in dispc_ovl_setup()
2798 dispc_ovl_set_channel_out(dispc, plane, channel); in dispc_ovl_setup()
2800 r = dispc_ovl_setup_common(dispc, plane, caps, oi->paddr, oi->p_uv_addr, in dispc_ovl_setup()
2809 static int dispc_wb_setup(struct dispc_device *dispc, in dispc_wb_setup() argument
2833 r = dispc_ovl_setup_common(dispc, plane, caps, wi->paddr, wi->p_uv_addr, in dispc_wb_setup()
2858 l = dispc_read_reg(dispc, DISPC_OVL_ATTRIBUTES(plane)); in dispc_wb_setup()
2866 dispc_write_reg(dispc, DISPC_OVL_ATTRIBUTES(plane), l); in dispc_wb_setup()
2870 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), 0, 7, 0); in dispc_wb_setup()
2886 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES2(plane), wbdelay, 7, 0); in dispc_wb_setup()
2892 static bool dispc_has_writeback(struct dispc_device *dispc) in dispc_has_writeback() argument
2894 return dispc->feat->has_writeback; in dispc_has_writeback()
2897 static int dispc_ovl_enable(struct dispc_device *dispc, in dispc_ovl_enable() argument
2902 REG_FLD_MOD(dispc, DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0); in dispc_ovl_enable()
2908 dispc_mgr_get_supported_outputs(struct dispc_device *dispc, in dispc_mgr_get_supported_outputs() argument
2911 return dss_get_supported_outputs(dispc->dss, channel); in dispc_mgr_get_supported_outputs()
2914 static void dispc_lcd_enable_signal_polarity(struct dispc_device *dispc, in dispc_lcd_enable_signal_polarity() argument
2917 if (!dispc_has_feature(dispc, FEAT_LCDENABLEPOL)) in dispc_lcd_enable_signal_polarity()
2920 REG_FLD_MOD(dispc, DISPC_CONTROL, act_high ? 1 : 0, 29, 29); in dispc_lcd_enable_signal_polarity()
2923 void dispc_lcd_enable_signal(struct dispc_device *dispc, bool enable) in dispc_lcd_enable_signal() argument
2925 if (!dispc_has_feature(dispc, FEAT_LCDENABLESIGNAL)) in dispc_lcd_enable_signal()
2928 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 28, 28); in dispc_lcd_enable_signal()
2931 void dispc_pck_free_enable(struct dispc_device *dispc, bool enable) in dispc_pck_free_enable() argument
2933 if (!dispc_has_feature(dispc, FEAT_PCKFREEENABLE)) in dispc_pck_free_enable()
2936 REG_FLD_MOD(dispc, DISPC_CONTROL, enable ? 1 : 0, 27, 27); in dispc_pck_free_enable()
2939 static void dispc_mgr_enable_fifohandcheck(struct dispc_device *dispc, in dispc_mgr_enable_fifohandcheck() argument
2943 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_FIFOHANDCHECK, enable); in dispc_mgr_enable_fifohandcheck()
2947 static void dispc_mgr_set_lcd_type_tft(struct dispc_device *dispc, in dispc_mgr_set_lcd_type_tft() argument
2950 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STNTFT, 1); in dispc_mgr_set_lcd_type_tft()
2953 static void dispc_set_loadmode(struct dispc_device *dispc, in dispc_set_loadmode() argument
2956 REG_FLD_MOD(dispc, DISPC_CONFIG, mode, 2, 1); in dispc_set_loadmode()
2960 static void dispc_mgr_set_default_color(struct dispc_device *dispc, in dispc_mgr_set_default_color() argument
2963 dispc_write_reg(dispc, DISPC_DEFAULT_COLOR(channel), color); in dispc_mgr_set_default_color()
2966 static void dispc_mgr_set_trans_key(struct dispc_device *dispc, in dispc_mgr_set_trans_key() argument
2971 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKSELECTION, type); in dispc_mgr_set_trans_key()
2973 dispc_write_reg(dispc, DISPC_TRANS_COLOR(ch), trans_key); in dispc_mgr_set_trans_key()
2976 static void dispc_mgr_enable_trans_key(struct dispc_device *dispc, in dispc_mgr_enable_trans_key() argument
2979 mgr_fld_write(dispc, ch, DISPC_MGR_FLD_TCKENABLE, enable); in dispc_mgr_enable_trans_key()
2982 static void dispc_mgr_enable_alpha_fixed_zorder(struct dispc_device *dispc, in dispc_mgr_enable_alpha_fixed_zorder() argument
2986 if (!dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER)) in dispc_mgr_enable_alpha_fixed_zorder()
2990 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 18, 18); in dispc_mgr_enable_alpha_fixed_zorder()
2992 REG_FLD_MOD(dispc, DISPC_CONFIG, enable, 19, 19); in dispc_mgr_enable_alpha_fixed_zorder()
2995 static void dispc_mgr_setup(struct dispc_device *dispc, in dispc_mgr_setup() argument
2999 dispc_mgr_set_default_color(dispc, channel, info->default_color); in dispc_mgr_setup()
3000 dispc_mgr_set_trans_key(dispc, channel, info->trans_key_type, in dispc_mgr_setup()
3002 dispc_mgr_enable_trans_key(dispc, channel, info->trans_enabled); in dispc_mgr_setup()
3003 dispc_mgr_enable_alpha_fixed_zorder(dispc, channel, in dispc_mgr_setup()
3005 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_mgr_setup()
3006 dispc_mgr_enable_cpr(dispc, channel, info->cpr_enable); in dispc_mgr_setup()
3007 dispc_mgr_set_cpr_coef(dispc, channel, &info->cpr_coefs); in dispc_mgr_setup()
3011 static void dispc_mgr_set_tft_data_lines(struct dispc_device *dispc, in dispc_mgr_set_tft_data_lines() argument
3035 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_TFTDATALINES, code); in dispc_mgr_set_tft_data_lines()
3038 static void dispc_mgr_set_io_pad_mode(struct dispc_device *dispc, in dispc_mgr_set_io_pad_mode() argument
3062 l = dispc_read_reg(dispc, DISPC_CONTROL); in dispc_mgr_set_io_pad_mode()
3065 dispc_write_reg(dispc, DISPC_CONTROL, l); in dispc_mgr_set_io_pad_mode()
3068 static void dispc_mgr_enable_stallmode(struct dispc_device *dispc, in dispc_mgr_enable_stallmode() argument
3071 mgr_fld_write(dispc, channel, DISPC_MGR_FLD_STALLMODE, enable); in dispc_mgr_enable_stallmode()
3074 static void dispc_mgr_set_lcd_config(struct dispc_device *dispc, in dispc_mgr_set_lcd_config() argument
3078 dispc_mgr_set_io_pad_mode(dispc, config->io_pad_mode); in dispc_mgr_set_lcd_config()
3080 dispc_mgr_enable_stallmode(dispc, channel, config->stallmode); in dispc_mgr_set_lcd_config()
3081 dispc_mgr_enable_fifohandcheck(dispc, channel, config->fifohandcheck); in dispc_mgr_set_lcd_config()
3083 dispc_mgr_set_clock_div(dispc, channel, &config->clock_info); in dispc_mgr_set_lcd_config()
3085 dispc_mgr_set_tft_data_lines(dispc, channel, config->video_port_width); in dispc_mgr_set_lcd_config()
3087 dispc_lcd_enable_signal_polarity(dispc, config->lcden_sig_polarity); in dispc_mgr_set_lcd_config()
3089 dispc_mgr_set_lcd_type_tft(dispc, channel); in dispc_mgr_set_lcd_config()
3092 static bool _dispc_mgr_size_ok(struct dispc_device *dispc, in _dispc_mgr_size_ok() argument
3095 return width <= dispc->feat->mgr_width_max && in _dispc_mgr_size_ok()
3096 height <= dispc->feat->mgr_height_max; in _dispc_mgr_size_ok()
3099 static bool _dispc_lcd_timings_ok(struct dispc_device *dispc, in _dispc_lcd_timings_ok() argument
3103 if (hsync_len < 1 || hsync_len > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3104 hfp < 1 || hfp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3105 hbp < 1 || hbp > dispc->feat->hp_max || in _dispc_lcd_timings_ok()
3106 vsw < 1 || vsw > dispc->feat->sw_max || in _dispc_lcd_timings_ok()
3107 vfp < 0 || vfp > dispc->feat->vp_max || in _dispc_lcd_timings_ok()
3108 vbp < 0 || vbp > dispc->feat->vp_max) in _dispc_lcd_timings_ok()
3113 static bool _dispc_mgr_pclk_ok(struct dispc_device *dispc, in _dispc_mgr_pclk_ok() argument
3118 return pclk <= dispc->feat->max_lcd_pclk; in _dispc_mgr_pclk_ok()
3120 return pclk <= dispc->feat->max_tv_pclk; in _dispc_mgr_pclk_ok()
3123 bool dispc_mgr_timings_ok(struct dispc_device *dispc, enum omap_channel channel, in dispc_mgr_timings_ok() argument
3126 if (!_dispc_mgr_size_ok(dispc, vm->hactive, vm->vactive)) in dispc_mgr_timings_ok()
3129 if (!_dispc_mgr_pclk_ok(dispc, channel, vm->pixelclock)) in dispc_mgr_timings_ok()
3137 if (!_dispc_lcd_timings_ok(dispc, vm->hsync_len, in dispc_mgr_timings_ok()
3147 static void _dispc_mgr_set_lcd_timings(struct dispc_device *dispc, in _dispc_mgr_set_lcd_timings() argument
3154 timing_h = FLD_VAL(vm->hsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3155 FLD_VAL(vm->hfront_porch - 1, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3156 FLD_VAL(vm->hback_porch - 1, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3157 timing_v = FLD_VAL(vm->vsync_len - 1, dispc->feat->sw_start, 0) | in _dispc_mgr_set_lcd_timings()
3158 FLD_VAL(vm->vfront_porch, dispc->feat->fp_start, 8) | in _dispc_mgr_set_lcd_timings()
3159 FLD_VAL(vm->vback_porch, dispc->feat->bp_start, 20); in _dispc_mgr_set_lcd_timings()
3161 dispc_write_reg(dispc, DISPC_TIMING_H(channel), timing_h); in _dispc_mgr_set_lcd_timings()
3162 dispc_write_reg(dispc, DISPC_TIMING_V(channel), timing_v); in _dispc_mgr_set_lcd_timings()
3200 if (dispc->feat->supports_sync_align) in _dispc_mgr_set_lcd_timings()
3203 dispc_write_reg(dispc, DISPC_POL_FREQ(channel), l); in _dispc_mgr_set_lcd_timings()
3205 if (dispc->syscon_pol) { in _dispc_mgr_set_lcd_timings()
3220 regmap_update_bits(dispc->syscon_pol, dispc->syscon_pol_offset, in _dispc_mgr_set_lcd_timings()
3236 static void dispc_mgr_set_timings(struct dispc_device *dispc, in dispc_mgr_set_timings() argument
3246 if (!dispc_mgr_timings_ok(dispc, channel, &t)) { in dispc_mgr_set_timings()
3252 _dispc_mgr_set_lcd_timings(dispc, channel, &t); in dispc_mgr_set_timings()
3276 if (dispc->feat->supports_double_pixel) in dispc_mgr_set_timings()
3277 REG_FLD_MOD(dispc, DISPC_CONTROL, in dispc_mgr_set_timings()
3282 dispc_mgr_set_size(dispc, channel, t.hactive, t.vactive); in dispc_mgr_set_timings()
3285 static void dispc_mgr_set_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_set_lcd_divisor() argument
3292 dispc_write_reg(dispc, DISPC_DIVISORo(channel), in dispc_mgr_set_lcd_divisor()
3295 if (!dispc_has_feature(dispc, FEAT_CORE_CLK_DIV) && in dispc_mgr_set_lcd_divisor()
3297 dispc->core_clk_rate = dispc_fclk_rate(dispc) / lck_div; in dispc_mgr_set_lcd_divisor()
3300 static void dispc_mgr_get_lcd_divisor(struct dispc_device *dispc, in dispc_mgr_get_lcd_divisor() argument
3305 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_get_lcd_divisor()
3310 static unsigned long dispc_fclk_rate(struct dispc_device *dispc) in dispc_fclk_rate() argument
3315 src = dss_get_dispc_clk_source(dispc->dss); in dispc_fclk_rate()
3318 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_fclk_rate()
3323 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_fclk_rate()
3332 static unsigned long dispc_mgr_lclk_rate(struct dispc_device *dispc, in dispc_mgr_lclk_rate() argument
3341 return dispc_fclk_rate(dispc); in dispc_mgr_lclk_rate()
3343 src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_mgr_lclk_rate()
3346 r = dss_get_dispc_clk_rate(dispc->dss); in dispc_mgr_lclk_rate()
3351 pll = dss_pll_find_by_src(dispc->dss, src); in dispc_mgr_lclk_rate()
3357 lcd = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_lclk_rate()
3362 static unsigned long dispc_mgr_pclk_rate(struct dispc_device *dispc, in dispc_mgr_pclk_rate() argument
3371 l = dispc_read_reg(dispc, DISPC_DIVISORo(channel)); in dispc_mgr_pclk_rate()
3375 r = dispc_mgr_lclk_rate(dispc, channel); in dispc_mgr_pclk_rate()
3379 return dispc->tv_pclk_rate; in dispc_mgr_pclk_rate()
3383 void dispc_set_tv_pclk(struct dispc_device *dispc, unsigned long pclk) in dispc_set_tv_pclk() argument
3385 dispc->tv_pclk_rate = pclk; in dispc_set_tv_pclk()
3388 static unsigned long dispc_core_clk_rate(struct dispc_device *dispc) in dispc_core_clk_rate() argument
3390 return dispc->core_clk_rate; in dispc_core_clk_rate()
3393 static unsigned long dispc_plane_pclk_rate(struct dispc_device *dispc, in dispc_plane_pclk_rate() argument
3401 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_pclk_rate()
3403 return dispc_mgr_pclk_rate(dispc, channel); in dispc_plane_pclk_rate()
3406 static unsigned long dispc_plane_lclk_rate(struct dispc_device *dispc, in dispc_plane_lclk_rate() argument
3414 channel = dispc_ovl_get_channel_out(dispc, plane); in dispc_plane_lclk_rate()
3416 return dispc_mgr_lclk_rate(dispc, channel); in dispc_plane_lclk_rate()
3419 static void dispc_dump_clocks_channel(struct dispc_device *dispc, in dispc_dump_clocks_channel() argument
3428 lcd_clk_src = dss_get_lcd_clk_source(dispc->dss, channel); in dispc_dump_clocks_channel()
3433 dispc_mgr_get_lcd_divisor(dispc, channel, &lcd, &pcd); in dispc_dump_clocks_channel()
3436 dispc_mgr_lclk_rate(dispc, channel), lcd); in dispc_dump_clocks_channel()
3438 dispc_mgr_pclk_rate(dispc, channel), pcd); in dispc_dump_clocks_channel()
3441 void dispc_dump_clocks(struct dispc_device *dispc, struct seq_file *s) in dispc_dump_clocks() argument
3447 if (dispc_runtime_get(dispc)) in dispc_dump_clocks()
3450 seq_printf(s, "- DISPC -\n"); in dispc_dump_clocks()
3452 dispc_clk_src = dss_get_dispc_clk_source(dispc->dss); in dispc_dump_clocks()
3453 seq_printf(s, "dispc fclk source = %s\n", in dispc_dump_clocks()
3456 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate(dispc)); in dispc_dump_clocks()
3458 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in dispc_dump_clocks()
3459 seq_printf(s, "- DISPC-CORE-CLK -\n"); in dispc_dump_clocks()
3460 l = dispc_read_reg(dispc, DISPC_DIVISOR); in dispc_dump_clocks()
3464 (dispc_fclk_rate(dispc)/lcd), lcd); in dispc_dump_clocks()
3467 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD); in dispc_dump_clocks()
3469 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_dump_clocks()
3470 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD2); in dispc_dump_clocks()
3471 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_dump_clocks()
3472 dispc_dump_clocks_channel(dispc, s, OMAP_DSS_CHANNEL_LCD3); in dispc_dump_clocks()
3474 dispc_runtime_put(dispc); in dispc_dump_clocks()
3479 struct dispc_device *dispc = s->private; in dispc_dump_regs() local
3496 #define DUMPREG(dispc, r) \ in dispc_dump_regs() argument
3497 seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(dispc, r)) in dispc_dump_regs()
3499 if (dispc_runtime_get(dispc)) in dispc_dump_regs()
3502 /* DISPC common registers */ in dispc_dump_regs()
3503 DUMPREG(dispc, DISPC_REVISION); in dispc_dump_regs()
3504 DUMPREG(dispc, DISPC_SYSCONFIG); in dispc_dump_regs()
3505 DUMPREG(dispc, DISPC_SYSSTATUS); in dispc_dump_regs()
3506 DUMPREG(dispc, DISPC_IRQSTATUS); in dispc_dump_regs()
3507 DUMPREG(dispc, DISPC_IRQENABLE); in dispc_dump_regs()
3508 DUMPREG(dispc, DISPC_CONTROL); in dispc_dump_regs()
3509 DUMPREG(dispc, DISPC_CONFIG); in dispc_dump_regs()
3510 DUMPREG(dispc, DISPC_CAPABLE); in dispc_dump_regs()
3511 DUMPREG(dispc, DISPC_LINE_STATUS); in dispc_dump_regs()
3512 DUMPREG(dispc, DISPC_LINE_NUMBER); in dispc_dump_regs()
3513 if (dispc_has_feature(dispc, FEAT_ALPHA_FIXED_ZORDER) || in dispc_dump_regs()
3514 dispc_has_feature(dispc, FEAT_ALPHA_FREE_ZORDER)) in dispc_dump_regs()
3515 DUMPREG(dispc, DISPC_GLOBAL_ALPHA); in dispc_dump_regs()
3516 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) { in dispc_dump_regs()
3517 DUMPREG(dispc, DISPC_CONTROL2); in dispc_dump_regs()
3518 DUMPREG(dispc, DISPC_CONFIG2); in dispc_dump_regs()
3520 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) { in dispc_dump_regs()
3521 DUMPREG(dispc, DISPC_CONTROL3); in dispc_dump_regs()
3522 DUMPREG(dispc, DISPC_CONFIG3); in dispc_dump_regs()
3524 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3525 DUMPREG(dispc, DISPC_GLOBAL_MFLAG_ATTRIBUTE); in dispc_dump_regs()
3530 #define DUMPREG(dispc, i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \ in dispc_dump_regs() argument
3532 dispc_read_reg(dispc, DISPC_REG(i, r))) in dispc_dump_regs()
3536 /* DISPC channel specific registers */ in dispc_dump_regs()
3537 for (i = 0; i < dispc_get_num_mgrs(dispc); i++) { in dispc_dump_regs()
3538 DUMPREG(dispc, i, DISPC_DEFAULT_COLOR); in dispc_dump_regs()
3539 DUMPREG(dispc, i, DISPC_TRANS_COLOR); in dispc_dump_regs()
3540 DUMPREG(dispc, i, DISPC_SIZE_MGR); in dispc_dump_regs()
3545 DUMPREG(dispc, i, DISPC_TIMING_H); in dispc_dump_regs()
3546 DUMPREG(dispc, i, DISPC_TIMING_V); in dispc_dump_regs()
3547 DUMPREG(dispc, i, DISPC_POL_FREQ); in dispc_dump_regs()
3548 DUMPREG(dispc, i, DISPC_DIVISORo); in dispc_dump_regs()
3550 DUMPREG(dispc, i, DISPC_DATA_CYCLE1); in dispc_dump_regs()
3551 DUMPREG(dispc, i, DISPC_DATA_CYCLE2); in dispc_dump_regs()
3552 DUMPREG(dispc, i, DISPC_DATA_CYCLE3); in dispc_dump_regs()
3554 if (dispc_has_feature(dispc, FEAT_CPR)) { in dispc_dump_regs()
3555 DUMPREG(dispc, i, DISPC_CPR_COEF_R); in dispc_dump_regs()
3556 DUMPREG(dispc, i, DISPC_CPR_COEF_G); in dispc_dump_regs()
3557 DUMPREG(dispc, i, DISPC_CPR_COEF_B); in dispc_dump_regs()
3563 for (i = 0; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3564 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3565 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3566 DUMPREG(dispc, i, DISPC_OVL_POSITION); in dispc_dump_regs()
3567 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3568 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3569 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3570 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3571 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3572 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3574 if (dispc_has_feature(dispc, FEAT_PRELOAD)) in dispc_dump_regs()
3575 DUMPREG(dispc, i, DISPC_OVL_PRELOAD); in dispc_dump_regs()
3576 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3577 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3580 DUMPREG(dispc, i, DISPC_OVL_WINDOW_SKIP); in dispc_dump_regs()
3581 DUMPREG(dispc, i, DISPC_OVL_TABLE_BA); in dispc_dump_regs()
3585 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3586 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3587 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3588 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3589 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3590 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3591 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3592 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3593 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3594 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3596 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3597 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3600 if (dispc->feat->has_writeback) { in dispc_dump_regs()
3602 DUMPREG(dispc, i, DISPC_OVL_BA0); in dispc_dump_regs()
3603 DUMPREG(dispc, i, DISPC_OVL_BA1); in dispc_dump_regs()
3604 DUMPREG(dispc, i, DISPC_OVL_SIZE); in dispc_dump_regs()
3605 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES); in dispc_dump_regs()
3606 DUMPREG(dispc, i, DISPC_OVL_FIFO_THRESHOLD); in dispc_dump_regs()
3607 DUMPREG(dispc, i, DISPC_OVL_FIFO_SIZE_STATUS); in dispc_dump_regs()
3608 DUMPREG(dispc, i, DISPC_OVL_ROW_INC); in dispc_dump_regs()
3609 DUMPREG(dispc, i, DISPC_OVL_PIXEL_INC); in dispc_dump_regs()
3611 if (dispc_has_feature(dispc, FEAT_MFLAG)) in dispc_dump_regs()
3612 DUMPREG(dispc, i, DISPC_OVL_MFLAG_THRESHOLD); in dispc_dump_regs()
3614 DUMPREG(dispc, i, DISPC_OVL_FIR); in dispc_dump_regs()
3615 DUMPREG(dispc, i, DISPC_OVL_PICTURE_SIZE); in dispc_dump_regs()
3616 DUMPREG(dispc, i, DISPC_OVL_ACCU0); in dispc_dump_regs()
3617 DUMPREG(dispc, i, DISPC_OVL_ACCU1); in dispc_dump_regs()
3618 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3619 DUMPREG(dispc, i, DISPC_OVL_BA0_UV); in dispc_dump_regs()
3620 DUMPREG(dispc, i, DISPC_OVL_BA1_UV); in dispc_dump_regs()
3621 DUMPREG(dispc, i, DISPC_OVL_FIR2); in dispc_dump_regs()
3622 DUMPREG(dispc, i, DISPC_OVL_ACCU2_0); in dispc_dump_regs()
3623 DUMPREG(dispc, i, DISPC_OVL_ACCU2_1); in dispc_dump_regs()
3625 if (dispc_has_feature(dispc, FEAT_ATTR2)) in dispc_dump_regs()
3626 DUMPREG(dispc, i, DISPC_OVL_ATTRIBUTES2); in dispc_dump_regs()
3633 #define DUMPREG(dispc, plane, name, i) \ in dispc_dump_regs() argument
3636 dispc_read_reg(dispc, DISPC_REG(plane, name, i))) in dispc_dump_regs()
3641 for (i = 1; i < dispc_get_num_ovls(dispc); i++) { in dispc_dump_regs()
3643 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H, j); in dispc_dump_regs()
3646 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV, j); in dispc_dump_regs()
3649 DUMPREG(dispc, i, DISPC_OVL_CONV_COEF, j); in dispc_dump_regs()
3651 if (dispc_has_feature(dispc, FEAT_FIR_COEF_V)) { in dispc_dump_regs()
3653 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V, j); in dispc_dump_regs()
3656 if (dispc_has_feature(dispc, FEAT_HANDLE_UV_SEPARATE)) { in dispc_dump_regs()
3658 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_H2, j); in dispc_dump_regs()
3661 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_HV2, j); in dispc_dump_regs()
3664 DUMPREG(dispc, i, DISPC_OVL_FIR_COEF_V2, j); in dispc_dump_regs()
3668 dispc_runtime_put(dispc); in dispc_dump_regs()
3677 int dispc_calc_clock_rates(struct dispc_device *dispc, in dispc_calc_clock_rates() argument
3692 bool dispc_div_calc(struct dispc_device *dispc, unsigned long dispc_freq, in dispc_div_calc() argument
3710 pckd_hw_min = dispc->feat->min_pcd; in dispc_div_calc()
3713 lck_max = dss_get_max_fck_rate(dispc->dss); in dispc_div_calc()
3731 * For OMAP2/3 the DISPC fclk is the same as LCD's logic in dispc_div_calc()
3732 * clock, which means we're configuring DISPC fclk here in dispc_div_calc()
3734 * OMAP4+ the DISPC fclk is a separate clock. in dispc_div_calc()
3736 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) in dispc_div_calc()
3737 fck = dispc_core_clk_rate(dispc); in dispc_div_calc()
3752 void dispc_mgr_set_clock_div(struct dispc_device *dispc, in dispc_mgr_set_clock_div() argument
3759 dispc_mgr_set_lcd_divisor(dispc, channel, cinfo->lck_div, in dispc_mgr_set_clock_div()
3763 int dispc_mgr_get_clock_div(struct dispc_device *dispc, in dispc_mgr_get_clock_div() argument
3769 fck = dispc_fclk_rate(dispc); in dispc_mgr_get_clock_div()
3771 cinfo->lck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 23, 16); in dispc_mgr_get_clock_div()
3772 cinfo->pck_div = REG_GET(dispc, DISPC_DIVISORo(channel), 7, 0); in dispc_mgr_get_clock_div()
3780 static u32 dispc_read_irqstatus(struct dispc_device *dispc) in dispc_read_irqstatus() argument
3782 return dispc_read_reg(dispc, DISPC_IRQSTATUS); in dispc_read_irqstatus()
3785 static void dispc_clear_irqstatus(struct dispc_device *dispc, u32 mask) in dispc_clear_irqstatus() argument
3787 dispc_write_reg(dispc, DISPC_IRQSTATUS, mask); in dispc_clear_irqstatus()
3790 static void dispc_write_irqenable(struct dispc_device *dispc, u32 mask) in dispc_write_irqenable() argument
3792 u32 old_mask = dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3795 dispc_clear_irqstatus(dispc, (mask ^ old_mask) & mask); in dispc_write_irqenable()
3797 dispc_write_reg(dispc, DISPC_IRQENABLE, mask); in dispc_write_irqenable()
3800 dispc_read_reg(dispc, DISPC_IRQENABLE); in dispc_write_irqenable()
3803 void dispc_enable_sidle(struct dispc_device *dispc) in dispc_enable_sidle() argument
3806 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 2, 4, 3); in dispc_enable_sidle()
3809 void dispc_disable_sidle(struct dispc_device *dispc) in dispc_disable_sidle() argument
3811 REG_FLD_MOD(dispc, DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */ in dispc_disable_sidle()
3814 static u32 dispc_mgr_gamma_size(struct dispc_device *dispc, in dispc_mgr_gamma_size() argument
3819 if (!dispc->feat->has_gamma_table) in dispc_mgr_gamma_size()
3825 static void dispc_mgr_write_gamma_table(struct dispc_device *dispc, in dispc_mgr_write_gamma_table() argument
3829 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_write_gamma_table()
3842 dispc_write_reg(dispc, gdesc->reg, v); in dispc_mgr_write_gamma_table()
3846 static void dispc_restore_gamma_tables(struct dispc_device *dispc) in dispc_restore_gamma_tables() argument
3850 if (!dispc->feat->has_gamma_table) in dispc_restore_gamma_tables()
3853 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD); in dispc_restore_gamma_tables()
3855 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_DIGIT); in dispc_restore_gamma_tables()
3857 if (dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_restore_gamma_tables()
3858 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD2); in dispc_restore_gamma_tables()
3860 if (dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_restore_gamma_tables()
3861 dispc_mgr_write_gamma_table(dispc, OMAP_DSS_CHANNEL_LCD3); in dispc_restore_gamma_tables()
3869 static void dispc_mgr_set_gamma(struct dispc_device *dispc, in dispc_mgr_set_gamma() argument
3875 u32 *table = dispc->gamma_table[channel]; in dispc_mgr_set_gamma()
3881 if (!dispc->feat->has_gamma_table) in dispc_mgr_set_gamma()
3913 if (dispc->is_enabled) in dispc_mgr_set_gamma()
3914 dispc_mgr_write_gamma_table(dispc, channel); in dispc_mgr_set_gamma()
3917 static int dispc_init_gamma_tables(struct dispc_device *dispc) in dispc_init_gamma_tables() argument
3921 if (!dispc->feat->has_gamma_table) in dispc_init_gamma_tables()
3924 for (channel = 0; channel < ARRAY_SIZE(dispc->gamma_table); channel++) { in dispc_init_gamma_tables()
3929 !dispc_has_feature(dispc, FEAT_MGR_LCD2)) in dispc_init_gamma_tables()
3933 !dispc_has_feature(dispc, FEAT_MGR_LCD3)) in dispc_init_gamma_tables()
3936 gt = devm_kmalloc_array(&dispc->pdev->dev, gdesc->len, in dispc_init_gamma_tables()
3941 dispc->gamma_table[channel] = gt; in dispc_init_gamma_tables()
3943 dispc_mgr_set_gamma(dispc, channel, NULL, 0); in dispc_init_gamma_tables()
3948 static void _omap_dispc_initial_config(struct dispc_device *dispc) in _omap_dispc_initial_config() argument
3953 if (dispc_has_feature(dispc, FEAT_CORE_CLK_DIV)) { in _omap_dispc_initial_config()
3954 l = dispc_read_reg(dispc, DISPC_DIVISOR); in _omap_dispc_initial_config()
3958 dispc_write_reg(dispc, DISPC_DIVISOR, l); in _omap_dispc_initial_config()
3960 dispc->core_clk_rate = dispc_fclk_rate(dispc); in _omap_dispc_initial_config()
3964 if (dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3965 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 3, 3); in _omap_dispc_initial_config()
3969 * (dispc->feat->has_gamma_table) this enables tv-out gamma tables. in _omap_dispc_initial_config()
3971 if (dispc_has_feature(dispc, FEAT_FUNCGATED) || in _omap_dispc_initial_config()
3972 dispc->feat->has_gamma_table) in _omap_dispc_initial_config()
3973 REG_FLD_MOD(dispc, DISPC_CONFIG, 1, 9, 9); in _omap_dispc_initial_config()
3975 dispc_setup_color_conv_coef(dispc); in _omap_dispc_initial_config()
3977 dispc_set_loadmode(dispc, OMAP_DSS_LOAD_FRAME_ONLY); in _omap_dispc_initial_config()
3979 dispc_init_fifos(dispc); in _omap_dispc_initial_config()
3981 dispc_configure_burst_sizes(dispc); in _omap_dispc_initial_config()
3983 dispc_ovl_enable_zorder_planes(dispc); in _omap_dispc_initial_config()
3985 if (dispc->feat->mstandby_workaround) in _omap_dispc_initial_config()
3986 REG_FLD_MOD(dispc, DISPC_MSTANDBY_CTRL, 1, 0, 0); in _omap_dispc_initial_config()
3988 if (dispc_has_feature(dispc, FEAT_MFLAG)) in _omap_dispc_initial_config()
3989 dispc_init_mflag(dispc); in _omap_dispc_initial_config()
4268 * Assume the line width buffer to be 768 pixels as OMAP2 DISPC scaler
4508 struct dispc_device *dispc = arg; in dispc_irq_handler() local
4510 if (!dispc->is_enabled) in dispc_irq_handler()
4513 return dispc->user_handler(irq, dispc->user_data); in dispc_irq_handler()
4516 static int dispc_request_irq(struct dispc_device *dispc, irq_handler_t handler, in dispc_request_irq() argument
4521 if (dispc->user_handler != NULL) in dispc_request_irq()
4524 dispc->user_handler = handler; in dispc_request_irq()
4525 dispc->user_data = dev_id; in dispc_request_irq()
4530 r = devm_request_irq(&dispc->pdev->dev, dispc->irq, dispc_irq_handler, in dispc_request_irq()
4531 IRQF_SHARED, "OMAP DISPC", dispc); in dispc_request_irq()
4533 dispc->user_handler = NULL; in dispc_request_irq()
4534 dispc->user_data = NULL; in dispc_request_irq()
4540 static void dispc_free_irq(struct dispc_device *dispc, void *dev_id) in dispc_free_irq() argument
4542 devm_free_irq(&dispc->pdev->dev, dispc->irq, dispc); in dispc_free_irq()
4544 dispc->user_handler = NULL; in dispc_free_irq()
4545 dispc->user_data = NULL; in dispc_free_irq()
4548 static u32 dispc_get_memory_bandwidth_limit(struct dispc_device *dispc) in dispc_get_memory_bandwidth_limit() argument
4553 of_property_read_u32(dispc->pdev->dev.of_node, "max-memory-bandwidth", in dispc_get_memory_bandwidth_limit()
4560 * Workaround for errata i734 in DSS dispc
4630 static int dispc_errata_i734_wa_init(struct dispc_device *dispc) in dispc_errata_i734_wa_init() argument
4632 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_init()
4638 i734_buf.vaddr = dma_alloc_writecombine(&dispc->pdev->dev, in dispc_errata_i734_wa_init()
4642 dev_err(&dispc->pdev->dev, "%s: dma_alloc_writecombine failed\n", in dispc_errata_i734_wa_init()
4650 static void dispc_errata_i734_wa_fini(struct dispc_device *dispc) in dispc_errata_i734_wa_fini() argument
4652 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa_fini()
4655 dma_free_writecombine(&dispc->pdev->dev, i734_buf.size, i734_buf.vaddr, in dispc_errata_i734_wa_fini()
4659 static void dispc_errata_i734_wa(struct dispc_device *dispc) in dispc_errata_i734_wa() argument
4661 u32 framedone_irq = dispc_mgr_get_framedone_irq(dispc, in dispc_errata_i734_wa()
4668 if (!dispc->feat->has_gamma_i734_bug) in dispc_errata_i734_wa()
4671 gatestate = REG_GET(dispc, DISPC_CONFIG, 8, 4); in dispc_errata_i734_wa()
4678 REG_FLD_MOD(dispc, DISPC_CONFIG, 0x1f, 8, 4); in dispc_errata_i734_wa()
4681 dispc_ovl_setup(dispc, OMAP_DSS_GFX, &ovli, &i734.vm, false, in dispc_errata_i734_wa()
4683 dispc_ovl_enable(dispc, OMAP_DSS_GFX, true); in dispc_errata_i734_wa()
4686 dispc_mgr_setup(dispc, OMAP_DSS_CHANNEL_LCD, &i734.mgri); in dispc_errata_i734_wa()
4687 dispc_calc_clock_rates(dispc, dss_get_dispc_clk_rate(dispc->dss), in dispc_errata_i734_wa()
4689 dispc_mgr_set_lcd_config(dispc, OMAP_DSS_CHANNEL_LCD, &lcd_conf); in dispc_errata_i734_wa()
4690 dispc_mgr_set_timings(dispc, OMAP_DSS_CHANNEL_LCD, &i734.vm); in dispc_errata_i734_wa()
4692 dispc_clear_irqstatus(dispc, framedone_irq); in dispc_errata_i734_wa()
4695 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, true); in dispc_errata_i734_wa()
4696 dispc_mgr_enable(dispc, OMAP_DSS_CHANNEL_LCD, false); in dispc_errata_i734_wa()
4703 while (!(dispc_read_irqstatus(dispc) & framedone_irq)) { in dispc_errata_i734_wa()
4705 dev_err(&dispc->pdev->dev, "%s: framedone timeout\n", in dispc_errata_i734_wa()
4710 dispc_ovl_enable(dispc, OMAP_DSS_GFX, false); in dispc_errata_i734_wa()
4713 dispc_clear_irqstatus(dispc, 0xffffffff); in dispc_errata_i734_wa()
4716 REG_FLD_MOD(dispc, DISPC_CONFIG, gatestate, 8, 4); in dispc_errata_i734_wa()
4760 /* DISPC HW IP initialisation */
4762 { .compatible = "ti,omap2-dispc", .data = &omap24xx_dispc_feats },
4763 { .compatible = "ti,omap3-dispc", .data = &omap36xx_dispc_feats },
4764 { .compatible = "ti,omap4-dispc", .data = &omap44xx_dispc_feats },
4765 { .compatible = "ti,omap5-dispc", .data = &omap54xx_dispc_feats },
4766 { .compatible = "ti,dra7-dispc", .data = &omap54xx_dispc_feats },
4784 struct dispc_device *dispc; in dispc_bind() local
4790 dispc = kzalloc(sizeof(*dispc), GFP_KERNEL); in dispc_bind()
4791 if (!dispc) in dispc_bind()
4794 dispc->pdev = pdev; in dispc_bind()
4795 platform_set_drvdata(pdev, dispc); in dispc_bind()
4796 dispc->dss = dss; in dispc_bind()
4798 spin_lock_init(&dispc->control_lock); in dispc_bind()
4806 dispc->feat = soc->data; in dispc_bind()
4808 dispc->feat = of_match_device(dispc_of_match, &pdev->dev)->data; in dispc_bind()
4810 r = dispc_errata_i734_wa_init(dispc); in dispc_bind()
4814 dispc_mem = platform_get_resource(dispc->pdev, IORESOURCE_MEM, 0); in dispc_bind()
4815 dispc->base = devm_ioremap_resource(&pdev->dev, dispc_mem); in dispc_bind()
4816 if (IS_ERR(dispc->base)) { in dispc_bind()
4817 r = PTR_ERR(dispc->base); in dispc_bind()
4821 dispc->irq = platform_get_irq(dispc->pdev, 0); in dispc_bind()
4822 if (dispc->irq < 0) { in dispc_bind()
4829 dispc->syscon_pol = syscon_regmap_lookup_by_phandle(np, "syscon-pol"); in dispc_bind()
4830 if (IS_ERR(dispc->syscon_pol)) { in dispc_bind()
4832 r = PTR_ERR(dispc->syscon_pol); in dispc_bind()
4837 &dispc->syscon_pol_offset)) { in dispc_bind()
4844 r = dispc_init_gamma_tables(dispc); in dispc_bind()
4850 r = dispc_runtime_get(dispc); in dispc_bind()
4854 _omap_dispc_initial_config(dispc); in dispc_bind()
4856 rev = dispc_read_reg(dispc, DISPC_REVISION); in dispc_bind()
4857 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n", in dispc_bind()
4860 dispc_runtime_put(dispc); in dispc_bind()
4862 dss->dispc = dispc; in dispc_bind()
4865 dispc->debugfs = dss_debugfs_create_file(dss, "dispc", dispc_dump_regs, in dispc_bind()
4866 dispc); in dispc_bind()
4873 kfree(dispc); in dispc_bind()
4879 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_unbind() local
4880 struct dss_device *dss = dispc->dss; in dispc_unbind()
4882 dss_debugfs_remove_file(dispc->debugfs); in dispc_unbind()
4884 dss->dispc = NULL; in dispc_unbind()
4889 dispc_errata_i734_wa_fini(dispc); in dispc_unbind()
4891 kfree(dispc); in dispc_unbind()
4912 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_suspend() local
4914 dispc->is_enabled = false; in dispc_runtime_suspend()
4917 /* wait for current handler to finish before turning the DISPC off */ in dispc_runtime_suspend()
4918 synchronize_irq(dispc->irq); in dispc_runtime_suspend()
4920 dispc_save_context(dispc); in dispc_runtime_suspend()
4927 struct dispc_device *dispc = dev_get_drvdata(dev); in dispc_runtime_resume() local
4935 if (REG_GET(dispc, DISPC_CONFIG, 2, 1) != OMAP_DSS_LOAD_FRAME_ONLY) { in dispc_runtime_resume()
4936 _omap_dispc_initial_config(dispc); in dispc_runtime_resume()
4938 dispc_errata_i734_wa(dispc); in dispc_runtime_resume()
4940 dispc_restore_context(dispc); in dispc_runtime_resume()
4942 dispc_restore_gamma_tables(dispc); in dispc_runtime_resume()
4945 dispc->is_enabled = true; in dispc_runtime_resume()