Lines Matching full:pi
196 struct ci_power_info *pi = rdev->pm.dpm.priv; in ci_get_pi() local
198 return pi; in ci_get_pi()
210 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_powertune_defaults() local
220 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
226 pi->powertune_defaults = &defaults_saturn_xt; in ci_initialize_powertune_defaults()
230 pi->powertune_defaults = &defaults_hawaii_xt; in ci_initialize_powertune_defaults()
234 pi->powertune_defaults = &defaults_hawaii_pro; in ci_initialize_powertune_defaults()
244 pi->powertune_defaults = &defaults_bonaire_xt; in ci_initialize_powertune_defaults()
248 pi->dte_tj_offset = 0; in ci_initialize_powertune_defaults()
250 pi->caps_power_containment = true; in ci_initialize_powertune_defaults()
251 pi->caps_cac = false; in ci_initialize_powertune_defaults()
252 pi->caps_sq_ramping = false; in ci_initialize_powertune_defaults()
253 pi->caps_db_ramping = false; in ci_initialize_powertune_defaults()
254 pi->caps_td_ramping = false; in ci_initialize_powertune_defaults()
255 pi->caps_tcp_ramping = false; in ci_initialize_powertune_defaults()
257 if (pi->caps_power_containment) { in ci_initialize_powertune_defaults()
258 pi->caps_cac = true; in ci_initialize_powertune_defaults()
260 pi->enable_bapm_feature = false; in ci_initialize_powertune_defaults()
262 pi->enable_bapm_feature = true; in ci_initialize_powertune_defaults()
263 pi->enable_tdc_limit_feature = true; in ci_initialize_powertune_defaults()
264 pi->enable_pkg_pwr_tracking_feature = true; in ci_initialize_powertune_defaults()
275 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_vid_sidd() local
276 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_populate_bapm_vddc_vid_sidd()
277 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_populate_bapm_vddc_vid_sidd()
278 u8 *hi2_vid = pi->smc_powertune_table.BapmVddCVidHiSidd2; in ci_populate_bapm_vddc_vid_sidd()
304 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_vddc_vid() local
305 u8 *vid = pi->smc_powertune_table.VddCVid; in ci_populate_vddc_vid()
308 if (pi->vddc_voltage_table.count > 8) in ci_populate_vddc_vid()
311 for (i = 0; i < pi->vddc_voltage_table.count; i++) in ci_populate_vddc_vid()
312 vid[i] = ci_convert_to_vid(pi->vddc_voltage_table.entries[i].value); in ci_populate_vddc_vid()
319 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_svi_load_line() local
320 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_svi_load_line()
322 pi->smc_powertune_table.SviLoadLineEn = pt_defaults->svi_load_line_en; in ci_populate_svi_load_line()
323 pi->smc_powertune_table.SviLoadLineVddC = pt_defaults->svi_load_line_vddc; in ci_populate_svi_load_line()
324 pi->smc_powertune_table.SviLoadLineTrimVddC = 3; in ci_populate_svi_load_line()
325 pi->smc_powertune_table.SviLoadLineOffsetVddC = 0; in ci_populate_svi_load_line()
332 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_tdc_limit() local
333 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_tdc_limit()
337 pi->smc_powertune_table.TDC_VDDC_PkgLimit = cpu_to_be16(tdc_limit); in ci_populate_tdc_limit()
338 pi->smc_powertune_table.TDC_VDDC_ThrottleReleaseLimitPerc = in ci_populate_tdc_limit()
340 pi->smc_powertune_table.TDC_MAWt = pt_defaults->tdc_mawt; in ci_populate_tdc_limit()
347 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_dw8() local
348 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_dw8()
355 (u32 *)&pi->smc_powertune_table.TdcWaterfallCtl, in ci_populate_dw8()
356 pi->sram_end); in ci_populate_dw8()
360 pi->smc_powertune_table.TdcWaterfallCtl = pt_defaults->tdc_waterfall_ctl; in ci_populate_dw8()
367 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_fuzzy_fan() local
374 pi->smc_powertune_table.FuzzyFan_PwmSetDelta = in ci_populate_fuzzy_fan()
382 struct ci_power_info *pi = ci_get_pi(rdev); in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc() local
383 u8 *hi_vid = pi->smc_powertune_table.BapmVddCVidHiSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
384 u8 *lo_vid = pi->smc_powertune_table.BapmVddCVidLoSidd; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
406 pi->smc_powertune_table.GnbLPMLMaxVid = (u8)max; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
407 pi->smc_powertune_table.GnbLPMLMinVid = (u8)min; in ci_min_max_v_gnbl_pm_lid_from_bapm_vddc()
414 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_vddc_base_leakage_sidd() local
415 u16 hi_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
416 u16 lo_sidd = pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd; in ci_populate_bapm_vddc_base_leakage_sidd()
423 pi->smc_powertune_table.BapmVddCBaseLeakageHiSidd = cpu_to_be16(hi_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
424 pi->smc_powertune_table.BapmVddCBaseLeakageLoSidd = cpu_to_be16(lo_sidd); in ci_populate_bapm_vddc_base_leakage_sidd()
431 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_bapm_parameters_in_dpm_table() local
432 const struct ci_pt_defaults *pt_defaults = pi->powertune_defaults; in ci_populate_bapm_parameters_in_dpm_table()
433 SMU7_Discrete_DpmTable *dpm_table = &pi->smc_state_table; in ci_populate_bapm_parameters_in_dpm_table()
444 dpm_table->DTETjOffset = (u8)pi->dte_tj_offset; in ci_populate_bapm_parameters_in_dpm_table()
446 (u8)(pi->thermal_temp_setting.temperature_high / 1000); in ci_populate_bapm_parameters_in_dpm_table()
479 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_pm_base() local
483 if (pi->caps_power_containment) { in ci_populate_pm_base()
487 &pm_fuse_table_offset, pi->sram_end); in ci_populate_pm_base()
515 (u8 *)&pi->smc_powertune_table, in ci_populate_pm_base()
516 sizeof(SMU7_Discrete_PmFuses), pi->sram_end); in ci_populate_pm_base()
526 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_enable_didt() local
529 if (pi->caps_sq_ramping) { in ci_do_enable_didt()
538 if (pi->caps_db_ramping) { in ci_do_enable_didt()
547 if (pi->caps_td_ramping) { in ci_do_enable_didt()
556 if (pi->caps_tcp_ramping) { in ci_do_enable_didt()
616 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_didt() local
619 if (pi->caps_sq_ramping || pi->caps_db_ramping || in ci_enable_didt()
620 pi->caps_td_ramping || pi->caps_tcp_ramping) { in ci_enable_didt()
641 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_power_containment() local
646 pi->power_containment_features = 0; in ci_enable_power_containment()
647 if (pi->caps_power_containment) { in ci_enable_power_containment()
648 if (pi->enable_bapm_feature) { in ci_enable_power_containment()
653 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_BAPM; in ci_enable_power_containment()
656 if (pi->enable_tdc_limit_feature) { in ci_enable_power_containment()
661 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_TDCLimit; in ci_enable_power_containment()
664 if (pi->enable_pkg_pwr_tracking_feature) { in ci_enable_power_containment()
674 pi->power_containment_features |= POWERCONTAINMENT_FEATURE_PkgPwrLimit; in ci_enable_power_containment()
681 if (pi->caps_power_containment && pi->power_containment_features) { in ci_enable_power_containment()
682 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_TDCLimit) in ci_enable_power_containment()
685 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_BAPM) in ci_enable_power_containment()
688 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) in ci_enable_power_containment()
690 pi->power_containment_features = 0; in ci_enable_power_containment()
699 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_smc_cac() local
703 if (pi->caps_cac) { in ci_enable_smc_cac()
708 pi->cac_enabled = false; in ci_enable_smc_cac()
710 pi->cac_enabled = true; in ci_enable_smc_cac()
712 } else if (pi->cac_enabled) { in ci_enable_smc_cac()
714 pi->cac_enabled = false; in ci_enable_smc_cac()
724 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_thermal_based_sclk_dpm() local
727 if (pi->thermal_sclk_dpm_enabled) { in ci_enable_thermal_based_sclk_dpm()
742 struct ci_power_info *pi = ci_get_pi(rdev); in ci_power_control_set_level() local
750 if (pi->caps_power_containment) { in ci_power_control_set_level()
764 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_powergate_uvd() local
766 if (pi->uvd_power_gated == gate) in ci_dpm_powergate_uvd()
769 pi->uvd_power_gated = gate; in ci_dpm_powergate_uvd()
776 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_vblank_too_short() local
778 u32 switch_limit = pi->mem_gddr5 ? 450 : 300; in ci_dpm_vblank_too_short()
797 struct ci_power_info *pi = ci_get_pi(rdev); in ci_apply_state_adjust_rules() local
818 pi->battery_state = true; in ci_apply_state_adjust_rules()
820 pi->battery_state = false; in ci_apply_state_adjust_rules()
935 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_static_mode() local
938 if (pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_static_mode()
940 pi->fan_ctrl_default_mode = tmp; in ci_fan_ctrl_set_static_mode()
942 pi->t_min = tmp; in ci_fan_ctrl_set_static_mode()
943 pi->fan_ctrl_is_in_default_mode = false; in ci_fan_ctrl_set_static_mode()
957 struct ci_power_info *pi = ci_get_pi(rdev); in ci_thermal_setup_fan_table() local
966 if (!pi->fan_table_start) { in ci_thermal_setup_fan_table()
1019 pi->fan_table_start, in ci_thermal_setup_fan_table()
1022 pi->sram_end); in ci_thermal_setup_fan_table()
1034 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_start_smc_fan_control() local
1037 if (pi->caps_od_fuzzy_fan_control_support) { in ci_fan_ctrl_start_smc_fan_control()
1056 pi->fan_is_controlled_by_smc = true; in ci_fan_ctrl_start_smc_fan_control()
1063 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_stop_smc_fan_control() local
1067 pi->fan_is_controlled_by_smc = false; in ci_fan_ctrl_stop_smc_fan_control()
1104 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_fan_speed_percent() local
1109 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_set_fan_speed_percent()
1149 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_get_mode() local
1152 if (pi->fan_is_controlled_by_smc) in ci_fan_ctrl_get_mode()
1213 struct ci_power_info *pi = ci_get_pi(rdev); in ci_fan_ctrl_set_default_mode() local
1216 if (!pi->fan_ctrl_is_in_default_mode) { in ci_fan_ctrl_set_default_mode()
1218 tmp |= FDO_PWM_MODE(pi->fan_ctrl_default_mode); in ci_fan_ctrl_set_default_mode()
1222 tmp |= TMIN(pi->t_min); in ci_fan_ctrl_set_default_mode()
1224 pi->fan_ctrl_is_in_default_mode = true; in ci_fan_ctrl_set_default_mode()
1282 struct ci_power_info *pi = ci_get_pi(rdev);
1285 pi->soft_regs_start + reg_offset,
1286 value, pi->sram_end);
1293 struct ci_power_info *pi = ci_get_pi(rdev); in ci_write_smc_soft_register() local
1296 pi->soft_regs_start + reg_offset, in ci_write_smc_soft_register()
1297 value, pi->sram_end); in ci_write_smc_soft_register()
1302 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_fps_limits() local
1303 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_fps_limits()
1305 if (pi->caps_fps) { in ci_init_fps_limits()
1318 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_sclk_t() local
1322 if (pi->caps_sclk_throttle_low_notification) { in ci_update_sclk_t()
1323 low_sclk_interrupt_t = cpu_to_be32(pi->low_sclk_interrupt_t); in ci_update_sclk_t()
1326 pi->dpm_table_start + in ci_update_sclk_t()
1329 sizeof(u32), pi->sram_end); in ci_update_sclk_t()
1338 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_leakage_voltages() local
1343 pi->vddc_leakage.count = 0; in ci_get_leakage_voltages()
1344 pi->vddci_leakage.count = 0; in ci_get_leakage_voltages()
1352 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1353 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1354 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1364 pi->vddc_leakage.actual_voltage[pi->vddc_leakage.count] = vddc; in ci_get_leakage_voltages()
1365 pi->vddc_leakage.leakage_id[pi->vddc_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1366 pi->vddc_leakage.count++; in ci_get_leakage_voltages()
1369 pi->vddci_leakage.actual_voltage[pi->vddci_leakage.count] = vddci; in ci_get_leakage_voltages()
1370 pi->vddci_leakage.leakage_id[pi->vddci_leakage.count] = virtual_voltage_id; in ci_get_leakage_voltages()
1371 pi->vddci_leakage.count++; in ci_get_leakage_voltages()
1380 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_dpm_event_sources() local
1415 if (pi->thermal_protection) in ci_set_dpm_event_sources()
1431 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_auto_throttle_source() local
1434 if (!(pi->active_auto_throttle_sources & (1 << source))) { in ci_enable_auto_throttle_source()
1435 pi->active_auto_throttle_sources |= 1 << source; in ci_enable_auto_throttle_source()
1436 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1439 if (pi->active_auto_throttle_sources & (1 << source)) { in ci_enable_auto_throttle_source()
1440 pi->active_auto_throttle_sources &= ~(1 << source); in ci_enable_auto_throttle_source()
1441 ci_set_dpm_event_sources(rdev, pi->active_auto_throttle_sources); in ci_enable_auto_throttle_source()
1454 struct ci_power_info *pi = ci_get_pi(rdev); in ci_unfreeze_sclk_mclk_dpm() local
1457 if (!pi->need_update_smu7_dpm_table) in ci_unfreeze_sclk_mclk_dpm()
1460 if ((!pi->sclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1461 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_unfreeze_sclk_mclk_dpm()
1467 if ((!pi->mclk_dpm_key_disabled) && in ci_unfreeze_sclk_mclk_dpm()
1468 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_unfreeze_sclk_mclk_dpm()
1474 pi->need_update_smu7_dpm_table = 0; in ci_unfreeze_sclk_mclk_dpm()
1480 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_sclk_mclk_dpm() local
1484 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1490 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1508 if (!pi->sclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1514 if (!pi->mclk_dpm_key_disabled) { in ci_enable_sclk_mclk_dpm()
1526 struct ci_power_info *pi = ci_get_pi(rdev); in ci_start_dpm() local
1551 if (!pi->pcie_dpm_key_disabled) { in ci_start_dpm()
1562 struct ci_power_info *pi = ci_get_pi(rdev); in ci_freeze_sclk_mclk_dpm() local
1565 if (!pi->need_update_smu7_dpm_table) in ci_freeze_sclk_mclk_dpm()
1568 if ((!pi->sclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1569 (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK))) { in ci_freeze_sclk_mclk_dpm()
1575 if ((!pi->mclk_dpm_key_disabled) && in ci_freeze_sclk_mclk_dpm()
1576 (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) { in ci_freeze_sclk_mclk_dpm()
1587 struct ci_power_info *pi = ci_get_pi(rdev); in ci_stop_dpm() local
1600 if (!pi->pcie_dpm_key_disabled) { in ci_stop_dpm()
1632 struct ci_power_info *pi = ci_get_pi(rdev);
1644 if (pi->caps_automatic_dc_transition) {
1698 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_sclk() local
1700 if (!pi->sclk_dpm_key_disabled) { in ci_dpm_force_state_sclk()
1712 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_mclk() local
1714 if (!pi->mclk_dpm_key_disabled) { in ci_dpm_force_state_mclk()
1726 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_state_pcie() local
1728 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_state_pcie()
1740 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_power_limit() local
1742 if (pi->power_containment_features & POWERCONTAINMENT_FEATURE_PkgPwrLimit) { in ci_set_power_limit()
1816 struct ci_power_info *pi = ci_get_pi(rdev); in ci_process_firmware_header() local
1823 &tmp, pi->sram_end); in ci_process_firmware_header()
1827 pi->dpm_table_start = tmp; in ci_process_firmware_header()
1832 &tmp, pi->sram_end); in ci_process_firmware_header()
1836 pi->soft_regs_start = tmp; in ci_process_firmware_header()
1841 &tmp, pi->sram_end); in ci_process_firmware_header()
1845 pi->mc_reg_table_start = tmp; in ci_process_firmware_header()
1850 &tmp, pi->sram_end); in ci_process_firmware_header()
1854 pi->fan_table_start = tmp; in ci_process_firmware_header()
1859 &tmp, pi->sram_end); in ci_process_firmware_header()
1863 pi->arb_table_start = tmp; in ci_process_firmware_header()
1870 struct ci_power_info *pi = ci_get_pi(rdev); in ci_read_clock_registers() local
1872 pi->clock_registers.cg_spll_func_cntl = in ci_read_clock_registers()
1874 pi->clock_registers.cg_spll_func_cntl_2 = in ci_read_clock_registers()
1876 pi->clock_registers.cg_spll_func_cntl_3 = in ci_read_clock_registers()
1878 pi->clock_registers.cg_spll_func_cntl_4 = in ci_read_clock_registers()
1880 pi->clock_registers.cg_spll_spread_spectrum = in ci_read_clock_registers()
1882 pi->clock_registers.cg_spll_spread_spectrum_2 = in ci_read_clock_registers()
1884 pi->clock_registers.dll_cntl = RREG32(DLL_CNTL); in ci_read_clock_registers()
1885 pi->clock_registers.mclk_pwrmgt_cntl = RREG32(MCLK_PWRMGT_CNTL); in ci_read_clock_registers()
1886 pi->clock_registers.mpll_ad_func_cntl = RREG32(MPLL_AD_FUNC_CNTL); in ci_read_clock_registers()
1887 pi->clock_registers.mpll_dq_func_cntl = RREG32(MPLL_DQ_FUNC_CNTL); in ci_read_clock_registers()
1888 pi->clock_registers.mpll_func_cntl = RREG32(MPLL_FUNC_CNTL); in ci_read_clock_registers()
1889 pi->clock_registers.mpll_func_cntl_1 = RREG32(MPLL_FUNC_CNTL_1); in ci_read_clock_registers()
1890 pi->clock_registers.mpll_func_cntl_2 = RREG32(MPLL_FUNC_CNTL_2); in ci_read_clock_registers()
1891 pi->clock_registers.mpll_ss1 = RREG32(MPLL_SS1); in ci_read_clock_registers()
1892 pi->clock_registers.mpll_ss2 = RREG32(MPLL_SS2); in ci_read_clock_registers()
1897 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_sclk_t() local
1899 pi->low_sclk_interrupt_t = 0; in ci_init_sclk_t()
1963 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ds_master_switch() local
1966 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
1974 if (pi->caps_sclk_ds) { in ci_enable_ds_master_switch()
2019 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_spread_spectrum() local
2023 if (pi->caps_sclk_ss_support) { in ci_enable_spread_spectrum()
2093 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_firmware() local
2105 ret = ci_load_smc_ucode(rdev, pi->sram_end); in ci_upload_firmware()
2134 struct ci_power_info *pi = ci_get_pi(rdev); in ci_construct_voltage_tables() local
2137 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2140 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2143 } else if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2146 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2151 if (pi->vddc_voltage_table.count > SMU7_MAX_LEVELS_VDDC) in ci_construct_voltage_tables()
2153 &pi->vddc_voltage_table); in ci_construct_voltage_tables()
2155 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2158 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2161 } else if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2164 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2169 if (pi->vddci_voltage_table.count > SMU7_MAX_LEVELS_VDDCI) in ci_construct_voltage_tables()
2171 &pi->vddci_voltage_table); in ci_construct_voltage_tables()
2173 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) { in ci_construct_voltage_tables()
2176 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2179 } else if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_construct_voltage_tables()
2182 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2187 if (pi->mvdd_voltage_table.count > SMU7_MAX_LEVELS_MVDD) in ci_construct_voltage_tables()
2189 &pi->mvdd_voltage_table); in ci_construct_voltage_tables()
2219 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddc_table() local
2222 table->VddcLevelCount = pi->vddc_voltage_table.count; in ci_populate_smc_vddc_table()
2225 &pi->vddc_voltage_table.entries[count], in ci_populate_smc_vddc_table()
2228 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddc_table()
2230 pi->vddc_voltage_table.entries[count].smio_low; in ci_populate_smc_vddc_table()
2243 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_vddci_table() local
2245 table->VddciLevelCount = pi->vddci_voltage_table.count; in ci_populate_smc_vddci_table()
2248 &pi->vddci_voltage_table.entries[count], in ci_populate_smc_vddci_table()
2251 if (pi->vddci_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_vddci_table()
2253 pi->vddci_voltage_table.entries[count].smio_low; in ci_populate_smc_vddci_table()
2265 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_mvdd_table() local
2268 table->MvddLevelCount = pi->mvdd_voltage_table.count; in ci_populate_smc_mvdd_table()
2271 &pi->mvdd_voltage_table.entries[count], in ci_populate_smc_mvdd_table()
2274 if (pi->mvdd_control == CISLANDS_VOLTAGE_CONTROL_BY_GPIO) in ci_populate_smc_mvdd_table()
2276 pi->mvdd_voltage_table.entries[count].smio_low; in ci_populate_smc_mvdd_table()
2308 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mvdd_value() local
2311 if (pi->mvdd_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_mvdd_value()
2314 voltage->Voltage = pi->mvdd_voltage_table.entries[i].value; in ci_populate_mvdd_value()
2413 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_arb_table_index() local
2417 ret = ci_read_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2418 &tmp, pi->sram_end); in ci_init_arb_table_index()
2425 return ci_write_smc_sram_dword(rdev, pi->arb_table_start, in ci_init_arb_table_index()
2426 tmp, pi->sram_end); in ci_init_arb_table_index()
2546 struct ci_power_info *pi = ci_get_pi(rdev); in ci_do_program_memory_timing_parameters() local
2553 for (i = 0; i < pi->dpm_table.sclk_table.count; i++) { in ci_do_program_memory_timing_parameters()
2554 for (j = 0; j < pi->dpm_table.mclk_table.count; j++) { in ci_do_program_memory_timing_parameters()
2556 pi->dpm_table.sclk_table.dpm_levels[i].value, in ci_do_program_memory_timing_parameters()
2557 pi->dpm_table.mclk_table.dpm_levels[j].value, in ci_do_program_memory_timing_parameters()
2566 pi->arb_table_start, in ci_do_program_memory_timing_parameters()
2569 pi->sram_end); in ci_do_program_memory_timing_parameters()
2576 struct ci_power_info *pi = ci_get_pi(rdev); in ci_program_memory_timing_parameters() local
2578 if (pi->need_update_smu7_dpm_table == 0) in ci_program_memory_timing_parameters()
2588 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_initial_state() local
2594 pi->smc_state_table.GraphicsBootLevel = level; in ci_populate_smc_initial_state()
2602 pi->smc_state_table.MemoryBootLevel = level; in ci_populate_smc_initial_state()
2627 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_link_level() local
2628 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_smc_link_level()
2641 pi->smc_state_table.LinkLevelCount = (u8)dpm_table->pcie_speed_table.count; in ci_populate_smc_link_level()
2642 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_populate_smc_link_level()
2792 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_mclk_params() local
2793 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_calculate_mclk_params()
2794 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_calculate_mclk_params()
2795 u32 mpll_ad_func_cntl = pi->clock_registers.mpll_ad_func_cntl; in ci_calculate_mclk_params()
2796 u32 mpll_dq_func_cntl = pi->clock_registers.mpll_dq_func_cntl; in ci_calculate_mclk_params()
2797 u32 mpll_func_cntl = pi->clock_registers.mpll_func_cntl; in ci_calculate_mclk_params()
2798 u32 mpll_func_cntl_1 = pi->clock_registers.mpll_func_cntl_1; in ci_calculate_mclk_params()
2799 u32 mpll_func_cntl_2 = pi->clock_registers.mpll_func_cntl_2; in ci_calculate_mclk_params()
2800 u32 mpll_ss1 = pi->clock_registers.mpll_ss1; in ci_calculate_mclk_params()
2801 u32 mpll_ss2 = pi->clock_registers.mpll_ss2; in ci_calculate_mclk_params()
2819 if (pi->mem_gddr5) { in ci_calculate_mclk_params()
2825 if (pi->caps_mclk_ss_support) { in ci_calculate_mclk_params()
2877 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_memory_level() local
2907 if (pi->vddc_phase_shed_control) in ci_populate_single_memory_level()
2917 memory_level->ActivityLevel = (u16)pi->mclk_activity_target; in ci_populate_single_memory_level()
2927 if (pi->mclk_stutter_mode_threshold && in ci_populate_single_memory_level()
2928 (memory_clock <= pi->mclk_stutter_mode_threshold) && in ci_populate_single_memory_level()
2929 (pi->uvd_enabled == false) && in ci_populate_single_memory_level()
2934 if (pi->mclk_strobe_mode_threshold && in ci_populate_single_memory_level()
2935 (memory_clock <= pi->mclk_strobe_mode_threshold)) in ci_populate_single_memory_level()
2938 if (pi->mem_gddr5) { in ci_populate_single_memory_level()
2941 if (pi->mclk_edc_enable_threshold && in ci_populate_single_memory_level()
2942 (memory_clock > pi->mclk_edc_enable_threshold)) in ci_populate_single_memory_level()
2945 if (pi->mclk_edc_wr_enable_threshold && in ci_populate_single_memory_level()
2946 (memory_clock > pi->mclk_edc_wr_enable_threshold)) in ci_populate_single_memory_level()
2956 dll_state_on = pi->dll_default_on; in ci_populate_single_memory_level()
2990 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_smc_acpi_level() local
2993 u32 spll_func_cntl = pi->clock_registers.cg_spll_func_cntl; in ci_populate_smc_acpi_level()
2994 u32 spll_func_cntl_2 = pi->clock_registers.cg_spll_func_cntl_2; in ci_populate_smc_acpi_level()
2995 u32 dll_cntl = pi->clock_registers.dll_cntl; in ci_populate_smc_acpi_level()
2996 u32 mclk_pwrmgt_cntl = pi->clock_registers.mclk_pwrmgt_cntl; in ci_populate_smc_acpi_level()
3001 if (pi->acpi_vddc) in ci_populate_smc_acpi_level()
3002 table->ACPILevel.MinVddc = cpu_to_be32(pi->acpi_vddc * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3004 table->ACPILevel.MinVddc = cpu_to_be32(pi->min_vddc_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3006 table->ACPILevel.MinVddcPhases = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_smc_acpi_level()
3028 table->ACPILevel.CgSpllFuncCntl3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_populate_smc_acpi_level()
3029 table->ACPILevel.CgSpllFuncCntl4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_populate_smc_acpi_level()
3030 table->ACPILevel.SpllSpreadSpectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_populate_smc_acpi_level()
3031 table->ACPILevel.SpllSpreadSpectrum2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_populate_smc_acpi_level()
3050 if (pi->vddci_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_populate_smc_acpi_level()
3051 if (pi->acpi_vddci) in ci_populate_smc_acpi_level()
3053 cpu_to_be32(pi->acpi_vddci * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3056 cpu_to_be32(pi->min_vddci_in_pp_table * VOLTAGE_SCALE); in ci_populate_smc_acpi_level()
3073 cpu_to_be32(pi->clock_registers.mpll_ad_func_cntl); in ci_populate_smc_acpi_level()
3075 cpu_to_be32(pi->clock_registers.mpll_dq_func_cntl); in ci_populate_smc_acpi_level()
3077 cpu_to_be32(pi->clock_registers.mpll_func_cntl); in ci_populate_smc_acpi_level()
3079 cpu_to_be32(pi->clock_registers.mpll_func_cntl_1); in ci_populate_smc_acpi_level()
3081 cpu_to_be32(pi->clock_registers.mpll_func_cntl_2); in ci_populate_smc_acpi_level()
3082 table->MemoryACPILevel.MpllSs1 = cpu_to_be32(pi->clock_registers.mpll_ss1); in ci_populate_smc_acpi_level()
3083 table->MemoryACPILevel.MpllSs2 = cpu_to_be32(pi->clock_registers.mpll_ss2); in ci_populate_smc_acpi_level()
3091 cpu_to_be16((u16)pi->mclk_activity_target); in ci_populate_smc_acpi_level()
3105 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_ulv() local
3106 struct ci_ulv_parm *ulv = &pi->ulv; in ci_enable_ulv()
3123 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_ulv_level() local
3130 pi->ulv.supported = false; in ci_populate_ulv_level()
3134 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_BY_SVID2) { in ci_populate_ulv_level()
3148 state->VddcPhase = pi->vddc_phase_shed_control ? 0 : 1; in ci_populate_ulv_level()
3161 struct ci_power_info *pi = ci_get_pi(rdev); in ci_calculate_sclk_params() local
3163 u32 spll_func_cntl_3 = pi->clock_registers.cg_spll_func_cntl_3; in ci_calculate_sclk_params()
3164 u32 spll_func_cntl_4 = pi->clock_registers.cg_spll_func_cntl_4; in ci_calculate_sclk_params()
3165 u32 cg_spll_spread_spectrum = pi->clock_registers.cg_spll_spread_spectrum; in ci_calculate_sclk_params()
3166 u32 cg_spll_spread_spectrum_2 = pi->clock_registers.cg_spll_spread_spectrum_2; in ci_calculate_sclk_params()
3185 if (pi->caps_sclk_ss_support) { in ci_calculate_sclk_params()
3218 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_single_graphic_level() local
3236 if (pi->vddc_phase_shed_control) in ci_populate_single_graphic_level()
3252 if (pi->caps_sclk_ds) in ci_populate_single_graphic_level()
3276 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_graphic_levels() local
3277 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_graphic_levels()
3278 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_graphic_levels()
3282 SMU7_Discrete_GraphicsLevel *levels = pi->smc_state_table.GraphicsLevel; in ci_populate_all_graphic_levels()
3290 (u16)pi->activity_target[i], in ci_populate_all_graphic_levels()
3291 &pi->smc_state_table.GraphicsLevel[i]); in ci_populate_all_graphic_levels()
3295 pi->smc_state_table.GraphicsLevel[i].DeepSleepDivId = 0; in ci_populate_all_graphic_levels()
3297 pi->smc_state_table.GraphicsLevel[i].DisplayWatermark = in ci_populate_all_graphic_levels()
3300 pi->smc_state_table.GraphicsLevel[0].EnabledForActivity = 1; in ci_populate_all_graphic_levels()
3302 pi->smc_state_table.GraphicsDpmLevelCount = (u8)dpm_table->sclk_table.count; in ci_populate_all_graphic_levels()
3303 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_populate_all_graphic_levels()
3308 pi->sram_end); in ci_populate_all_graphic_levels()
3323 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_all_memory_levels() local
3324 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_all_memory_levels()
3325 u32 level_array_address = pi->dpm_table_start + in ci_populate_all_memory_levels()
3329 SMU7_Discrete_MemoryLevel *levels = pi->smc_state_table.MemoryLevel; in ci_populate_all_memory_levels()
3339 &pi->smc_state_table.MemoryLevel[i]); in ci_populate_all_memory_levels()
3344 pi->smc_state_table.MemoryLevel[0].EnabledForActivity = 1; in ci_populate_all_memory_levels()
3348 pi->smc_state_table.MemoryLevel[1].MinVddc = in ci_populate_all_memory_levels()
3349 pi->smc_state_table.MemoryLevel[0].MinVddc; in ci_populate_all_memory_levels()
3350 pi->smc_state_table.MemoryLevel[1].MinVddcPhases = in ci_populate_all_memory_levels()
3351 pi->smc_state_table.MemoryLevel[0].MinVddcPhases; in ci_populate_all_memory_levels()
3354 pi->smc_state_table.MemoryLevel[0].ActivityLevel = cpu_to_be16(0x1F); in ci_populate_all_memory_levels()
3356 pi->smc_state_table.MemoryDpmLevelCount = (u8)dpm_table->mclk_table.count; in ci_populate_all_memory_levels()
3357 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_populate_all_memory_levels()
3360 pi->smc_state_table.MemoryLevel[dpm_table->mclk_table.count - 1].DisplayWatermark = in ci_populate_all_memory_levels()
3365 pi->sram_end); in ci_populate_all_memory_levels()
3393 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_pcie_tables() local
3395 if (!pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) in ci_setup_default_pcie_tables()
3398 if (pi->use_pcie_performance_levels && !pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3399 pi->pcie_gen_powersaving = pi->pcie_gen_performance; in ci_setup_default_pcie_tables()
3400 pi->pcie_lane_powersaving = pi->pcie_lane_performance; in ci_setup_default_pcie_tables()
3401 } else if (!pi->use_pcie_performance_levels && pi->use_pcie_powersaving_levels) { in ci_setup_default_pcie_tables()
3402 pi->pcie_gen_performance = pi->pcie_gen_powersaving; in ci_setup_default_pcie_tables()
3403 pi->pcie_lane_performance = pi->pcie_lane_powersaving; in ci_setup_default_pcie_tables()
3407 &pi->dpm_table.pcie_speed_table, in ci_setup_default_pcie_tables()
3411 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3412 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3413 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3415 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 0, in ci_setup_default_pcie_tables()
3416 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3417 pi->pcie_lane_powersaving.min); in ci_setup_default_pcie_tables()
3418 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 1, in ci_setup_default_pcie_tables()
3419 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3420 pi->pcie_lane_performance.min); in ci_setup_default_pcie_tables()
3421 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 2, in ci_setup_default_pcie_tables()
3422 pi->pcie_gen_powersaving.min, in ci_setup_default_pcie_tables()
3423 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3424 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 3, in ci_setup_default_pcie_tables()
3425 pi->pcie_gen_performance.min, in ci_setup_default_pcie_tables()
3426 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3427 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 4, in ci_setup_default_pcie_tables()
3428 pi->pcie_gen_powersaving.max, in ci_setup_default_pcie_tables()
3429 pi->pcie_lane_powersaving.max); in ci_setup_default_pcie_tables()
3430 ci_setup_pcie_table_entry(&pi->dpm_table.pcie_speed_table, 5, in ci_setup_default_pcie_tables()
3431 pi->pcie_gen_performance.max, in ci_setup_default_pcie_tables()
3432 pi->pcie_lane_performance.max); in ci_setup_default_pcie_tables()
3434 pi->dpm_table.pcie_speed_table.count = 6; in ci_setup_default_pcie_tables()
3441 struct ci_power_info *pi = ci_get_pi(rdev); in ci_setup_default_dpm_tables() local
3459 memset(&pi->dpm_table, 0, sizeof(struct ci_dpm_table)); in ci_setup_default_dpm_tables()
3462 &pi->dpm_table.sclk_table, in ci_setup_default_dpm_tables()
3465 &pi->dpm_table.mclk_table, in ci_setup_default_dpm_tables()
3468 &pi->dpm_table.vddc_table, in ci_setup_default_dpm_tables()
3471 &pi->dpm_table.vddci_table, in ci_setup_default_dpm_tables()
3474 &pi->dpm_table.mvdd_table, in ci_setup_default_dpm_tables()
3477 pi->dpm_table.sclk_table.count = 0; in ci_setup_default_dpm_tables()
3480 (pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count-1].value != in ci_setup_default_dpm_tables()
3482 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].value = in ci_setup_default_dpm_tables()
3484 pi->dpm_table.sclk_table.dpm_levels[pi->dpm_table.sclk_table.count].enabled = in ci_setup_default_dpm_tables()
3486 pi->dpm_table.sclk_table.count++; in ci_setup_default_dpm_tables()
3490 pi->dpm_table.mclk_table.count = 0; in ci_setup_default_dpm_tables()
3493 (pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count-1].value != in ci_setup_default_dpm_tables()
3495 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].value = in ci_setup_default_dpm_tables()
3497 pi->dpm_table.mclk_table.dpm_levels[pi->dpm_table.mclk_table.count].enabled = in ci_setup_default_dpm_tables()
3499 pi->dpm_table.mclk_table.count++; in ci_setup_default_dpm_tables()
3504 pi->dpm_table.vddc_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3506 pi->dpm_table.vddc_table.dpm_levels[i].param1 = in ci_setup_default_dpm_tables()
3508 pi->dpm_table.vddc_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3510 pi->dpm_table.vddc_table.count = allowed_sclk_vddc_table->count; in ci_setup_default_dpm_tables()
3515 pi->dpm_table.vddci_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3517 pi->dpm_table.vddci_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3519 pi->dpm_table.vddci_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3525 pi->dpm_table.mvdd_table.dpm_levels[i].value = in ci_setup_default_dpm_tables()
3527 pi->dpm_table.mvdd_table.dpm_levels[i].enabled = true; in ci_setup_default_dpm_tables()
3529 pi->dpm_table.mvdd_table.count = allowed_mclk_table->count; in ci_setup_default_dpm_tables()
3555 struct ci_power_info *pi = ci_get_pi(rdev); in ci_init_smc_table() local
3556 struct ci_ulv_parm *ulv = &pi->ulv; in ci_init_smc_table()
3558 SMU7_Discrete_DpmTable *table = &pi->smc_state_table; in ci_init_smc_table()
3565 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) in ci_init_smc_table()
3576 if (pi->mem_gddr5) in ci_init_smc_table()
3580 ret = ci_populate_ulv_state(rdev, &pi->smc_state_table.Ulv); in ci_init_smc_table()
3627 ret = ci_find_boot_level(&pi->dpm_table.sclk_table, in ci_init_smc_table()
3628 pi->vbios_boot_state.sclk_bootup_value, in ci_init_smc_table()
3629 (u32 *)&pi->smc_state_table.GraphicsBootLevel); in ci_init_smc_table()
3631 ret = ci_find_boot_level(&pi->dpm_table.mclk_table, in ci_init_smc_table()
3632 pi->vbios_boot_state.mclk_bootup_value, in ci_init_smc_table()
3633 (u32 *)&pi->smc_state_table.MemoryBootLevel); in ci_init_smc_table()
3635 table->BootVddc = pi->vbios_boot_state.vddc_bootup_value; in ci_init_smc_table()
3636 table->BootVddci = pi->vbios_boot_state.vddci_bootup_value; in ci_init_smc_table()
3637 table->BootMVdd = pi->vbios_boot_state.mvdd_bootup_value; in ci_init_smc_table()
3654 table->TemperatureLimitHigh = (u16)((pi->thermal_temp_setting.temperature_high * in ci_init_smc_table()
3656 table->TemperatureLimitLow = (u16)((pi->thermal_temp_setting.temperature_low * in ci_init_smc_table()
3664 table->PCIeBootLinkLevel = pi->dpm_table.pcie_speed_table.count - 1; in ci_init_smc_table()
3666 if (pi->voltage_control == CISLANDS_VOLTAGE_CONTROL_BY_SVID2) in ci_init_smc_table()
3690 pi->dpm_table_start + in ci_init_smc_table()
3694 pi->sram_end); in ci_init_smc_table()
3720 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_pcie_dpm_states() local
3721 struct ci_single_dpm_table *pcie_table = &pi->dpm_table.pcie_speed_table; in ci_trim_pcie_dpm_states()
3751 struct ci_power_info *pi = ci_get_pi(rdev); in ci_trim_dpm_states() local
3763 &pi->dpm_table.sclk_table, in ci_trim_dpm_states()
3768 &pi->dpm_table.mclk_table, in ci_trim_dpm_states()
3815 struct ci_power_info *pi = ci_get_pi(rdev); in ci_upload_dpm_level_enable_mask() local
3820 if (!pi->sclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3821 if (pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3824 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3830 if (!pi->mclk_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3831 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3834 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3840 if (!pi->pcie_dpm_key_disabled) { in ci_upload_dpm_level_enable_mask()
3841 if (pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_upload_dpm_level_enable_mask()
3844 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_upload_dpm_level_enable_mask()
3856 struct ci_power_info *pi = ci_get_pi(rdev); in ci_find_dpm_states_clocks_in_dpm_table() local
3858 struct ci_single_dpm_table *sclk_table = &pi->dpm_table.sclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3860 struct ci_single_dpm_table *mclk_table = &pi->dpm_table.mclk_table; in ci_find_dpm_states_clocks_in_dpm_table()
3864 pi->need_update_smu7_dpm_table = 0; in ci_find_dpm_states_clocks_in_dpm_table()
3872 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3879 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_SCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3888 pi->need_update_smu7_dpm_table |= DPMTABLE_OD_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3892 pi->need_update_smu7_dpm_table |= DPMTABLE_UPDATE_MCLK; in ci_find_dpm_states_clocks_in_dpm_table()
3898 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_and_upload_sclk_mclk_dpm_levels() local
3902 struct ci_dpm_table *dpm_table = &pi->dpm_table; in ci_populate_and_upload_sclk_mclk_dpm_levels()
3905 if (!pi->need_update_smu7_dpm_table) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3908 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_SCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3911 if (pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK) in ci_populate_and_upload_sclk_mclk_dpm_levels()
3914 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_SCLK | DPMTABLE_UPDATE_SCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3920 if (pi->need_update_smu7_dpm_table & (DPMTABLE_OD_UPDATE_MCLK | DPMTABLE_UPDATE_MCLK)) { in ci_populate_and_upload_sclk_mclk_dpm_levels()
3931 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_uvd_dpm() local
3941 pi->dpm_level_enable_mask.uvd_dpm_enable_mask = 0; in ci_enable_uvd_dpm()
3945 pi->dpm_level_enable_mask.uvd_dpm_enable_mask |= 1 << i; in ci_enable_uvd_dpm()
3947 if (!pi->caps_uvd_dpm) in ci_enable_uvd_dpm()
3954 pi->dpm_level_enable_mask.uvd_dpm_enable_mask); in ci_enable_uvd_dpm()
3956 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3957 pi->uvd_enabled = true; in ci_enable_uvd_dpm()
3958 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_enable_uvd_dpm()
3961 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3964 if (pi->last_mclk_dpm_enable_mask & 0x1) { in ci_enable_uvd_dpm()
3965 pi->uvd_enabled = false; in ci_enable_uvd_dpm()
3966 pi->dpm_level_enable_mask.mclk_dpm_enable_mask |= 1; in ci_enable_uvd_dpm()
3969 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_enable_uvd_dpm()
3980 struct ci_power_info *pi = ci_get_pi(rdev); in ci_enable_vce_dpm() local
3990 pi->dpm_level_enable_mask.vce_dpm_enable_mask = 0; in ci_enable_vce_dpm()
3993 pi->dpm_level_enable_mask.vce_dpm_enable_mask |= 1 << i; in ci_enable_vce_dpm()
3995 if (!pi->caps_vce_dpm) in ci_enable_vce_dpm()
4002 pi->dpm_level_enable_mask.vce_dpm_enable_mask); in ci_enable_vce_dpm()
4013 struct ci_power_info *pi = ci_get_pi(rdev);
4023 pi->dpm_level_enable_mask.samu_dpm_enable_mask = 0;
4026 pi->dpm_level_enable_mask.samu_dpm_enable_mask |= 1 << i;
4028 if (!pi->caps_samu_dpm)
4035 pi->dpm_level_enable_mask.samu_dpm_enable_mask);
4044 struct ci_power_info *pi = ci_get_pi(rdev);
4054 pi->dpm_level_enable_mask.acp_dpm_enable_mask = 0;
4057 pi->dpm_level_enable_mask.acp_dpm_enable_mask |= 1 << i;
4059 if (!pi->caps_acp_dpm)
4066 pi->dpm_level_enable_mask.acp_dpm_enable_mask);
4077 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_uvd_dpm() local
4081 if (pi->caps_uvd_dpm || in ci_update_uvd_dpm()
4083 pi->smc_state_table.UvdBootLevel = 0; in ci_update_uvd_dpm()
4085 pi->smc_state_table.UvdBootLevel = in ci_update_uvd_dpm()
4090 tmp |= UvdBootLevel(pi->smc_state_table.UvdBootLevel); in ci_update_uvd_dpm()
4116 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_vce_dpm() local
4125 pi->smc_state_table.VceBootLevel = ci_get_vce_boot_level(rdev); in ci_update_vce_dpm()
4128 tmp |= VceBootLevel(pi->smc_state_table.VceBootLevel); in ci_update_vce_dpm()
4150 struct ci_power_info *pi = ci_get_pi(rdev);
4154 pi->smc_state_table.AcpBootLevel = 0;
4158 tmp |= AcpBootLevel(pi->smc_state_table.AcpBootLevel);
4169 struct ci_power_info *pi = ci_get_pi(rdev); in ci_generate_dpm_level_enable_mask() local
4176 pi->dpm_level_enable_mask.sclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4177 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.sclk_table); in ci_generate_dpm_level_enable_mask()
4178 pi->dpm_level_enable_mask.mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4179 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.mclk_table); in ci_generate_dpm_level_enable_mask()
4180 pi->last_mclk_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4181 pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_generate_dpm_level_enable_mask()
4182 if (pi->uvd_enabled) { in ci_generate_dpm_level_enable_mask()
4183 if (pi->dpm_level_enable_mask.mclk_dpm_enable_mask & 1) in ci_generate_dpm_level_enable_mask()
4184 pi->dpm_level_enable_mask.mclk_dpm_enable_mask &= 0xFFFFFFFE; in ci_generate_dpm_level_enable_mask()
4186 pi->dpm_level_enable_mask.pcie_dpm_enable_mask = in ci_generate_dpm_level_enable_mask()
4187 ci_get_dpm_level_enable_mask_value(&pi->dpm_table.pcie_speed_table); in ci_generate_dpm_level_enable_mask()
4207 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_force_performance_level() local
4212 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4213 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4215 tmp = pi->dpm_level_enable_mask.pcie_dpm_enable_mask; in ci_dpm_force_performance_level()
4231 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4232 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4234 tmp = pi->dpm_level_enable_mask.sclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4250 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4251 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4253 tmp = pi->dpm_level_enable_mask.mclk_dpm_enable_mask; in ci_dpm_force_performance_level()
4270 if ((!pi->sclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4271 pi->dpm_level_enable_mask.sclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4273 pi->dpm_level_enable_mask.sclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4285 if ((!pi->mclk_dpm_key_disabled) && in ci_dpm_force_performance_level()
4286 pi->dpm_level_enable_mask.mclk_dpm_enable_mask) { in ci_dpm_force_performance_level()
4288 pi->dpm_level_enable_mask.mclk_dpm_enable_mask); in ci_dpm_force_performance_level()
4300 if ((!pi->pcie_dpm_key_disabled) && in ci_dpm_force_performance_level()
4301 pi->dpm_level_enable_mask.pcie_dpm_enable_mask) { in ci_dpm_force_performance_level()
4303 pi->dpm_level_enable_mask.pcie_dpm_enable_mask); in ci_dpm_force_performance_level()
4316 if (!pi->pcie_dpm_key_disabled) { in ci_dpm_force_performance_level()
4337 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_mc_special_registers() local
4363 if (!pi->mem_gddr5) in ci_set_mc_special_registers()
4370 if (!pi->mem_gddr5) { in ci_set_mc_special_registers()
4624 struct ci_power_info *pi = ci_get_pi(rdev); in ci_initialize_mc_reg_table() local
4626 struct ci_mc_reg_table *ci_table = &pi->mc_reg_table; in ci_initialize_mc_reg_table()
4684 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_mc_reg_addresses() local
4687 for (i = 0, j = 0; j < pi->mc_reg_table.last; j++) { in ci_populate_mc_reg_addresses()
4688 if (pi->mc_reg_table.valid_flag & (1 << j)) { in ci_populate_mc_reg_addresses()
4691 mc_reg_table->address[i].s0 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s0); in ci_populate_mc_reg_addresses()
4692 mc_reg_table->address[i].s1 = cpu_to_be16(pi->mc_reg_table.mc_reg_address[j].s1); in ci_populate_mc_reg_addresses()
4720 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_entry_to_smc() local
4723 for(i = 0; i < pi->mc_reg_table.num_entries; i++) { in ci_convert_mc_reg_table_entry_to_smc()
4724 if (memory_clock <= pi->mc_reg_table.mc_reg_table_entry[i].mclk_max) in ci_convert_mc_reg_table_entry_to_smc()
4728 if ((i == pi->mc_reg_table.num_entries) && (i > 0)) in ci_convert_mc_reg_table_entry_to_smc()
4731 ci_convert_mc_registers(&pi->mc_reg_table.mc_reg_table_entry[i], in ci_convert_mc_reg_table_entry_to_smc()
4732 mc_reg_table_data, pi->mc_reg_table.last, in ci_convert_mc_reg_table_entry_to_smc()
4733 pi->mc_reg_table.valid_flag); in ci_convert_mc_reg_table_entry_to_smc()
4739 struct ci_power_info *pi = ci_get_pi(rdev); in ci_convert_mc_reg_table_to_smc() local
4742 for (i = 0; i < pi->dpm_table.mclk_table.count; i++) in ci_convert_mc_reg_table_to_smc()
4744 pi->dpm_table.mclk_table.dpm_levels[i].value, in ci_convert_mc_reg_table_to_smc()
4750 struct ci_power_info *pi = ci_get_pi(rdev); in ci_populate_initial_mc_reg_table() local
4753 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_populate_initial_mc_reg_table()
4755 ret = ci_populate_mc_reg_addresses(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4758 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_populate_initial_mc_reg_table()
4761 pi->mc_reg_table_start, in ci_populate_initial_mc_reg_table()
4762 (u8 *)&pi->smc_mc_reg_table, in ci_populate_initial_mc_reg_table()
4764 pi->sram_end); in ci_populate_initial_mc_reg_table()
4769 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_and_upload_mc_reg_table() local
4771 if (!(pi->need_update_smu7_dpm_table & DPMTABLE_OD_UPDATE_MCLK)) in ci_update_and_upload_mc_reg_table()
4774 memset(&pi->smc_mc_reg_table, 0, sizeof(SMU7_Discrete_MCRegisters)); in ci_update_and_upload_mc_reg_table()
4776 ci_convert_mc_reg_table_to_smc(rdev, &pi->smc_mc_reg_table); in ci_update_and_upload_mc_reg_table()
4779 pi->mc_reg_table_start + in ci_update_and_upload_mc_reg_table()
4781 (u8 *)&pi->smc_mc_reg_table.data[0], in ci_update_and_upload_mc_reg_table()
4783 pi->dpm_table.mclk_table.count, in ci_update_and_upload_mc_reg_table()
4784 pi->sram_end); in ci_update_and_upload_mc_reg_table()
4851 struct ci_power_info *pi = ci_get_pi(rdev); in ci_request_link_speed_change_before_state_change() local
4856 if (pi->force_pcie_gen == RADEON_PCIE_GEN_INVALID) in ci_request_link_speed_change_before_state_change()
4859 current_link_speed = pi->force_pcie_gen; in ci_request_link_speed_change_before_state_change()
4861 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_request_link_speed_change_before_state_change()
4862 pi->pspp_notify_required = false; in ci_request_link_speed_change_before_state_change()
4869 pi->force_pcie_gen = RADEON_PCIE_GEN2; in ci_request_link_speed_change_before_state_change()
4877 pi->force_pcie_gen = ci_get_current_pcie_speed(rdev); in ci_request_link_speed_change_before_state_change()
4882 pi->pspp_notify_required = true; in ci_request_link_speed_change_before_state_change()
4890 struct ci_power_info *pi = ci_get_pi(rdev); in ci_notify_link_speed_change_after_state_change() local
4895 if (pi->pspp_notify_required) { in ci_notify_link_speed_change_after_state_change()
4915 struct ci_power_info *pi = ci_get_pi(rdev); in ci_set_private_data_variables_based_on_pptable() local
4936 pi->min_vddc_in_pp_table = allowed_sclk_vddc_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4937 pi->max_vddc_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4940 pi->min_vddci_in_pp_table = allowed_mclk_vddci_table->entries[0].v; in ci_set_private_data_variables_based_on_pptable()
4941 pi->max_vddci_in_pp_table = in ci_set_private_data_variables_based_on_pptable()
4958 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddc_leakage() local
4959 struct ci_leakage_voltage *leakage_table = &pi->vddc_leakage; in ci_patch_with_vddc_leakage()
4972 struct ci_power_info *pi = ci_get_pi(rdev); in ci_patch_with_vddci_leakage() local
4973 struct ci_leakage_voltage *leakage_table = &pi->vddci_leakage; in ci_patch_with_vddci_leakage()
5091 struct ci_power_info *pi = ci_get_pi(rdev); in ci_get_memory_type() local
5098 pi->mem_gddr5 = true; in ci_get_memory_type()
5100 pi->mem_gddr5 = false; in ci_get_memory_type()
5108 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_current_ps() local
5110 pi->current_rps = *rps; in ci_update_current_ps()
5111 pi->current_ps = *new_ps; in ci_update_current_ps()
5112 pi->current_rps.ps_priv = &pi->current_ps; in ci_update_current_ps()
5119 struct ci_power_info *pi = ci_get_pi(rdev); in ci_update_requested_ps() local
5121 pi->requested_rps = *rps; in ci_update_requested_ps()
5122 pi->requested_ps = *new_ps; in ci_update_requested_ps()
5123 pi->requested_rps.ps_priv = &pi->requested_ps; in ci_update_requested_ps()
5128 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_pre_set_power_state() local
5134 ci_apply_state_adjust_rules(rdev, &pi->requested_rps); in ci_dpm_pre_set_power_state()
5141 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_post_set_power_state() local
5142 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_post_set_power_state()
5163 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_enable() local
5169 if (pi->voltage_control != CISLANDS_VOLTAGE_CONTROL_NONE) { in ci_dpm_enable()
5177 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5180 pi->caps_dynamic_ac_timing = false; in ci_dpm_enable()
5182 if (pi->dynamic_ss) in ci_dpm_enable()
5184 if (pi->thermal_protection) in ci_dpm_enable()
5214 if (pi->caps_dynamic_ac_timing) { in ci_dpm_enable()
5318 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_disable() local
5328 if (pi->thermal_protection) in ci_dpm_disable()
5349 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_set_power_state() local
5350 struct radeon_ps *new_ps = &pi->requested_rps; in ci_dpm_set_power_state()
5351 struct radeon_ps *old_ps = &pi->current_rps; in ci_dpm_set_power_state()
5355 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5384 if (pi->caps_dynamic_ac_timing) { in ci_dpm_set_power_state()
5406 if (pi->pcie_performance_request) in ci_dpm_set_power_state()
5474 struct ci_power_info *pi = ci_get_pi(rdev); in ci_parse_pplib_clock_info() local
5486 pi->sys_pcie_mask, in ci_parse_pplib_clock_info()
5487 pi->vbios_boot_state.pcie_gen_bootup_value, in ci_parse_pplib_clock_info()
5490 pi->vbios_boot_state.pcie_lane_bootup_value, in ci_parse_pplib_clock_info()
5494 pi->acpi_pcie_gen = pl->pcie_gen; in ci_parse_pplib_clock_info()
5498 pi->ulv.supported = true; in ci_parse_pplib_clock_info()
5499 pi->ulv.pl = *pl; in ci_parse_pplib_clock_info()
5500 pi->ulv.cg_ulv_parameter = CISLANDS_CGULVPARAMETER_DFLT; in ci_parse_pplib_clock_info()
5505 pl->mclk = pi->vbios_boot_state.mclk_bootup_value; in ci_parse_pplib_clock_info()
5506 pl->sclk = pi->vbios_boot_state.sclk_bootup_value; in ci_parse_pplib_clock_info()
5507 pl->pcie_gen = pi->vbios_boot_state.pcie_gen_bootup_value; in ci_parse_pplib_clock_info()
5508 pl->pcie_lane = pi->vbios_boot_state.pcie_lane_bootup_value; in ci_parse_pplib_clock_info()
5513 pi->use_pcie_powersaving_levels = true; in ci_parse_pplib_clock_info()
5514 if (pi->pcie_gen_powersaving.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5515 pi->pcie_gen_powersaving.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5516 if (pi->pcie_gen_powersaving.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5517 pi->pcie_gen_powersaving.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5518 if (pi->pcie_lane_powersaving.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5519 pi->pcie_lane_powersaving.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5520 if (pi->pcie_lane_powersaving.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5521 pi->pcie_lane_powersaving.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5524 pi->use_pcie_performance_levels = true; in ci_parse_pplib_clock_info()
5525 if (pi->pcie_gen_performance.max < pl->pcie_gen) in ci_parse_pplib_clock_info()
5526 pi->pcie_gen_performance.max = pl->pcie_gen; in ci_parse_pplib_clock_info()
5527 if (pi->pcie_gen_performance.min > pl->pcie_gen) in ci_parse_pplib_clock_info()
5528 pi->pcie_gen_performance.min = pl->pcie_gen; in ci_parse_pplib_clock_info()
5529 if (pi->pcie_lane_performance.max < pl->pcie_lane) in ci_parse_pplib_clock_info()
5530 pi->pcie_lane_performance.max = pl->pcie_lane; in ci_parse_pplib_clock_info()
5531 if (pi->pcie_lane_performance.min > pl->pcie_lane) in ci_parse_pplib_clock_info()
5532 pi->pcie_lane_performance.min = pl->pcie_lane; in ci_parse_pplib_clock_info()
5677 struct ci_power_info *pi; in ci_dpm_init() local
5682 pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); in ci_dpm_init()
5683 if (pi == NULL) in ci_dpm_init()
5685 rdev->pm.dpm.priv = pi; in ci_dpm_init()
5690 pi->sys_pcie_mask = 0; in ci_dpm_init()
5693 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5697 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | in ci_dpm_init()
5700 pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; in ci_dpm_init()
5702 pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; in ci_dpm_init()
5704 pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5705 pi->pcie_gen_performance.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5706 pi->pcie_gen_powersaving.max = RADEON_PCIE_GEN1; in ci_dpm_init()
5707 pi->pcie_gen_powersaving.min = RADEON_PCIE_GEN3; in ci_dpm_init()
5709 pi->pcie_lane_performance.max = 0; in ci_dpm_init()
5710 pi->pcie_lane_performance.min = 16; in ci_dpm_init()
5711 pi->pcie_lane_powersaving.max = 0; in ci_dpm_init()
5712 pi->pcie_lane_powersaving.min = 16; in ci_dpm_init()
5714 ret = ci_get_vbios_boot_values(rdev, &pi->vbios_boot_state); in ci_dpm_init()
5738 pi->dll_default_on = false; in ci_dpm_init()
5739 pi->sram_end = SMC_RAM_END; in ci_dpm_init()
5741 pi->activity_target[0] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5742 pi->activity_target[1] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5743 pi->activity_target[2] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5744 pi->activity_target[3] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5745 pi->activity_target[4] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5746 pi->activity_target[5] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5747 pi->activity_target[6] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5748 pi->activity_target[7] = CISLAND_TARGETACTIVITY_DFLT; in ci_dpm_init()
5750 pi->mclk_activity_target = CISLAND_MCLK_TARGETACTIVITY_DFLT; in ci_dpm_init()
5752 pi->sclk_dpm_key_disabled = 0; in ci_dpm_init()
5753 pi->mclk_dpm_key_disabled = 0; in ci_dpm_init()
5754 pi->pcie_dpm_key_disabled = 0; in ci_dpm_init()
5755 pi->thermal_sclk_dpm_enabled = 0; in ci_dpm_init()
5760 pi->mclk_dpm_key_disabled = 1; in ci_dpm_init()
5763 pi->caps_sclk_ds = true; in ci_dpm_init()
5765 pi->mclk_strobe_mode_threshold = 40000; in ci_dpm_init()
5766 pi->mclk_stutter_mode_threshold = 40000; in ci_dpm_init()
5767 pi->mclk_edc_enable_threshold = 40000; in ci_dpm_init()
5768 pi->mclk_edc_wr_enable_threshold = 40000; in ci_dpm_init()
5772 pi->caps_fps = false; in ci_dpm_init()
5774 pi->caps_sclk_throttle_low_notification = false; in ci_dpm_init()
5776 pi->caps_uvd_dpm = true; in ci_dpm_init()
5777 pi->caps_vce_dpm = true; in ci_dpm_init()
5811 pi->thermal_temp_setting.temperature_low = 94500; in ci_dpm_init()
5812 pi->thermal_temp_setting.temperature_high = 95000; in ci_dpm_init()
5813 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5815 pi->thermal_temp_setting.temperature_low = 99500; in ci_dpm_init()
5816 pi->thermal_temp_setting.temperature_high = 100000; in ci_dpm_init()
5817 pi->thermal_temp_setting.temperature_shutdown = 104000; in ci_dpm_init()
5820 pi->uvd_enabled = false; in ci_dpm_init()
5822 dpm_table = &pi->smc_state_table; in ci_dpm_init()
5871 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5872 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5873 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_NONE; in ci_dpm_init()
5875 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5877 pi->voltage_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5881 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5883 pi->vddci_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5890 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_GPIO; in ci_dpm_init()
5892 pi->mvdd_control = CISLANDS_VOLTAGE_CONTROL_BY_SVID2; in ci_dpm_init()
5897 pi->vddc_phase_shed_control = true; in ci_dpm_init()
5900 pi->pcie_performance_request = in ci_dpm_init()
5903 pi->pcie_performance_request = false; in ci_dpm_init()
5908 pi->caps_sclk_ss_support = true; in ci_dpm_init()
5909 pi->caps_mclk_ss_support = true; in ci_dpm_init()
5910 pi->dynamic_ss = true; in ci_dpm_init()
5912 pi->caps_sclk_ss_support = false; in ci_dpm_init()
5913 pi->caps_mclk_ss_support = false; in ci_dpm_init()
5914 pi->dynamic_ss = true; in ci_dpm_init()
5918 pi->thermal_protection = true; in ci_dpm_init()
5920 pi->thermal_protection = false; in ci_dpm_init()
5922 pi->caps_dynamic_ac_timing = true; in ci_dpm_init()
5924 pi->uvd_power_gated = false; in ci_dpm_init()
5932 pi->fan_ctrl_is_in_default_mode = true; in ci_dpm_init()
5940 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_debugfs_print_current_performance_level() local
5941 struct radeon_ps *rps = &pi->current_rps; in ci_dpm_debugfs_print_current_performance_level()
5945 seq_printf(m, "uvd %sabled\n", pi->uvd_enabled ? "en" : "dis"); in ci_dpm_debugfs_print_current_performance_level()
5985 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_sclk() local
5986 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_sclk()
5996 struct ci_power_info *pi = ci_get_pi(rdev); in ci_dpm_get_mclk() local
5997 struct ci_ps *requested_state = ci_get_ps(&pi->requested_rps); in ci_dpm_get_mclk()