Lines Matching full:dsi
31 #define DRIVER_NAME "dw-mipi-dsi"
378 static inline void dsi_write(struct dw_mipi_dsi *dsi, u32 reg, u32 val) in dsi_write() argument
380 writel(val, dsi->base + reg); in dsi_write()
383 static inline u32 dsi_read(struct dw_mipi_dsi *dsi, u32 reg) in dsi_read() argument
385 return readl(dsi->base + reg); in dsi_read()
388 static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code, in dw_mipi_dsi_phy_write() argument
396 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
398 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_TESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
401 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
403 dsi_write(dsi, DSI_PHY_TST_CTRL1, PHY_UNTESTEN | PHY_TESTDOUT(0) | in dw_mipi_dsi_phy_write()
406 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); in dw_mipi_dsi_phy_write()
412 static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns) in ns2bc() argument
414 return DIV_ROUND_UP(ns * dsi->lane_mbps / 8, 1000); in ns2bc()
420 static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns) in ns2ui() argument
422 return DIV_ROUND_UP(ns * dsi->lane_mbps, 1000); in ns2ui()
425 static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_phy_init() argument
429 vco = (dsi->lane_mbps < 200) ? 0 : (dsi->lane_mbps + 100) / 200; in dw_mipi_dsi_phy_init()
431 testdin = max_mbps_to_testdin(dsi->lane_mbps); in dw_mipi_dsi_phy_init()
433 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
435 dsi->lane_mbps); in dw_mipi_dsi_phy_init()
440 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); in dw_mipi_dsi_phy_init()
441 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLR); in dw_mipi_dsi_phy_init()
442 dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_UNTESTCLR); in dw_mipi_dsi_phy_init()
444 ret = clk_prepare_enable(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
446 DRM_DEV_ERROR(dsi->dev, "Failed to enable phy_cfg_clk\n"); in dw_mipi_dsi_phy_init()
450 dw_mipi_dsi_phy_write(dsi, 0x10, BYPASS_VCO_RANGE | in dw_mipi_dsi_phy_init()
455 dw_mipi_dsi_phy_write(dsi, 0x11, CP_CURRENT_3MA); in dw_mipi_dsi_phy_init()
456 dw_mipi_dsi_phy_write(dsi, 0x12, CP_PROGRAM_EN | LPF_PROGRAM_EN | in dw_mipi_dsi_phy_init()
459 dw_mipi_dsi_phy_write(dsi, 0x44, HSFREQRANGE_SEL(testdin)); in dw_mipi_dsi_phy_init()
461 dw_mipi_dsi_phy_write(dsi, 0x17, INPUT_DIVIDER(dsi->input_div)); in dw_mipi_dsi_phy_init()
462 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_LOW_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
464 dw_mipi_dsi_phy_write(dsi, 0x18, LOOP_DIV_HIGH_SEL(dsi->feedback_div) | in dw_mipi_dsi_phy_init()
466 dw_mipi_dsi_phy_write(dsi, 0x19, PLL_LOOP_DIV_EN | PLL_INPUT_DIV_EN); in dw_mipi_dsi_phy_init()
468 dw_mipi_dsi_phy_write(dsi, 0x22, LOW_PROGRAM_EN | in dw_mipi_dsi_phy_init()
470 dw_mipi_dsi_phy_write(dsi, 0x22, HIGH_PROGRAM_EN | in dw_mipi_dsi_phy_init()
473 dw_mipi_dsi_phy_write(dsi, 0x20, POWER_CONTROL | INTERNAL_REG_CURRENT | in dw_mipi_dsi_phy_init()
476 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_LOW | TER_CAL_DONE | in dw_mipi_dsi_phy_init()
478 dw_mipi_dsi_phy_write(dsi, 0x21, TER_RESISTOR_HIGH | LEVEL_SHIFTERS_ON | in dw_mipi_dsi_phy_init()
482 dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
483 dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); in dw_mipi_dsi_phy_init()
484 dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); in dw_mipi_dsi_phy_init()
485 dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); in dw_mipi_dsi_phy_init()
486 dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
487 dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7)); in dw_mipi_dsi_phy_init()
489 dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500)); in dw_mipi_dsi_phy_init()
490 dw_mipi_dsi_phy_write(dsi, 0x71, in dw_mipi_dsi_phy_init()
491 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5)); in dw_mipi_dsi_phy_init()
492 dw_mipi_dsi_phy_write(dsi, 0x72, in dw_mipi_dsi_phy_init()
493 THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); in dw_mipi_dsi_phy_init()
494 dw_mipi_dsi_phy_write(dsi, 0x73, in dw_mipi_dsi_phy_init()
495 THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); in dw_mipi_dsi_phy_init()
496 dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100)); in dw_mipi_dsi_phy_init()
498 dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | in dw_mipi_dsi_phy_init()
501 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, in dw_mipi_dsi_phy_init()
504 DRM_DEV_ERROR(dsi->dev, "failed to wait for phy lock state\n"); in dw_mipi_dsi_phy_init()
508 ret = readl_poll_timeout(dsi->base + DSI_PHY_STATUS, in dw_mipi_dsi_phy_init()
512 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_phy_init()
516 clk_disable_unprepare(dsi->phy_cfg_clk); in dw_mipi_dsi_phy_init()
521 static int dw_mipi_dsi_get_lane_bps(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_get_lane_bps() argument
530 bpp = mipi_dsi_pixel_format_to_bpp(dsi->format); in dw_mipi_dsi_get_lane_bps()
532 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_bps()
534 dsi->format); in dw_mipi_dsi_get_lane_bps()
541 tmp = mpclk * (bpp / dsi->lanes) * 10 / 8; in dw_mipi_dsi_get_lane_bps()
545 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_get_lane_bps()
549 pllref = DIV_ROUND_UP(clk_get_rate(dsi->pllref_clk), USEC_PER_SEC); in dw_mipi_dsi_get_lane_bps()
574 dsi->lane_mbps = pllref / n * m; in dw_mipi_dsi_get_lane_bps()
575 dsi->input_div = n; in dw_mipi_dsi_get_lane_bps()
576 dsi->feedback_div = m; in dw_mipi_dsi_get_lane_bps()
584 struct dw_mipi_dsi *dsi = host_to_dsi(host); in dw_mipi_dsi_host_attach() local
586 if (device->lanes > dsi->pdata->max_data_lanes) { in dw_mipi_dsi_host_attach()
587 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_host_attach()
593 dsi->lanes = device->lanes; in dw_mipi_dsi_host_attach()
594 dsi->channel = device->channel; in dw_mipi_dsi_host_attach()
595 dsi->format = device->format; in dw_mipi_dsi_host_attach()
596 dsi->mode_flags = device->mode_flags; in dw_mipi_dsi_host_attach()
597 dsi->panel = of_drm_find_panel(device->dev.of_node); in dw_mipi_dsi_host_attach()
598 if (!IS_ERR(dsi->panel)) in dw_mipi_dsi_host_attach()
599 return drm_panel_attach(dsi->panel, &dsi->connector); in dw_mipi_dsi_host_attach()
607 struct dw_mipi_dsi *dsi = host_to_dsi(host); in dw_mipi_dsi_host_detach() local
609 drm_panel_detach(dsi->panel); in dw_mipi_dsi_host_detach()
614 static void dw_mipi_message_config(struct dw_mipi_dsi *dsi, in dw_mipi_message_config() argument
625 dsi_write(dsi, DSI_LPCLK_CTRL, lpm ? 0 : PHY_TXREQUESTCLKHS); in dw_mipi_message_config()
626 dsi_write(dsi, DSI_CMD_MODE_CFG, val); in dw_mipi_message_config()
629 static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) in dw_mipi_dsi_gen_pkt_hdr_write() argument
634 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, in dw_mipi_dsi_gen_pkt_hdr_write()
638 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_gen_pkt_hdr_write()
643 dsi_write(dsi, DSI_GEN_HDR, hdr_val); in dw_mipi_dsi_gen_pkt_hdr_write()
646 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, in dw_mipi_dsi_gen_pkt_hdr_write()
650 DRM_DEV_ERROR(dsi->dev, "failed to write command FIFO\n"); in dw_mipi_dsi_gen_pkt_hdr_write()
657 static int dw_mipi_dsi_dcs_short_write(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_dcs_short_write() argument
670 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_dcs_short_write()
677 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, val); in dw_mipi_dsi_dcs_short_write()
680 static int dw_mipi_dsi_dcs_long_write(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_dcs_long_write() argument
690 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_dcs_long_write()
700 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder); in dw_mipi_dsi_dcs_long_write()
704 dsi_write(dsi, DSI_GEN_PLD_DATA, remainder); in dw_mipi_dsi_dcs_long_write()
709 ret = readl_poll_timeout(dsi->base + DSI_CMD_PKT_STATUS, in dw_mipi_dsi_dcs_long_write()
713 DRM_DEV_ERROR(dsi->dev, in dw_mipi_dsi_dcs_long_write()
719 return dw_mipi_dsi_gen_pkt_hdr_write(dsi, hdr_val); in dw_mipi_dsi_dcs_long_write()
725 struct dw_mipi_dsi *dsi = host_to_dsi(host); in dw_mipi_dsi_host_transfer() local
728 dw_mipi_message_config(dsi, msg); in dw_mipi_dsi_host_transfer()
734 ret = dw_mipi_dsi_dcs_short_write(dsi, msg); in dw_mipi_dsi_host_transfer()
737 ret = dw_mipi_dsi_dcs_long_write(dsi, msg); in dw_mipi_dsi_host_transfer()
740 DRM_DEV_ERROR(dsi->dev, "unsupported message type 0x%02x\n", in dw_mipi_dsi_host_transfer()
754 static void dw_mipi_dsi_video_mode_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_video_mode_config() argument
760 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_BURST) in dw_mipi_dsi_video_mode_config()
762 else if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO_SYNC_PULSE) in dw_mipi_dsi_video_mode_config()
767 dsi_write(dsi, DSI_VID_MODE_CFG, val); in dw_mipi_dsi_video_mode_config()
770 static void dw_mipi_dsi_set_mode(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_set_mode() argument
774 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_set_mode()
775 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); in dw_mipi_dsi_set_mode()
776 dsi_write(dsi, DSI_PWR_UP, POWERUP); in dw_mipi_dsi_set_mode()
778 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_set_mode()
779 dsi_write(dsi, DSI_MODE_CFG, ENABLE_VIDEO_MODE); in dw_mipi_dsi_set_mode()
780 dw_mipi_dsi_video_mode_config(dsi); in dw_mipi_dsi_set_mode()
781 dsi_write(dsi, DSI_LPCLK_CTRL, PHY_TXREQUESTCLKHS); in dw_mipi_dsi_set_mode()
782 dsi_write(dsi, DSI_PWR_UP, POWERUP); in dw_mipi_dsi_set_mode()
786 static void dw_mipi_dsi_disable(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_disable() argument
788 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_disable()
789 dsi_write(dsi, DSI_PHY_RSTZ, PHY_RSTZ); in dw_mipi_dsi_disable()
792 static void dw_mipi_dsi_init(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_init() argument
802 u32 esc_clk_division = (dsi->lane_mbps >> 3) / 20 + 1; in dw_mipi_dsi_init()
804 dsi_write(dsi, DSI_PWR_UP, RESET); in dw_mipi_dsi_init()
805 dsi_write(dsi, DSI_PHY_RSTZ, PHY_DISFORCEPLL | PHY_DISABLECLK in dw_mipi_dsi_init()
807 dsi_write(dsi, DSI_CLKMGR_CFG, TO_CLK_DIVIDSION(10) | in dw_mipi_dsi_init()
811 static void dw_mipi_dsi_dpi_config(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_dpi_config() argument
816 switch (dsi->format) { in dw_mipi_dsi_dpi_config()
836 dsi_write(dsi, DSI_DPI_VCID, DPI_VID(dsi->channel)); in dw_mipi_dsi_dpi_config()
837 dsi_write(dsi, DSI_DPI_COLOR_CODING, color); in dw_mipi_dsi_dpi_config()
838 dsi_write(dsi, DSI_DPI_CFG_POL, val); in dw_mipi_dsi_dpi_config()
839 dsi_write(dsi, DSI_DPI_LP_CMD_TIM, OUTVACT_LPCMD_TIME(4) in dw_mipi_dsi_dpi_config()
843 static void dw_mipi_dsi_packet_handler_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_packet_handler_config() argument
845 dsi_write(dsi, DSI_PCKHDL_CFG, EN_CRC_RX | EN_ECC_RX | EN_BTA); in dw_mipi_dsi_packet_handler_config()
848 static void dw_mipi_dsi_video_packet_config(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_video_packet_config() argument
851 dsi_write(dsi, DSI_VID_PKT_SIZE, VID_PKT_SIZE(mode->hdisplay)); in dw_mipi_dsi_video_packet_config()
854 static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_command_mode_config() argument
856 dsi_write(dsi, DSI_TO_CNT_CFG, HSTX_TO_CNT(1000) | LPRX_TO_CNT(1000)); in dw_mipi_dsi_command_mode_config()
857 dsi_write(dsi, DSI_BTA_TO_CNT, 0xd00); in dw_mipi_dsi_command_mode_config()
858 dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE); in dw_mipi_dsi_command_mode_config()
862 static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_get_hcomponent_lbcc() argument
868 lbcc = hcomponent * dsi->lane_mbps * MSEC_PER_SEC / 8; in dw_mipi_dsi_get_hcomponent_lbcc()
878 static void dw_mipi_dsi_line_timer_config(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_line_timer_config() argument
887 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, htotal); in dw_mipi_dsi_line_timer_config()
888 dsi_write(dsi, DSI_VID_HLINE_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
890 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hsa); in dw_mipi_dsi_line_timer_config()
891 dsi_write(dsi, DSI_VID_HSA_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
893 lbcc = dw_mipi_dsi_get_hcomponent_lbcc(dsi, mode, hbp); in dw_mipi_dsi_line_timer_config()
894 dsi_write(dsi, DSI_VID_HBP_TIME, lbcc); in dw_mipi_dsi_line_timer_config()
897 static void dw_mipi_dsi_vertical_timing_config(struct dw_mipi_dsi *dsi, in dw_mipi_dsi_vertical_timing_config() argument
907 dsi_write(dsi, DSI_VID_VACTIVE_LINES, vactive); in dw_mipi_dsi_vertical_timing_config()
908 dsi_write(dsi, DSI_VID_VSA_LINES, vsa); in dw_mipi_dsi_vertical_timing_config()
909 dsi_write(dsi, DSI_VID_VFP_LINES, vfp); in dw_mipi_dsi_vertical_timing_config()
910 dsi_write(dsi, DSI_VID_VBP_LINES, vbp); in dw_mipi_dsi_vertical_timing_config()
913 static void dw_mipi_dsi_dphy_timing_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_dphy_timing_config() argument
915 dsi_write(dsi, DSI_PHY_TMR_CFG, PHY_HS2LP_TIME(0x40) in dw_mipi_dsi_dphy_timing_config()
918 dsi_write(dsi, DSI_PHY_TMR_LPCLK_CFG, PHY_CLKHS2LP_TIME(0x40) in dw_mipi_dsi_dphy_timing_config()
922 static void dw_mipi_dsi_dphy_interface_config(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_dphy_interface_config() argument
924 dsi_write(dsi, DSI_PHY_IF_CFG, PHY_STOP_WAIT_TIME(0x20) | in dw_mipi_dsi_dphy_interface_config()
925 N_LANES(dsi->lanes)); in dw_mipi_dsi_dphy_interface_config()
928 static void dw_mipi_dsi_clear_err(struct dw_mipi_dsi *dsi) in dw_mipi_dsi_clear_err() argument
930 dsi_read(dsi, DSI_INT_ST0); in dw_mipi_dsi_clear_err()
931 dsi_read(dsi, DSI_INT_ST1); in dw_mipi_dsi_clear_err()
932 dsi_write(dsi, DSI_INT_MSK0, 0); in dw_mipi_dsi_clear_err()
933 dsi_write(dsi, DSI_INT_MSK1, 0); in dw_mipi_dsi_clear_err()
938 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); in dw_mipi_dsi_encoder_disable() local
940 if (dsi->dpms_mode != DRM_MODE_DPMS_ON) in dw_mipi_dsi_encoder_disable()
943 if (clk_prepare_enable(dsi->pclk)) { in dw_mipi_dsi_encoder_disable()
944 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n"); in dw_mipi_dsi_encoder_disable()
948 drm_panel_disable(dsi->panel); in dw_mipi_dsi_encoder_disable()
950 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE); in dw_mipi_dsi_encoder_disable()
951 drm_panel_unprepare(dsi->panel); in dw_mipi_dsi_encoder_disable()
953 dw_mipi_dsi_disable(dsi); in dw_mipi_dsi_encoder_disable()
954 pm_runtime_put(dsi->dev); in dw_mipi_dsi_encoder_disable()
955 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_encoder_disable()
956 dsi->dpms_mode = DRM_MODE_DPMS_OFF; in dw_mipi_dsi_encoder_disable()
961 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); in dw_mipi_dsi_encoder_enable() local
963 const struct dw_mipi_dsi_plat_data *pdata = dsi->pdata; in dw_mipi_dsi_encoder_enable()
964 int mux = drm_of_encoder_active_endpoint_id(dsi->dev->of_node, encoder); in dw_mipi_dsi_encoder_enable()
968 ret = dw_mipi_dsi_get_lane_bps(dsi, mode); in dw_mipi_dsi_encoder_enable()
972 if (dsi->dpms_mode == DRM_MODE_DPMS_ON) in dw_mipi_dsi_encoder_enable()
975 if (clk_prepare_enable(dsi->pclk)) { in dw_mipi_dsi_encoder_enable()
976 DRM_DEV_ERROR(dsi->dev, "Failed to enable pclk\n"); in dw_mipi_dsi_encoder_enable()
980 pm_runtime_get_sync(dsi->dev); in dw_mipi_dsi_encoder_enable()
981 dw_mipi_dsi_init(dsi); in dw_mipi_dsi_encoder_enable()
982 dw_mipi_dsi_dpi_config(dsi, mode); in dw_mipi_dsi_encoder_enable()
983 dw_mipi_dsi_packet_handler_config(dsi); in dw_mipi_dsi_encoder_enable()
984 dw_mipi_dsi_video_mode_config(dsi); in dw_mipi_dsi_encoder_enable()
985 dw_mipi_dsi_video_packet_config(dsi, mode); in dw_mipi_dsi_encoder_enable()
986 dw_mipi_dsi_command_mode_config(dsi); in dw_mipi_dsi_encoder_enable()
987 dw_mipi_dsi_line_timer_config(dsi, mode); in dw_mipi_dsi_encoder_enable()
988 dw_mipi_dsi_vertical_timing_config(dsi, mode); in dw_mipi_dsi_encoder_enable()
989 dw_mipi_dsi_dphy_timing_config(dsi); in dw_mipi_dsi_encoder_enable()
990 dw_mipi_dsi_dphy_interface_config(dsi); in dw_mipi_dsi_encoder_enable()
991 dw_mipi_dsi_clear_err(dsi); in dw_mipi_dsi_encoder_enable()
998 ret = clk_prepare_enable(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
1000 DRM_DEV_ERROR(dsi->dev, "Failed to enable grf_clk: %d\n", ret); in dw_mipi_dsi_encoder_enable()
1005 regmap_write(dsi->grf_regmap, pdata->grf_dsi0_mode_reg, in dw_mipi_dsi_encoder_enable()
1008 dw_mipi_dsi_phy_init(dsi); in dw_mipi_dsi_encoder_enable()
1011 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_CMD_MODE); in dw_mipi_dsi_encoder_enable()
1012 if (drm_panel_prepare(dsi->panel)) in dw_mipi_dsi_encoder_enable()
1013 DRM_DEV_ERROR(dsi->dev, "failed to prepare panel\n"); in dw_mipi_dsi_encoder_enable()
1015 dw_mipi_dsi_set_mode(dsi, DW_MIPI_DSI_VID_MODE); in dw_mipi_dsi_encoder_enable()
1016 drm_panel_enable(dsi->panel); in dw_mipi_dsi_encoder_enable()
1018 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_encoder_enable()
1025 regmap_write(dsi->grf_regmap, pdata->grf_switch_reg, val); in dw_mipi_dsi_encoder_enable()
1026 DRM_DEV_DEBUG(dsi->dev, in dw_mipi_dsi_encoder_enable()
1028 dsi->dpms_mode = DRM_MODE_DPMS_ON; in dw_mipi_dsi_encoder_enable()
1030 clk_disable_unprepare(dsi->grf_clk); in dw_mipi_dsi_encoder_enable()
1039 struct dw_mipi_dsi *dsi = encoder_to_dsi(encoder); in dw_mipi_dsi_encoder_atomic_check() local
1041 switch (dsi->format) { in dw_mipi_dsi_encoder_atomic_check()
1074 struct dw_mipi_dsi *dsi = con_to_dsi(connector); in dw_mipi_dsi_connector_get_modes() local
1076 return drm_panel_get_modes(dsi->panel); in dw_mipi_dsi_connector_get_modes()
1098 struct dw_mipi_dsi *dsi) in dw_mipi_dsi_register() argument
1100 struct drm_encoder *encoder = &dsi->encoder; in dw_mipi_dsi_register()
1101 struct drm_connector *connector = &dsi->connector; in dw_mipi_dsi_register()
1102 struct device *dev = dsi->dev; in dw_mipi_dsi_register()
1116 drm_encoder_helper_add(&dsi->encoder, in dw_mipi_dsi_register()
1118 ret = drm_encoder_init(drm, &dsi->encoder, &dw_mipi_dsi_encoder_funcs, in dw_mipi_dsi_register()
1128 drm_connector_init(drm, &dsi->connector, in dw_mipi_dsi_register()
1137 static int rockchip_mipi_parse_dt(struct dw_mipi_dsi *dsi) in rockchip_mipi_parse_dt() argument
1139 struct device_node *np = dsi->dev->of_node; in rockchip_mipi_parse_dt()
1141 dsi->grf_regmap = syscon_regmap_lookup_by_phandle(np, "rockchip,grf"); in rockchip_mipi_parse_dt()
1142 if (IS_ERR(dsi->grf_regmap)) { in rockchip_mipi_parse_dt()
1143 DRM_DEV_ERROR(dsi->dev, "Unable to get rockchip,grf\n"); in rockchip_mipi_parse_dt()
1144 return PTR_ERR(dsi->grf_regmap); in rockchip_mipi_parse_dt()
1169 .compatible = "rockchip,rk3288-mipi-dsi",
1172 .compatible = "rockchip,rk3399-mipi-dsi",
1188 struct dw_mipi_dsi *dsi; in dw_mipi_dsi_bind() local
1192 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in dw_mipi_dsi_bind()
1193 if (!dsi) in dw_mipi_dsi_bind()
1196 dsi->dev = dev; in dw_mipi_dsi_bind()
1197 dsi->pdata = pdata; in dw_mipi_dsi_bind()
1198 dsi->dpms_mode = DRM_MODE_DPMS_OFF; in dw_mipi_dsi_bind()
1200 ret = rockchip_mipi_parse_dt(dsi); in dw_mipi_dsi_bind()
1205 dsi->base = devm_ioremap_resource(dev, res); in dw_mipi_dsi_bind()
1206 if (IS_ERR(dsi->base)) in dw_mipi_dsi_bind()
1207 return PTR_ERR(dsi->base); in dw_mipi_dsi_bind()
1209 dsi->pllref_clk = devm_clk_get(dev, "ref"); in dw_mipi_dsi_bind()
1210 if (IS_ERR(dsi->pllref_clk)) { in dw_mipi_dsi_bind()
1211 ret = PTR_ERR(dsi->pllref_clk); in dw_mipi_dsi_bind()
1217 dsi->pclk = devm_clk_get(dev, "pclk"); in dw_mipi_dsi_bind()
1218 if (IS_ERR(dsi->pclk)) { in dw_mipi_dsi_bind()
1219 ret = PTR_ERR(dsi->pclk); in dw_mipi_dsi_bind()
1241 ret = clk_prepare_enable(dsi->pclk); in dw_mipi_dsi_bind()
1251 clk_disable_unprepare(dsi->pclk); in dw_mipi_dsi_bind()
1255 dsi->phy_cfg_clk = devm_clk_get(dev, "phy_cfg"); in dw_mipi_dsi_bind()
1256 if (IS_ERR(dsi->phy_cfg_clk)) { in dw_mipi_dsi_bind()
1257 ret = PTR_ERR(dsi->phy_cfg_clk); in dw_mipi_dsi_bind()
1265 dsi->grf_clk = devm_clk_get(dev, "grf"); in dw_mipi_dsi_bind()
1266 if (IS_ERR(dsi->grf_clk)) { in dw_mipi_dsi_bind()
1267 ret = PTR_ERR(dsi->grf_clk); in dw_mipi_dsi_bind()
1273 ret = clk_prepare_enable(dsi->pllref_clk); in dw_mipi_dsi_bind()
1279 ret = dw_mipi_dsi_register(drm, dsi); in dw_mipi_dsi_bind()
1285 dsi->dsi_host.ops = &dw_mipi_dsi_host_ops; in dw_mipi_dsi_bind()
1286 dsi->dsi_host.dev = dev; in dw_mipi_dsi_bind()
1287 ret = mipi_dsi_host_register(&dsi->dsi_host); in dw_mipi_dsi_bind()
1293 if (!dsi->panel) { in dw_mipi_dsi_bind()
1298 dev_set_drvdata(dev, dsi); in dw_mipi_dsi_bind()
1303 mipi_dsi_host_unregister(&dsi->dsi_host); in dw_mipi_dsi_bind()
1305 dsi->connector.funcs->destroy(&dsi->connector); in dw_mipi_dsi_bind()
1306 dsi->encoder.funcs->destroy(&dsi->encoder); in dw_mipi_dsi_bind()
1308 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_bind()
1315 struct dw_mipi_dsi *dsi = dev_get_drvdata(dev); in dw_mipi_dsi_unbind() local
1317 mipi_dsi_host_unregister(&dsi->dsi_host); in dw_mipi_dsi_unbind()
1320 dsi->connector.funcs->destroy(&dsi->connector); in dw_mipi_dsi_unbind()
1321 dsi->encoder.funcs->destroy(&dsi->encoder); in dw_mipi_dsi_unbind()
1323 clk_disable_unprepare(dsi->pllref_clk); in dw_mipi_dsi_unbind()