Lines Matching +full:0 +full:x720
18 #define HDA_ANA_CFG 0x0000
19 #define HDA_ANA_SCALE_CTRL_Y 0x0004
20 #define HDA_ANA_SCALE_CTRL_CB 0x0008
21 #define HDA_ANA_SCALE_CTRL_CR 0x000C
22 #define HDA_ANA_ANC_CTRL 0x0010
23 #define HDA_ANA_SRC_Y_CFG 0x0014
24 #define HDA_COEFF_Y_PH1_TAP123 0x0018
25 #define HDA_COEFF_Y_PH1_TAP456 0x001C
26 #define HDA_COEFF_Y_PH2_TAP123 0x0020
27 #define HDA_COEFF_Y_PH2_TAP456 0x0024
28 #define HDA_COEFF_Y_PH3_TAP123 0x0028
29 #define HDA_COEFF_Y_PH3_TAP456 0x002C
30 #define HDA_COEFF_Y_PH4_TAP123 0x0030
31 #define HDA_COEFF_Y_PH4_TAP456 0x0034
32 #define HDA_ANA_SRC_C_CFG 0x0040
33 #define HDA_COEFF_C_PH1_TAP123 0x0044
34 #define HDA_COEFF_C_PH1_TAP456 0x0048
35 #define HDA_COEFF_C_PH2_TAP123 0x004C
36 #define HDA_COEFF_C_PH2_TAP456 0x0050
37 #define HDA_COEFF_C_PH3_TAP123 0x0054
38 #define HDA_COEFF_C_PH3_TAP456 0x0058
39 #define HDA_COEFF_C_PH4_TAP123 0x005C
40 #define HDA_COEFF_C_PH4_TAP456 0x0060
41 #define HDA_SYNC_AWGI 0x0300
44 #define CFG_AWG_ASYNC_EN BIT(0)
49 #define CFG_AWG_FLTR_MODE_MASK (0xF << CFG_AWG_FLTR_MODE_SHIFT)
50 #define CFG_AWG_FLTR_MODE_SD (0 << CFG_AWG_FLTR_MODE_SHIFT)
56 #define CFG_PBPR_SYNC_OFF_MASK (0x7FF << CFG_PBPR_SYNC_OFF_SHIFT)
57 #define CFG_PBPR_SYNC_OFF_VAL 0x117 /* Voltage dependent. stiH416 */
60 #define SCALE_CTRL_Y_DFLT 0x00C50256
61 #define SCALE_CTRL_CB_DFLT 0x00DB0249
62 #define SCALE_CTRL_CR_DFLT 0x00DB0249
69 #define HDA_ANA_SRC_Y_CFG_ALT_2X 0x01130000
71 0x00FE83FB, 0x1F900401, 0x00000000, 0x00000000,
72 0x00F408F9, 0x055F7C25, 0x00000000, 0x00000000
75 #define HDA_ANA_SRC_C_CFG_ALT_2X 0x01750004
77 0x001305F7, 0x05274BD0, 0x00000000, 0x00000000,
78 0x0004907C, 0x09C80B9D, 0x00000000, 0x00000000
82 #define HDA_ANA_SRC_Y_CFG_4X 0x01ED0005
83 #define HDA_ANA_SRC_C_CFG_4X 0x01ED0004
85 0x00FC827F, 0x008FE20B, 0x00F684FC, 0x050F7C24,
86 0x00F4857C, 0x0A1F402E, 0x00FA027F, 0x0E076E1D
94 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
95 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
96 0x00000D8E, 0x00000104, 0x00001804, 0x00000971,
97 0x00000C26, 0x0000003B, 0x00000FB4, 0x00000FB5,
98 0x00000104, 0x00001AE8
105 0x00000971, 0x00000C26, 0x0000013B, 0x00000CDA,
106 0x00000104, 0x00000E7E, 0x00000E7F, 0x0000013B,
107 0x00000C44, 0x00000104, 0x00001804, 0x00000971,
108 0x00000C26, 0x0000003B, 0x00000F0F, 0x00000F10,
109 0x00000104, 0x00001AE8
116 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
117 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
118 0x00000C2A, 0x00000104, 0x00001804, 0x00000971,
119 0x00000C2A, 0x0000003B, 0x00000EBE, 0x00000EBF,
120 0x00000EBF, 0x00000104, 0x00001A2F, 0x00001C4B,
121 0x00001C52
128 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
129 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
130 0x00000DE2, 0x00000104, 0x00001804, 0x00000971,
131 0x00000C2A, 0x0000003B, 0x00000F51, 0x00000F51,
132 0x00000F52, 0x00000104, 0x00001A2F, 0x00001C4B,
133 0x00001C52
140 0x00000971, 0x00000C2A, 0x0000013B, 0x00000C56,
141 0x00000104, 0x00000FDC, 0x00000FDD, 0x0000013B,
142 0x00000E50, 0x00000104, 0x00001804, 0x00000971,
143 0x00000C2A, 0x0000003B, 0x00000F76, 0x00000F76,
144 0x00000F76, 0x00000104, 0x00001A2F, 0x00001C4B,
145 0x00001C52
152 0x00000904, 0x00000F18, 0x0000013B, 0x00001805,
153 0x00000904, 0x00000C3D, 0x0000003B, 0x00001A06
179 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
184 2052, 2200, 0, 1080, 1084, 1089, 1125, 0,
189 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
194 2602, 2750, 0, 1080, 1084, 1089, 1125, 0,
199 2492, 2640, 0, 1080, 1084, 1089, 1125, 0,
203 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1390,
204 1430, 1650, 0, 720, 725, 730, 750, 0,
208 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74176, 1280, 1390,
209 1430, 1650, 0, 720, 725, 730, 750, 0,
213 {{DRM_MODE("1280x720", DRM_MODE_TYPE_DRIVER, 74250, 1280, 1720,
214 1760, 1980, 0, 720, 725, 730, 750, 0,
219 798, 858, 0, 480, 489, 495, 525, 0,
224 798, 858, 0, 480, 489, 495, 525, 0,
281 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) in hda_get_mode_idx()
310 #define DBGFS_DUMP(reg) seq_printf(s, "\n %-25s 0x%08X", #reg, \
324 for (i = 0; i < AWG_MAX_INST; i++) { in hda_dbg_awg_microcode()
325 if (i % 8 == 0) in hda_dbg_awg_microcode()
335 seq_printf(s, "\n\n %-25s 0x%08X", "VIDEO_DACS_CONTROL", val); in hda_dbg_video_dacs_ctrl()
345 seq_printf(s, "HD Analog: (vaddr = 0x%p)", hda->regs); in hda_dbg_show()
358 return 0; in hda_dbg_show()
362 { "hda", hda_dbg_show, 0, NULL },
369 for (i = 0; i < ARRAY_SIZE(hda_debugfs_files); i++) in hda_debugfs_init()
390 for (i = 0; i < nb; i++) in sti_hda_configure_awg()
393 hda_write(hda, 0, HDA_SYNC_AWGI + i * 4); in sti_hda_configure_awg()
410 hda_write(hda, 0, HDA_ANA_ANC_CTRL); in sti_hda_disable()
485 for (i = 0; i < SAMPLER_COEF_NB; i++) { in sti_hda_pre_enable()
491 val = 0; in sti_hda_pre_enable()
493 0 : CFG_AWG_ASYNC_VSYNC_MTD; in sti_hda_pre_enable()
544 if (ret < 0) in sti_hda_set_mode()
550 if (ret < 0) in sti_hda_set_mode()
571 int count = 0; in sti_hda_connector_get_modes()
578 for (i = 0; i < ARRAY_SIZE(hda_supported_modes); i++) { in sti_hda_connector_get_modes()
587 if (i == 0) in sti_hda_connector_get_modes()
646 return 0; in sti_hda_late_register()
721 return 0; in sti_hda_bind()
795 return 0; in sti_hda_remove()