Lines Matching +full:0 +full:x50c
21 #define SUN4I_HDMI_CTRL_REG 0x004
24 #define SUN4I_HDMI_IRQ_REG 0x008
25 #define SUN4I_HDMI_IRQ_STA_MASK 0x73
27 #define SUN4I_HDMI_IRQ_STA_FIFO_UF BIT(0)
29 #define SUN4I_HDMI_HPD_REG 0x00c
30 #define SUN4I_HDMI_HPD_HIGH BIT(0)
32 #define SUN4I_HDMI_VID_CTRL_REG 0x010
36 #define SUN4I_HDMI_VID_TIMING_ACT_REG 0x014
37 #define SUN4I_HDMI_VID_TIMING_BP_REG 0x018
38 #define SUN4I_HDMI_VID_TIMING_FP_REG 0x01c
39 #define SUN4I_HDMI_VID_TIMING_SPW_REG 0x020
41 #define SUN4I_HDMI_VID_TIMING_X(x) ((((x) - 1) & GENMASK(11, 0)))
42 #define SUN4I_HDMI_VID_TIMING_Y(y) ((((y) - 1) & GENMASK(11, 0)) << 16)
44 #define SUN4I_HDMI_VID_TIMING_POL_REG 0x024
45 #define SUN4I_HDMI_VID_TIMING_POL_TX_CLK (0x3e0 << 16)
47 #define SUN4I_HDMI_VID_TIMING_POL_HSYNC BIT(0)
49 #define SUN4I_HDMI_AVI_INFOFRAME_REG(n) (0x080 + (n))
51 #define SUN4I_HDMI_PAD_CTRL0_REG 0x200
61 #define SUN4I_HDMI_PAD_CTRL1_REG 0x204
78 #define SUN4I_HDMI_PAD_CTRL1_INVERT_B BIT(0)
80 #define SUN4I_HDMI_PLL_CTRL_REG 0x208
89 #define SUN4I_HDMI_PLL_CTRL_CP_S(n) (((n) & 0x1f) << 12)
90 #define SUN4I_HDMI_PLL_CTRL_CS(n) (((n) & 0xf) << 8)
91 #define SUN4I_HDMI_PLL_CTRL_DIV(n) (((n) & 0xf) << 4)
93 #define SUN4I_HDMI_PLL_CTRL_VCO_S(n) ((n) & 0xf)
95 #define SUN4I_HDMI_PLL_DBG0_REG 0x20c
100 #define SUN4I_HDMI_CEC 0x214
105 #define SUN4I_HDMI_PKT_CTRL_REG(n) (0x2f0 + (4 * (n)))
108 #define SUN4I_HDMI_UNKNOWN_REG 0x300
111 #define SUN4I_HDMI_DDC_CTRL_REG 0x500
116 #define SUN4I_HDMI_DDC_CTRL_FIFO_DIR_READ (0 << 8)
117 #define SUN4I_HDMI_DDC_CTRL_RESET BIT(0)
119 #define SUN4I_HDMI_DDC_ADDR_REG 0x504
120 #define SUN4I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24)
121 #define SUN4I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
122 #define SUN4I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
123 #define SUN4I_HDMI_DDC_ADDR_SLAVE(addr) ((addr) & 0xff)
125 #define SUN4I_HDMI_DDC_INT_STATUS_REG 0x50c
133 #define SUN4I_HDMI_DDC_INT_STATUS_TRANSFER_COMPLETE BIT(0)
135 #define SUN4I_HDMI_DDC_FIFO_CTRL_REG 0x510
137 #define SUN4I_HDMI_DDC_FIFO_CTRL_RX_THRES(n) (((n) & 0xf) << 4)
140 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES(n) ((n) & 0xf)
141 #define SUN4I_HDMI_DDC_FIFO_CTRL_TX_THRES_MASK GENMASK(3, 0)
144 #define SUN4I_HDMI_DDC_FIFO_DATA_REG 0x518
146 #define SUN4I_HDMI_DDC_BYTE_COUNT_REG 0x51c
149 #define SUN4I_HDMI_DDC_CMD_REG 0x520
154 #define SUN4I_HDMI_DDC_CLK_REG 0x528
155 #define SUN4I_HDMI_DDC_CLK_M(m) (((m) & 0xf) << 3)
156 #define SUN4I_HDMI_DDC_CLK_N(n) ((n) & 0x7)
158 #define SUN4I_HDMI_DDC_LINE_CTRL_REG 0x540
165 #define SUN6I_HDMI_DDC_CTRL_REG 0x500
170 #define SUN6I_HDMI_DDC_CTRL_ENABLE BIT(0)
172 #define SUN6I_HDMI_DDC_CMD_REG 0x508
176 #define SUN6I_HDMI_DDC_ADDR_REG 0x50c
177 #define SUN6I_HDMI_DDC_ADDR_SEGMENT(seg) (((seg) & 0xff) << 24)
178 #define SUN6I_HDMI_DDC_ADDR_EDDC(addr) (((addr) & 0xff) << 16)
179 #define SUN6I_HDMI_DDC_ADDR_OFFSET(off) (((off) & 0xff) << 8)
180 #define SUN6I_HDMI_DDC_ADDR_SLAVE(addr) (((addr) & 0xff) << 1)
182 #define SUN6I_HDMI_DDC_INT_STATUS_REG 0x514
186 #define SUN6I_HDMI_DDC_FIFO_CTRL_REG 0x518
190 #define SUN6I_HDMI_DDC_CLK_REG 0x520
193 #define SUN6I_HDMI_DDC_FIFO_DATA_REG 0x580