Lines Matching full:tcon
81 static void sun4i_tcon_channel_set_status(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_channel_set_status() argument
88 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon_channel_set_status()
89 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_channel_set_status()
92 clk = tcon->dclk; in sun4i_tcon_channel_set_status()
95 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon_channel_set_status()
96 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_channel_set_status()
99 clk = tcon->sclk1; in sun4i_tcon_channel_set_status()
115 static void sun4i_tcon_lvds_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_lvds_set_status() argument
122 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
131 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_lvds_set_status()
138 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_lvds_set_status()
143 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_lvds_set_status()
152 regmap_write_bits(tcon->regs, SUN4I_TCON0_LVDS_ANA0_REG, in sun4i_tcon_lvds_set_status()
156 regmap_update_bits(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, in sun4i_tcon_lvds_set_status()
161 void sun4i_tcon_set_status(struct sun4i_tcon *tcon, in sun4i_tcon_set_status() argument
186 sun4i_tcon_lvds_set_status(tcon, encoder, false); in sun4i_tcon_set_status()
188 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon_set_status()
193 sun4i_tcon_lvds_set_status(tcon, encoder, true); in sun4i_tcon_set_status()
195 sun4i_tcon_channel_set_status(tcon, channel, enabled); in sun4i_tcon_set_status()
198 void sun4i_tcon_enable_vblank(struct sun4i_tcon *tcon, bool enable) in sun4i_tcon_enable_vblank() argument
211 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, mask, val); in sun4i_tcon_enable_vblank()
216 * This function is a helper for TCON output muxing. The TCON output
217 * muxing control register in earlier SoCs (without the TCON TOP block)
224 struct sun4i_tcon *tcon; in sun4i_get_tcon0() local
226 list_for_each_entry(tcon, &drv->tcon_list, list) in sun4i_get_tcon0()
227 if (tcon->id == 0) in sun4i_get_tcon0()
228 return tcon; in sun4i_get_tcon0()
236 void sun4i_tcon_set_mux(struct sun4i_tcon *tcon, int channel, in sun4i_tcon_set_mux() argument
241 if (tcon->quirks->set_mux) in sun4i_tcon_set_mux()
242 ret = tcon->quirks->set_mux(tcon, encoder); in sun4i_tcon_set_mux()
261 DRM_DEBUG_DRIVER("TCON %d clock delay %u\n", channel, delay); in sun4i_tcon_get_clk_delay()
266 static void sun4i_tcon0_mode_set_common(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_common() argument
270 clk_set_rate(tcon->dclk, mode->crtc_clock * 1000); in sun4i_tcon0_mode_set_common()
273 regmap_write(tcon->regs, SUN4I_TCON0_BASIC0_REG, in sun4i_tcon0_mode_set_common()
278 static void sun4i_tcon0_mode_set_cpu(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_cpu() argument
287 tcon->dclk_min_div = 4; in sun4i_tcon0_mode_set_cpu()
288 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_cpu()
290 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_cpu()
292 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_cpu()
296 regmap_write(tcon->regs, SUN4I_TCON_ECC_FIFO_REG, in sun4i_tcon0_mode_set_cpu()
299 regmap_write(tcon->regs, SUN4I_TCON0_CPU_IF_REG, in sun4i_tcon0_mode_set_cpu()
311 regmap_read(tcon->regs, SUN4I_TCON0_DCLK_REG, &tcon_div); in sun4i_tcon0_mode_set_cpu()
316 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI0_REG, in sun4i_tcon0_mode_set_cpu()
320 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI1_REG, in sun4i_tcon0_mode_set_cpu()
326 regmap_write(tcon->regs, SUN4I_TCON0_CPU_TRI2_REG, in sun4i_tcon0_mode_set_cpu()
334 regmap_write(tcon->regs, SUN4I_TCON_SAFE_PERIOD_REG, in sun4i_tcon0_mode_set_cpu()
339 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, in sun4i_tcon0_mode_set_cpu()
343 static void sun4i_tcon0_mode_set_lvds(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_lvds() argument
351 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_lvds()
353 tcon->dclk_min_div = 7; in sun4i_tcon0_mode_set_lvds()
354 tcon->dclk_max_div = 7; in sun4i_tcon0_mode_set_lvds()
355 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_lvds()
359 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_lvds()
372 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_lvds()
385 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_lvds()
397 regmap_write(tcon->regs, SUN4I_TCON0_LVDS_IF_REG, reg); in sun4i_tcon0_mode_set_lvds()
406 regmap_write(tcon->regs, SUN4I_TCON0_IO_POL_REG, val); in sun4i_tcon0_mode_set_lvds()
409 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_lvds()
414 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0xe0000000); in sun4i_tcon0_mode_set_lvds()
417 static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon, in sun4i_tcon0_mode_set_rgb() argument
424 WARN_ON(!tcon->quirks->has_channel_0); in sun4i_tcon0_mode_set_rgb()
426 tcon->dclk_min_div = tcon->quirks->dclk_min_div; in sun4i_tcon0_mode_set_rgb()
427 tcon->dclk_max_div = 127; in sun4i_tcon0_mode_set_rgb()
428 sun4i_tcon0_mode_set_common(tcon, mode); in sun4i_tcon0_mode_set_rgb()
432 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon0_mode_set_rgb()
445 regmap_write(tcon->regs, SUN4I_TCON0_BASIC1_REG, in sun4i_tcon0_mode_set_rgb()
458 regmap_write(tcon->regs, SUN4I_TCON0_BASIC2_REG, in sun4i_tcon0_mode_set_rgb()
466 regmap_write(tcon->regs, SUN4I_TCON0_BASIC3_REG, in sun4i_tcon0_mode_set_rgb()
477 regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG, in sun4i_tcon0_mode_set_rgb()
482 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon0_mode_set_rgb()
487 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, 0); in sun4i_tcon0_mode_set_rgb()
490 static void sun4i_tcon1_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon1_mode_set() argument
497 WARN_ON(!tcon->quirks->has_channel_1); in sun4i_tcon1_mode_set()
500 clk_set_rate(tcon->sclk1, mode->crtc_clock * 1000); in sun4i_tcon1_mode_set()
504 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
513 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon1_mode_set()
518 regmap_write(tcon->regs, SUN4I_TCON1_BASIC0_REG, in sun4i_tcon1_mode_set()
523 regmap_write(tcon->regs, SUN4I_TCON1_BASIC1_REG, in sun4i_tcon1_mode_set()
528 regmap_write(tcon->regs, SUN4I_TCON1_BASIC2_REG, in sun4i_tcon1_mode_set()
536 regmap_write(tcon->regs, SUN4I_TCON1_BASIC3_REG, in sun4i_tcon1_mode_set()
562 regmap_write(tcon->regs, SUN4I_TCON1_BASIC4_REG, in sun4i_tcon1_mode_set()
570 regmap_write(tcon->regs, SUN4I_TCON1_BASIC5_REG, in sun4i_tcon1_mode_set()
575 regmap_update_bits(tcon->regs, SUN4I_TCON_GCTL_REG, in sun4i_tcon1_mode_set()
580 void sun4i_tcon_mode_set(struct sun4i_tcon *tcon, in sun4i_tcon_mode_set() argument
593 sun4i_tcon0_mode_set_cpu(tcon, dsi->device, mode); in sun4i_tcon_mode_set()
596 sun4i_tcon0_mode_set_lvds(tcon, encoder, mode); in sun4i_tcon_mode_set()
599 sun4i_tcon0_mode_set_rgb(tcon, mode); in sun4i_tcon_mode_set()
600 sun4i_tcon_set_mux(tcon, 0, encoder); in sun4i_tcon_mode_set()
604 sun4i_tcon1_mode_set(tcon, mode); in sun4i_tcon_mode_set()
605 sun4i_tcon_set_mux(tcon, 1, encoder); in sun4i_tcon_mode_set()
629 struct sun4i_tcon *tcon = private; in sun4i_tcon_handler() local
630 struct drm_device *drm = tcon->drm; in sun4i_tcon_handler()
631 struct sun4i_crtc *scrtc = tcon->crtc; in sun4i_tcon_handler()
635 regmap_read(tcon->regs, SUN4I_TCON_GINT0_REG, &status); in sun4i_tcon_handler()
646 regmap_update_bits(tcon->regs, SUN4I_TCON_GINT0_REG, in sun4i_tcon_handler()
659 struct sun4i_tcon *tcon) in sun4i_tcon_init_clocks() argument
661 tcon->clk = devm_clk_get(dev, "ahb"); in sun4i_tcon_init_clocks()
662 if (IS_ERR(tcon->clk)) { in sun4i_tcon_init_clocks()
663 dev_err(dev, "Couldn't get the TCON bus clock\n"); in sun4i_tcon_init_clocks()
664 return PTR_ERR(tcon->clk); in sun4i_tcon_init_clocks()
666 clk_prepare_enable(tcon->clk); in sun4i_tcon_init_clocks()
668 if (tcon->quirks->has_channel_0) { in sun4i_tcon_init_clocks()
669 tcon->sclk0 = devm_clk_get(dev, "tcon-ch0"); in sun4i_tcon_init_clocks()
670 if (IS_ERR(tcon->sclk0)) { in sun4i_tcon_init_clocks()
671 dev_err(dev, "Couldn't get the TCON channel 0 clock\n"); in sun4i_tcon_init_clocks()
672 return PTR_ERR(tcon->sclk0); in sun4i_tcon_init_clocks()
675 clk_prepare_enable(tcon->sclk0); in sun4i_tcon_init_clocks()
677 if (tcon->quirks->has_channel_1) { in sun4i_tcon_init_clocks()
678 tcon->sclk1 = devm_clk_get(dev, "tcon-ch1"); in sun4i_tcon_init_clocks()
679 if (IS_ERR(tcon->sclk1)) { in sun4i_tcon_init_clocks()
680 dev_err(dev, "Couldn't get the TCON channel 1 clock\n"); in sun4i_tcon_init_clocks()
681 return PTR_ERR(tcon->sclk1); in sun4i_tcon_init_clocks()
688 static void sun4i_tcon_free_clocks(struct sun4i_tcon *tcon) in sun4i_tcon_free_clocks() argument
690 clk_disable_unprepare(tcon->sclk0); in sun4i_tcon_free_clocks()
691 clk_disable_unprepare(tcon->clk); in sun4i_tcon_free_clocks()
695 struct sun4i_tcon *tcon) in sun4i_tcon_init_irq() argument
702 dev_err(dev, "Couldn't retrieve the TCON interrupt\n"); in sun4i_tcon_init_irq()
707 dev_name(dev), tcon); in sun4i_tcon_init_irq()
724 struct sun4i_tcon *tcon) in sun4i_tcon_init_regmap() argument
735 tcon->regs = devm_regmap_init_mmio(dev, regs, in sun4i_tcon_init_regmap()
737 if (IS_ERR(tcon->regs)) { in sun4i_tcon_init_regmap()
738 dev_err(dev, "Couldn't create the TCON regmap\n"); in sun4i_tcon_init_regmap()
739 return PTR_ERR(tcon->regs); in sun4i_tcon_init_regmap()
742 /* Make sure the TCON is disabled and all IRQs are off */ in sun4i_tcon_init_regmap()
743 regmap_write(tcon->regs, SUN4I_TCON_GCTL_REG, 0); in sun4i_tcon_init_regmap()
744 regmap_write(tcon->regs, SUN4I_TCON_GINT0_REG, 0); in sun4i_tcon_init_regmap()
745 regmap_write(tcon->regs, SUN4I_TCON_GINT1_REG, 0); in sun4i_tcon_init_regmap()
748 regmap_write(tcon->regs, SUN4I_TCON0_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
749 regmap_write(tcon->regs, SUN4I_TCON1_IO_TRI_REG, ~0); in sun4i_tcon_init_regmap()
756 * the TCON is always tied to just one backend. Hence we can traverse
757 * the of_graph upwards to find the backend our tcon is connected to,
762 * registered and binded before the TCON, we can just go through the
783 * This only works if there is only one path from the TCON in sun4i_tcon_find_engine_traverse()
811 * more than one input and one output (TCON TOP) exits, correct in sun4i_tcon_find_engine_traverse()
836 * connection between components, up to and including the TCON, of
869 * Once we know the TCON's id, we can look through the list of
887 * we assumed the TCON was always tied to just one backend. However
888 * this proved not to be the case. On the A31, the TCON can select
890 * the backend can choose which TCON to output to.
893 * connection between components, up to and including the TCON, of
899 * However the connections between the backend and TCON were assumed
902 * up the remote endpoint ID of a TCON input endpoint. TCON1 would be
905 * This function first checks if the TCON node has 2 input endpoints.
910 * have endpoint connections between the backend and TCON across
930 * connections between the backend and TCON? in sun4i_tcon_find_engine()
955 struct sun4i_tcon *tcon; in sun4i_tcon_bind() local
966 tcon = devm_kzalloc(dev, sizeof(*tcon), GFP_KERNEL); in sun4i_tcon_bind()
967 if (!tcon) in sun4i_tcon_bind()
969 dev_set_drvdata(dev, tcon); in sun4i_tcon_bind()
970 tcon->drm = drm; in sun4i_tcon_bind()
971 tcon->dev = dev; in sun4i_tcon_bind()
972 tcon->id = engine->id; in sun4i_tcon_bind()
973 tcon->quirks = of_device_get_match_data(dev); in sun4i_tcon_bind()
975 tcon->lcd_rst = devm_reset_control_get(dev, "lcd"); in sun4i_tcon_bind()
976 if (IS_ERR(tcon->lcd_rst)) { in sun4i_tcon_bind()
978 return PTR_ERR(tcon->lcd_rst); in sun4i_tcon_bind()
981 if (tcon->quirks->needs_edp_reset) { in sun4i_tcon_bind()
995 /* Make sure our TCON is reset */ in sun4i_tcon_bind()
996 ret = reset_control_reset(tcon->lcd_rst); in sun4i_tcon_bind()
1002 if (tcon->quirks->supports_lvds) { in sun4i_tcon_bind()
1010 tcon->lvds_rst = devm_reset_control_get_optional(dev, "lvds"); in sun4i_tcon_bind()
1011 if (IS_ERR(tcon->lvds_rst)) { in sun4i_tcon_bind()
1013 return PTR_ERR(tcon->lvds_rst); in sun4i_tcon_bind()
1014 } else if (tcon->lvds_rst) { in sun4i_tcon_bind()
1016 reset_control_reset(tcon->lvds_rst); in sun4i_tcon_bind()
1028 if (tcon->quirks->has_lvds_alt) { in sun4i_tcon_bind()
1029 tcon->lvds_pll = devm_clk_get(dev, "lvds-alt"); in sun4i_tcon_bind()
1030 if (IS_ERR(tcon->lvds_pll)) { in sun4i_tcon_bind()
1031 if (PTR_ERR(tcon->lvds_pll) == -ENOENT) { in sun4i_tcon_bind()
1035 return PTR_ERR(tcon->lvds_pll); in sun4i_tcon_bind()
1043 (tcon->quirks->has_lvds_alt && !has_lvds_alt)) { in sun4i_tcon_bind()
1054 ret = sun4i_tcon_init_clocks(dev, tcon); in sun4i_tcon_bind()
1056 dev_err(dev, "Couldn't init our TCON clocks\n"); in sun4i_tcon_bind()
1060 ret = sun4i_tcon_init_regmap(dev, tcon); in sun4i_tcon_bind()
1062 dev_err(dev, "Couldn't init our TCON regmap\n"); in sun4i_tcon_bind()
1066 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1067 ret = sun4i_dclk_create(dev, tcon); in sun4i_tcon_bind()
1069 dev_err(dev, "Couldn't create our TCON dot clock\n"); in sun4i_tcon_bind()
1074 ret = sun4i_tcon_init_irq(dev, tcon); in sun4i_tcon_bind()
1076 dev_err(dev, "Couldn't init our TCON interrupts\n"); in sun4i_tcon_bind()
1080 tcon->crtc = sun4i_crtc_init(drm, engine, tcon); in sun4i_tcon_bind()
1081 if (IS_ERR(tcon->crtc)) { in sun4i_tcon_bind()
1083 ret = PTR_ERR(tcon->crtc); in sun4i_tcon_bind()
1087 if (tcon->quirks->has_channel_0) { in sun4i_tcon_bind()
1089 * If we have an LVDS panel connected to the TCON, we should in sun4i_tcon_bind()
1096 ret = sun4i_lvds_init(drm, tcon); in sun4i_tcon_bind()
1100 ret = sun4i_rgb_init(drm, tcon); in sun4i_tcon_bind()
1107 if (tcon->quirks->needs_de_be_mux) { in sun4i_tcon_bind()
1113 * the CRTC is tied to the TCON, while the layers are in sun4i_tcon_bind()
1118 regmap_update_bits(tcon->regs, SUN4I_TCON0_CTL_REG, in sun4i_tcon_bind()
1120 tcon->id); in sun4i_tcon_bind()
1121 regmap_update_bits(tcon->regs, SUN4I_TCON1_CTL_REG, in sun4i_tcon_bind()
1123 tcon->id); in sun4i_tcon_bind()
1126 list_add_tail(&tcon->list, &drv->tcon_list); in sun4i_tcon_bind()
1131 if (tcon->quirks->has_channel_0) in sun4i_tcon_bind()
1132 sun4i_dclk_free(tcon); in sun4i_tcon_bind()
1134 sun4i_tcon_free_clocks(tcon); in sun4i_tcon_bind()
1136 reset_control_assert(tcon->lcd_rst); in sun4i_tcon_bind()
1143 struct sun4i_tcon *tcon = dev_get_drvdata(dev); in sun4i_tcon_unbind() local
1145 list_del(&tcon->list); in sun4i_tcon_unbind()
1146 if (tcon->quirks->has_channel_0) in sun4i_tcon_unbind()
1147 sun4i_dclk_free(tcon); in sun4i_tcon_unbind()
1148 sun4i_tcon_free_clocks(tcon); in sun4i_tcon_unbind()
1183 /* platform specific TCON muxing callbacks */
1184 static int sun4i_a10_tcon_set_mux(struct sun4i_tcon *tcon, in sun4i_a10_tcon_set_mux() argument
1203 0x3 << shift, tcon->id << shift); in sun4i_a10_tcon_set_mux()
1208 static int sun5i_a13_tcon_set_mux(struct sun4i_tcon *tcon, in sun5i_a13_tcon_set_mux() argument
1221 return regmap_write(tcon->regs, SUN4I_TCON_MUX_CTRL_REG, val); in sun5i_a13_tcon_set_mux()
1224 static int sun6i_tcon_set_mux(struct sun4i_tcon *tcon, in sun6i_tcon_set_mux() argument
1244 0x3 << shift, tcon->id << shift); in sun6i_tcon_set_mux()
1319 /* sun4i_drv uses this list to check if a device node is a TCON */
1321 { .compatible = "allwinner,sun4i-a10-tcon", .data = &sun4i_a10_quirks },
1322 { .compatible = "allwinner,sun5i-a13-tcon", .data = &sun5i_a13_quirks },
1323 { .compatible = "allwinner,sun6i-a31-tcon", .data = &sun6i_a31_quirks },
1324 { .compatible = "allwinner,sun6i-a31s-tcon", .data = &sun6i_a31s_quirks },
1325 { .compatible = "allwinner,sun7i-a20-tcon", .data = &sun7i_a20_quirks },
1326 { .compatible = "allwinner,sun8i-a33-tcon", .data = &sun8i_a33_quirks },
1327 { .compatible = "allwinner,sun8i-a83t-tcon-lcd", .data = &sun8i_a83t_lcd_quirks },
1328 { .compatible = "allwinner,sun8i-a83t-tcon-tv", .data = &sun8i_a83t_tv_quirks },
1329 { .compatible = "allwinner,sun8i-v3s-tcon", .data = &sun8i_v3s_quirks },
1330 { .compatible = "allwinner,sun9i-a80-tcon-lcd", .data = &sun9i_a80_tcon_lcd_quirks },
1331 { .compatible = "allwinner,sun9i-a80-tcon-tv", .data = &sun9i_a80_tcon_tv_quirks },
1341 .name = "sun4i-tcon",