Lines Matching full:value
399 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl() local
401 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
403 return value; in tegra_sor_readl()
406 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
409 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
410 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
448 u32 value; in tegra_clk_sor_pad_set_parent() local
450 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
451 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_clk_sor_pad_set_parent()
455 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_clk_sor_pad_set_parent()
459 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_clk_sor_pad_set_parent()
463 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
473 u32 value; in tegra_clk_sor_pad_get_parent() local
475 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
477 switch (value & SOR_CLK_CNTRL_DP_CLK_SEL_MASK) { in tegra_clk_sor_pad_get_parent()
528 u32 value; in tegra_sor_dp_train_fast() local
532 value = SOR_LANE_DRIVE_CURRENT_LANE3(0x40) | in tegra_sor_dp_train_fast()
536 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
538 value = SOR_LANE_PREEMPHASIS_LANE3(0x0f) | in tegra_sor_dp_train_fast()
542 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
544 value = SOR_LANE_POSTCURSOR_LANE3(0x00) | in tegra_sor_dp_train_fast()
548 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
553 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
554 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_dp_train_fast()
555 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_dp_train_fast()
556 value |= SOR_DP_PADCTL_TX_PU(2); /* XXX: don't hardcode? */ in tegra_sor_dp_train_fast()
557 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
559 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
560 value |= SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_train_fast()
562 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
566 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
567 value &= ~(SOR_DP_PADCTL_CM_TXD_3 | SOR_DP_PADCTL_CM_TXD_2 | in tegra_sor_dp_train_fast()
569 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
575 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
579 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
582 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
590 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
591 value |= SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_dp_train_fast()
592 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_dp_train_fast()
593 value |= SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_dp_train_fast()
594 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
596 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
600 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
603 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
611 for (i = 0, value = 0; i < link->num_lanes; i++) { in tegra_sor_dp_train_fast()
615 value = (value << 8) | lane; in tegra_sor_dp_train_fast()
618 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
645 u32 value; in tegra_sor_setup_pwm() local
647 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
648 value &= ~SOR_PWM_DIV_MASK; in tegra_sor_setup_pwm()
649 value |= 0x400; /* period */ in tegra_sor_setup_pwm()
650 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
652 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
653 value &= ~SOR_PWM_CTL_DUTY_CYCLE_MASK; in tegra_sor_setup_pwm()
654 value |= 0x400; /* duty cycle */ in tegra_sor_setup_pwm()
655 value &= ~SOR_PWM_CTL_CLK_SEL; /* clock source: PCLK */ in tegra_sor_setup_pwm()
656 value |= SOR_PWM_CTL_TRIGGER; in tegra_sor_setup_pwm()
657 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
662 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
663 if ((value & SOR_PWM_CTL_TRIGGER) == 0) in tegra_sor_setup_pwm()
674 unsigned long value, timeout; in tegra_sor_attach() local
677 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
678 value |= SOR_SUPER_STATE_HEAD_MODE_AWAKE; in tegra_sor_attach()
679 value |= SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_attach()
680 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
684 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
685 value |= SOR_SUPER_STATE_ATTACHED; in tegra_sor_attach()
686 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
692 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
693 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_attach()
704 unsigned long value, timeout; in tegra_sor_wakeup() local
710 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
711 value &= SOR_TEST_HEAD_MODE_MASK; in tegra_sor_wakeup()
713 if (value == SOR_TEST_HEAD_MODE_AWAKE) in tegra_sor_wakeup()
724 u32 value; in tegra_sor_power_up() local
726 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
727 value |= SOR_PWR_TRIGGER | SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_up()
728 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
733 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
734 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_up()
921 u32 value; in tegra_sor_apply_config() local
923 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
924 value &= ~SOR_DP_LINKCTL_TU_SIZE_MASK; in tegra_sor_apply_config()
925 value |= SOR_DP_LINKCTL_TU_SIZE(config->tu_size); in tegra_sor_apply_config()
926 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
928 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
929 value &= ~SOR_DP_CONFIG_WATERMARK_MASK; in tegra_sor_apply_config()
930 value |= SOR_DP_CONFIG_WATERMARK(config->watermark); in tegra_sor_apply_config()
932 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_COUNT_MASK; in tegra_sor_apply_config()
933 value |= SOR_DP_CONFIG_ACTIVE_SYM_COUNT(config->active_count); in tegra_sor_apply_config()
935 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_FRAC_MASK; in tegra_sor_apply_config()
936 value |= SOR_DP_CONFIG_ACTIVE_SYM_FRAC(config->active_frac); in tegra_sor_apply_config()
939 value |= SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
941 value &= ~SOR_DP_CONFIG_ACTIVE_SYM_POLARITY; in tegra_sor_apply_config()
943 value |= SOR_DP_CONFIG_ACTIVE_SYM_ENABLE; in tegra_sor_apply_config()
944 value |= SOR_DP_CONFIG_DISPARITY_NEGATIVE; in tegra_sor_apply_config()
945 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
947 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
948 value &= ~SOR_DP_AUDIO_HBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
949 value |= config->hblank_symbols & 0xffff; in tegra_sor_apply_config()
950 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
952 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
953 value &= ~SOR_DP_AUDIO_VBLANK_SYMBOLS_MASK; in tegra_sor_apply_config()
954 value |= config->vblank_symbols & 0xffff; in tegra_sor_apply_config()
955 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
964 u32 value; in tegra_sor_mode_set() local
966 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
967 value &= ~SOR_STATE_ASY_PIXELDEPTH_MASK; in tegra_sor_mode_set()
968 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_mode_set()
969 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_mode_set()
971 value |= SOR_STATE_ASY_CRC_MODE_COMPLETE | in tegra_sor_mode_set()
975 value &= ~SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
978 value |= SOR_STATE_ASY_HSYNCPOL; in tegra_sor_mode_set()
981 value &= ~SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
984 value |= SOR_STATE_ASY_VSYNCPOL; in tegra_sor_mode_set()
988 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_48_444; in tegra_sor_mode_set()
992 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_36_444; in tegra_sor_mode_set()
996 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_30_444; in tegra_sor_mode_set()
1000 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1004 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_18_444; in tegra_sor_mode_set()
1008 value |= SOR_STATE_ASY_PIXELDEPTH_BPP_24_444; in tegra_sor_mode_set()
1012 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1019 value = ((mode->vtotal & 0x7fff) << 16) | (mode->htotal & 0x7fff); in tegra_sor_mode_set()
1020 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1026 value = ((vse & 0x7fff) << 16) | (hse & 0x7fff); in tegra_sor_mode_set()
1027 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1033 value = ((vbe & 0x7fff) << 16) | (hbe & 0x7fff); in tegra_sor_mode_set()
1034 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1040 value = ((vbs & 0x7fff) << 16) | (hbs & 0x7fff); in tegra_sor_mode_set()
1041 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1049 unsigned long value, timeout; in tegra_sor_detach() local
1052 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1053 value &= ~SOR_SUPER_STATE_MODE_NORMAL; in tegra_sor_detach()
1054 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1060 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1061 if (value & SOR_PWR_MODE_SAFE) in tegra_sor_detach()
1065 if ((value & SOR_PWR_MODE_SAFE) == 0) in tegra_sor_detach()
1069 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1070 value &= ~SOR_SUPER_STATE_HEAD_MODE_MASK; in tegra_sor_detach()
1071 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1075 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1076 value &= ~SOR_SUPER_STATE_ATTACHED; in tegra_sor_detach()
1077 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1083 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1084 if ((value & SOR_TEST_ATTACHED) == 0) in tegra_sor_detach()
1090 if ((value & SOR_TEST_ATTACHED) != 0) in tegra_sor_detach()
1098 unsigned long value, timeout; in tegra_sor_power_down() local
1101 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1102 value &= ~SOR_PWR_NORMAL_STATE_PU; in tegra_sor_power_down()
1103 value |= SOR_PWR_TRIGGER; in tegra_sor_power_down()
1104 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1109 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1110 if ((value & SOR_PWR_TRIGGER) == 0) in tegra_sor_power_down()
1116 if ((value & SOR_PWR_TRIGGER) != 0) in tegra_sor_power_down()
1126 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1127 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_power_down()
1129 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1132 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_UP | in tegra_sor_power_down()
1134 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1139 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1140 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_power_down()
1146 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) != 0) in tegra_sor_power_down()
1149 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1150 value |= SOR_PLL2_PORT_POWERDOWN; in tegra_sor_power_down()
1151 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1155 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1156 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_power_down()
1157 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1159 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1160 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_power_down()
1161 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_power_down()
1162 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1171 u32 value; in tegra_sor_crc_wait() local
1176 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1177 if (value & SOR_CRCA_VALID) in tegra_sor_crc_wait()
1193 u32 value; in tegra_sor_show_crc() local
1202 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1203 value &= ~SOR_STATE_ASY_CRC_MODE_MASK; in tegra_sor_show_crc()
1204 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1206 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1207 value |= SOR_CRC_CNTRL_ENABLE; in tegra_sor_show_crc()
1208 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1210 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1211 value &= ~SOR_TEST_CRC_POST_SERIALIZE; in tegra_sor_show_crc()
1212 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1219 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1221 seq_printf(s, "%08x\n", value); in tegra_sor_show_crc()
1515 u32 value; in tegra_sor_edp_disable() local
1533 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1534 value &= ~SOR_ENABLE(0); in tegra_sor_edp_disable()
1535 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_disable()
1562 unsigned int *value)
1591 if (value) {
1593 *value = a + 1;
1595 *value = a;
1614 u32 value; in tegra_sor_edp_enable() local
1645 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1646 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_edp_enable()
1647 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_DPCLK; in tegra_sor_edp_enable()
1648 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1650 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1651 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_edp_enable()
1652 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1655 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1656 value |= SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_edp_enable()
1657 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1659 value = SOR_PLL0_ICHPMP(0xf) | SOR_PLL0_VCOCAP_RST | in tegra_sor_edp_enable()
1661 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1663 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1664 value |= SOR_PLL2_SEQ_PLLCAPPD; in tegra_sor_edp_enable()
1665 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_edp_enable()
1666 value |= SOR_PLL2_LVDS_ENABLE; in tegra_sor_edp_enable()
1667 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1669 value = SOR_PLL1_TERM_COMPOUT | SOR_PLL1_TMDS_TERM; in tegra_sor_edp_enable()
1670 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_edp_enable()
1673 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1674 if ((value & SOR_PLL2_SEQ_PLLCAPPD_ENFORCE) == 0) in tegra_sor_edp_enable()
1680 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1681 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_edp_enable()
1682 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_edp_enable()
1683 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1690 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1691 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1692 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G1_62; in tegra_sor_edp_enable()
1693 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1696 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1697 value |= SOR_PLL2_SEQ_PLLCAPPD_ENFORCE | SOR_PLL2_PORT_POWERDOWN | in tegra_sor_edp_enable()
1699 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1701 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1702 value |= SOR_PLL0_VCOPD | SOR_PLL0_PWR; in tegra_sor_edp_enable()
1703 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1705 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1706 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_edp_enable()
1707 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1717 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1718 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_edp_enable()
1719 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1724 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1725 value &= ~SOR_PLL0_VCOPD; in tegra_sor_edp_enable()
1726 value &= ~SOR_PLL0_PWR; in tegra_sor_edp_enable()
1727 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1729 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1730 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_edp_enable()
1731 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1736 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1737 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_edp_enable()
1738 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1741 for (value = 0, i = 0; i < 5; i++) in tegra_sor_edp_enable()
1742 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_edp_enable()
1746 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_edp_enable()
1754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1757 value &= ~(SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2); in tegra_sor_edp_enable()
1759 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_2; in tegra_sor_edp_enable()
1762 value &= ~SOR_DP_PADCTL_PD_TXD_1; in tegra_sor_edp_enable()
1764 value |= SOR_DP_PADCTL_PD_TXD_1; in tegra_sor_edp_enable()
1767 value &= ~SOR_DP_PADCTL_PD_TXD_0; in tegra_sor_edp_enable()
1769 value |= SOR_DP_PADCTL_PD_TXD_0; in tegra_sor_edp_enable()
1771 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1773 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1774 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_edp_enable()
1775 value |= SOR_DP_LINKCTL_LANE_COUNT(link.num_lanes); in tegra_sor_edp_enable()
1776 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1779 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_edp_enable()
1781 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1784 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1785 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_edp_enable()
1792 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1793 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1794 value |= drm_dp_link_rate_to_bw_code(link.rate) << 2; in tegra_sor_edp_enable()
1795 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1800 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1801 value |= SOR_DP_LINKCTL_ENABLE; in tegra_sor_edp_enable()
1802 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_edp_enable()
1803 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1805 for (i = 0, value = 0; i < 4; i++) { in tegra_sor_edp_enable()
1809 value = (value << 8) | lane; in tegra_sor_edp_enable()
1812 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1815 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1816 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_edp_enable()
1817 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1834 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1835 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_edp_enable()
1836 value |= SOR_CLK_CNTRL_DP_LINK_SPEED(rate); in tegra_sor_edp_enable()
1837 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1839 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1840 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_edp_enable()
1841 value |= SOR_DP_LINKCTL_LANE_COUNT(lanes); in tegra_sor_edp_enable()
1844 value |= SOR_DP_LINKCTL_ENHANCED_FRAME; in tegra_sor_edp_enable()
1846 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1854 value = (value << 8) | lane; in tegra_sor_edp_enable()
1857 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1870 value = SOR_CSTM_LVDS | SOR_CSTM_LINK_ACT_A | SOR_CSTM_LINK_ACT_B | in tegra_sor_edp_enable()
1872 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_edp_enable()
1875 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_edp_enable()
1876 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_edp_enable()
1877 value |= SOR_STATE_ASY_PROTOCOL_DP_A; in tegra_sor_edp_enable()
1878 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_edp_enable()
1889 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
1890 value |= SOR_ENABLE(0); in tegra_sor_edp_enable()
1891 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_edp_enable()
1964 u32 value = 0; in tegra_sor_hdmi_subpack() local
1968 value = (value << 8) | ptr[i - 1]; in tegra_sor_hdmi_subpack()
1970 return value; in tegra_sor_hdmi_subpack()
1979 u32 value; in tegra_sor_hdmi_write_infopack() local
2000 value = INFOFRAME_HEADER_TYPE(ptr[0]) | in tegra_sor_hdmi_write_infopack()
2003 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
2014 value = tegra_sor_hdmi_subpack(&ptr[i], num); in tegra_sor_hdmi_write_infopack()
2015 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2019 value = tegra_sor_hdmi_subpack(&ptr[i + 4], num); in tegra_sor_hdmi_write_infopack()
2020 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2030 u32 value; in tegra_sor_hdmi_setup_avi_infoframe() local
2034 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2035 value &= ~INFOFRAME_CTRL_SINGLE; in tegra_sor_hdmi_setup_avi_infoframe()
2036 value &= ~INFOFRAME_CTRL_OTHER; in tegra_sor_hdmi_setup_avi_infoframe()
2037 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
2038 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2055 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2056 value |= INFOFRAME_CTRL_CHECKSUM_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
2057 value |= INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_setup_avi_infoframe()
2058 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2065 u32 value; in tegra_sor_hdmi_disable_audio_infoframe() local
2067 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2068 value &= ~INFOFRAME_CTRL_ENABLE; in tegra_sor_hdmi_disable_audio_infoframe()
2069 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2086 u32 value; in tegra_sor_hdmi_disable_scrambling() local
2088 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2089 value &= ~SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_disable_scrambling()
2090 value &= ~SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_disable_scrambling()
2091 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2114 u32 value; in tegra_sor_hdmi_enable_scrambling() local
2116 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2117 value |= SOR_HDMI2_CTRL_CLOCK_MODE_DIV_BY_4; in tegra_sor_hdmi_enable_scrambling()
2118 value |= SOR_HDMI2_CTRL_SCRAMBLE; in tegra_sor_hdmi_enable_scrambling()
2119 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2164 u32 value; in tegra_sor_hdmi_disable() local
2177 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2180 value &= ~(SOR1_TIMING_CYA | SOR_ENABLE(1)); in tegra_sor_hdmi_disable()
2182 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2184 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_disable()
2210 u32 value; in tegra_sor_hdmi_enable() local
2234 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2235 value &= ~SOR_PLL2_BANDGAP_POWERDOWN; in tegra_sor_hdmi_enable()
2236 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2240 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2241 value &= ~SOR_PLL3_PLL_VDD_MODE_3V3; in tegra_sor_hdmi_enable()
2242 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2244 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2245 value &= ~SOR_PLL0_VCOPD; in tegra_sor_hdmi_enable()
2246 value &= ~SOR_PLL0_PWR; in tegra_sor_hdmi_enable()
2247 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2249 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2250 value &= ~SOR_PLL2_SEQ_PLLCAPPD_ENFORCE; in tegra_sor_hdmi_enable()
2251 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2255 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2256 value &= ~SOR_PLL2_POWERDOWN_OVERRIDE; in tegra_sor_hdmi_enable()
2257 value &= ~SOR_PLL2_PORT_POWERDOWN; in tegra_sor_hdmi_enable()
2258 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2262 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2263 value |= SOR_DP_PADCTL_PD_TXD_3 | SOR_DP_PADCTL_PD_TXD_0 | in tegra_sor_hdmi_enable()
2265 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2268 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2269 if ((value & SOR_LANE_SEQ_CTL_STATE_BUSY) == 0) in tegra_sor_hdmi_enable()
2275 value = SOR_LANE_SEQ_CTL_TRIGGER | SOR_LANE_SEQ_CTL_SEQUENCE_DOWN | in tegra_sor_hdmi_enable()
2277 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2280 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2281 if ((value & SOR_LANE_SEQ_CTL_TRIGGER) == 0) in tegra_sor_hdmi_enable()
2287 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2288 value &= ~SOR_CLK_CNTRL_DP_LINK_SPEED_MASK; in tegra_sor_hdmi_enable()
2289 value &= ~SOR_CLK_CNTRL_DP_CLK_SEL_MASK; in tegra_sor_hdmi_enable()
2293 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G2_70; in tegra_sor_hdmi_enable()
2296 value |= SOR_CLK_CNTRL_DP_LINK_SPEED_G5_40; in tegra_sor_hdmi_enable()
2299 value |= SOR_CLK_CNTRL_DP_CLK_SEL_SINGLE_PCLK; in tegra_sor_hdmi_enable()
2300 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2305 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2306 value &= ~SOR_DP_LINKCTL_LANE_COUNT_MASK; in tegra_sor_hdmi_enable()
2307 value |= SOR_DP_LINKCTL_LANE_COUNT(4); in tegra_sor_hdmi_enable()
2308 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2310 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2311 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2312 value &= ~SOR_DP_SPARE_PANEL_INTERNAL; in tegra_sor_hdmi_enable()
2313 value &= ~SOR_DP_SPARE_SEQ_ENABLE; in tegra_sor_hdmi_enable()
2314 value &= ~SOR_DP_SPARE_MACRO_SOR_CLK; in tegra_sor_hdmi_enable()
2315 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2317 value = SOR_SEQ_CTL_PU_PC(0) | SOR_SEQ_CTL_PU_PC_ALT(0) | in tegra_sor_hdmi_enable()
2319 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2321 value = SOR_SEQ_INST_DRIVE_PWM_OUT_LO | SOR_SEQ_INST_HALT | in tegra_sor_hdmi_enable()
2323 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2324 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2328 value = SOR_REFCLK_DIV_INT(div) | SOR_REFCLK_DIV_FRAC(div); in tegra_sor_hdmi_enable()
2329 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2333 for (value = 0, i = 0; i < 5; i++) in tegra_sor_hdmi_enable()
2334 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2338 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2364 value = SOR_INPUT_CONTROL_HDMI_SRC_SELECT(dc->pipe); in tegra_sor_hdmi_enable()
2368 value |= SOR_INPUT_CONTROL_ARM_VIDEO_RANGE_LIMITED; in tegra_sor_hdmi_enable()
2370 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2375 value = SOR_HDMI_CTRL_ENABLE | SOR_HDMI_CTRL_MAX_AC_PACKET(max_ac) | in tegra_sor_hdmi_enable()
2377 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2385 value = PULSE_LAST_END_A | PULSE_QUAL_VACTIVE | in tegra_sor_hdmi_enable()
2387 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_CONTROL); in tegra_sor_hdmi_enable()
2389 value = PULSE_END(pulse_start + 8) | PULSE_START(pulse_start); in tegra_sor_hdmi_enable()
2390 tegra_dc_writel(dc, value, DC_DISP_H_PULSE2_POSITION_A); in tegra_sor_hdmi_enable()
2392 value = tegra_dc_readl(dc, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2393 value |= H_PULSE2_ENABLE; in tegra_sor_hdmi_enable()
2394 tegra_dc_writel(dc, value, DC_DISP_DISP_SIGNAL_OPTIONS0); in tegra_sor_hdmi_enable()
2406 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2407 value &= ~SOR_STATE_ASY_PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2408 value |= SOR_STATE_ASY_PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2409 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2412 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2413 value &= ~SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2414 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2424 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2425 value &= ~SOR_PLL0_ICHPMP_MASK; in tegra_sor_hdmi_enable()
2426 value &= ~SOR_PLL0_FILTER_MASK; in tegra_sor_hdmi_enable()
2427 value &= ~SOR_PLL0_VCOCAP_MASK; in tegra_sor_hdmi_enable()
2428 value |= SOR_PLL0_ICHPMP(settings->ichpmp); in tegra_sor_hdmi_enable()
2429 value |= SOR_PLL0_FILTER(settings->filter); in tegra_sor_hdmi_enable()
2430 value |= SOR_PLL0_VCOCAP(settings->vcocap); in tegra_sor_hdmi_enable()
2431 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2434 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2435 value &= ~SOR_PLL1_LOADADJ_MASK; in tegra_sor_hdmi_enable()
2436 value &= ~SOR_PLL1_TMDS_TERMADJ_MASK; in tegra_sor_hdmi_enable()
2437 value |= SOR_PLL1_LOADADJ(settings->loadadj); in tegra_sor_hdmi_enable()
2438 value |= SOR_PLL1_TMDS_TERMADJ(settings->tmds_termadj); in tegra_sor_hdmi_enable()
2439 value |= SOR_PLL1_TMDS_TERM; in tegra_sor_hdmi_enable()
2440 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2442 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2443 value &= ~SOR_PLL3_BG_TEMP_COEF_MASK; in tegra_sor_hdmi_enable()
2444 value &= ~SOR_PLL3_BG_VREF_LEVEL_MASK; in tegra_sor_hdmi_enable()
2445 value &= ~SOR_PLL3_AVDD10_LEVEL_MASK; in tegra_sor_hdmi_enable()
2446 value &= ~SOR_PLL3_AVDD14_LEVEL_MASK; in tegra_sor_hdmi_enable()
2447 value |= SOR_PLL3_BG_TEMP_COEF(settings->bg_temp_coef); in tegra_sor_hdmi_enable()
2448 value |= SOR_PLL3_BG_VREF_LEVEL(settings->bg_vref_level); in tegra_sor_hdmi_enable()
2449 value |= SOR_PLL3_AVDD10_LEVEL(settings->avdd10_level); in tegra_sor_hdmi_enable()
2450 value |= SOR_PLL3_AVDD14_LEVEL(settings->avdd14_level); in tegra_sor_hdmi_enable()
2451 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2453 value = settings->drive_current[3] << 24 | in tegra_sor_hdmi_enable()
2457 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2459 value = settings->preemphasis[3] << 24 | in tegra_sor_hdmi_enable()
2463 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2465 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2466 value &= ~SOR_DP_PADCTL_TX_PU_MASK; in tegra_sor_hdmi_enable()
2467 value |= SOR_DP_PADCTL_TX_PU_ENABLE; in tegra_sor_hdmi_enable()
2468 value |= SOR_DP_PADCTL_TX_PU(settings->tx_pu_value); in tegra_sor_hdmi_enable()
2469 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2471 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2472 value &= ~SOR_DP_PADCTL_SPAREPLL_MASK; in tegra_sor_hdmi_enable()
2473 value |= SOR_DP_PADCTL_SPAREPLL(settings->sparepll); in tegra_sor_hdmi_enable()
2474 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2477 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2478 value |= SOR_DP_PADCTL_PAD_CAL_PD; in tegra_sor_hdmi_enable()
2479 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2483 value = VSYNC_H_POSITION(1); in tegra_sor_hdmi_enable()
2484 tegra_dc_writel(dc, value, DC_DISP_DISP_TIMING_OPTIONS); in tegra_sor_hdmi_enable()
2487 value = tegra_dc_readl(dc, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2488 value &= ~DITHER_CONTROL_MASK; in tegra_sor_hdmi_enable()
2489 value &= ~BASE_COLOR_SIZE_MASK; in tegra_sor_hdmi_enable()
2493 value |= BASE_COLOR_SIZE_666; in tegra_sor_hdmi_enable()
2497 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2501 value |= BASE_COLOR_SIZE_101010; in tegra_sor_hdmi_enable()
2505 value |= BASE_COLOR_SIZE_121212; in tegra_sor_hdmi_enable()
2510 value |= BASE_COLOR_SIZE_888; in tegra_sor_hdmi_enable()
2514 tegra_dc_writel(dc, value, DC_DISP_DISP_COLOR_CONTROL); in tegra_sor_hdmi_enable()
2517 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2518 value &= ~SOR_STATE_ASY_OWNER_MASK; in tegra_sor_hdmi_enable()
2519 value |= SOR_STATE_ASY_OWNER(1 + dc->pipe); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2527 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2528 value &= ~SOR_HEAD_STATE_RANGECOMPRESS_MASK; in tegra_sor_hdmi_enable()
2529 value &= ~SOR_HEAD_STATE_DYNRANGE_MASK; in tegra_sor_hdmi_enable()
2530 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2533 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2534 value &= ~SOR_HEAD_STATE_COLORSPACE_MASK; in tegra_sor_hdmi_enable()
2535 value |= SOR_HEAD_STATE_COLORSPACE_RGB; in tegra_sor_hdmi_enable()
2536 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2543 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2544 value &= ~SOR_DP_SPARE_DISP_VIDEO_PREAMBLE; in tegra_sor_hdmi_enable()
2545 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2552 value = tegra_dc_readl(dc, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2555 value |= SOR_ENABLE(1) | SOR1_TIMING_CYA; in tegra_sor_hdmi_enable()
2557 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2559 tegra_dc_writel(dc, value, DC_DISP_DISP_WIN_OPTIONS); in tegra_sor_hdmi_enable()
2562 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2563 value &= ~PROTOCOL_MASK; in tegra_sor_hdmi_enable()
2564 value |= PROTOCOL_SINGLE_TMDS_A; in tegra_sor_hdmi_enable()
2565 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2910 u32 value; in tegra_sor_parse_dt() local
2914 err = of_property_read_u32(np, "nvidia,interface", &value); in tegra_sor_parse_dt()
2918 sor->index = value; in tegra_sor_parse_dt()