294 	unsigned int pll2;  member
1149 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_power_down()
1151 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_power_down()
1159 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_power_down()
1162 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_power_down()
1650 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1652 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1663 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1667 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1673 		value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1680 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1683 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1696 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1699 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1717 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1719 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1729 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1731 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1736 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
1738 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_edp_enable()
2234 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2236 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2249 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2251 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2255 	value = tegra_sor_readl(sor, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2258 	tegra_sor_writel(sor, value, sor->soc->regs->pll2);  in tegra_sor_hdmi_enable()
2795 	.pll2 = 0x19,
2820 	.pll2 = 0x19,
2864 	.pll2 = 0x165,