Lines Matching full:sor
29 #include "sor.h"
319 int (*probe)(struct tegra_sor *sor);
320 int (*remove)(struct tegra_sor *sor);
397 static inline u32 tegra_sor_readl(struct tegra_sor *sor, unsigned int offset) in tegra_sor_readl() argument
399 u32 value = readl(sor->regs + (offset << 2)); in tegra_sor_readl()
401 trace_sor_readl(sor->dev, offset, value); in tegra_sor_readl()
406 static inline void tegra_sor_writel(struct tegra_sor *sor, u32 value, in tegra_sor_writel() argument
409 trace_sor_writel(sor->dev, offset, value); in tegra_sor_writel()
410 writel(value, sor->regs + (offset << 2)); in tegra_sor_writel()
413 static int tegra_sor_set_parent_clock(struct tegra_sor *sor, struct clk *parent) in tegra_sor_set_parent_clock() argument
417 clk_disable_unprepare(sor->clk); in tegra_sor_set_parent_clock()
419 err = clk_set_parent(sor->clk_out, parent); in tegra_sor_set_parent_clock()
423 err = clk_prepare_enable(sor->clk); in tegra_sor_set_parent_clock()
432 struct tegra_sor *sor; member
447 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_set_parent() local
450 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
463 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_clk_sor_pad_set_parent()
471 struct tegra_sor *sor = pad->sor; in tegra_clk_sor_pad_get_parent() local
475 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_clk_sor_pad_get_parent()
497 static struct clk *tegra_clk_sor_pad_register(struct tegra_sor *sor, in tegra_clk_sor_pad_register() argument
504 pad = devm_kzalloc(sor->dev, sizeof(*pad), GFP_KERNEL); in tegra_clk_sor_pad_register()
508 pad->sor = sor; in tegra_clk_sor_pad_register()
518 clk = devm_clk_register(sor->dev, &pad->hw); in tegra_clk_sor_pad_register()
523 static int tegra_sor_dp_train_fast(struct tegra_sor *sor, in tegra_sor_dp_train_fast() argument
536 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_dp_train_fast()
542 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_dp_train_fast()
548 tegra_sor_writel(sor, value, SOR_LANE_POSTCURSOR0); in tegra_sor_dp_train_fast()
551 tegra_sor_writel(sor, 0, SOR_LVDS); in tegra_sor_dp_train_fast()
553 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
557 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
559 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
562 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
566 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
569 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_dp_train_fast()
571 err = drm_dp_aux_prepare(sor->aux, DP_SET_ANSI_8B10B); in tegra_sor_dp_train_fast()
582 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
586 err = drm_dp_aux_train(sor->aux, link, pattern); in tegra_sor_dp_train_fast()
590 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
594 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_dp_train_fast()
603 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
607 err = drm_dp_aux_train(sor->aux, link, pattern); in tegra_sor_dp_train_fast()
618 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_dp_train_fast()
622 err = drm_dp_aux_train(sor->aux, link, pattern); in tegra_sor_dp_train_fast()
629 static void tegra_sor_super_update(struct tegra_sor *sor) in tegra_sor_super_update() argument
631 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
632 tegra_sor_writel(sor, 1, SOR_SUPER_STATE0); in tegra_sor_super_update()
633 tegra_sor_writel(sor, 0, SOR_SUPER_STATE0); in tegra_sor_super_update()
636 static void tegra_sor_update(struct tegra_sor *sor) in tegra_sor_update() argument
638 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
639 tegra_sor_writel(sor, 1, SOR_STATE0); in tegra_sor_update()
640 tegra_sor_writel(sor, 0, SOR_STATE0); in tegra_sor_update()
643 static int tegra_sor_setup_pwm(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_setup_pwm() argument
647 value = tegra_sor_readl(sor, SOR_PWM_DIV); in tegra_sor_setup_pwm()
650 tegra_sor_writel(sor, value, SOR_PWM_DIV); in tegra_sor_setup_pwm()
652 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
657 tegra_sor_writel(sor, value, SOR_PWM_CTL); in tegra_sor_setup_pwm()
662 value = tegra_sor_readl(sor, SOR_PWM_CTL); in tegra_sor_setup_pwm()
672 static int tegra_sor_attach(struct tegra_sor *sor) in tegra_sor_attach() argument
677 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
680 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
681 tegra_sor_super_update(sor); in tegra_sor_attach()
684 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_attach()
686 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_attach()
687 tegra_sor_super_update(sor); in tegra_sor_attach()
692 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_attach()
702 static int tegra_sor_wakeup(struct tegra_sor *sor) in tegra_sor_wakeup() argument
710 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_wakeup()
722 static int tegra_sor_power_up(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_power_up() argument
726 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
728 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_up()
733 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_up()
758 static int tegra_sor_compute_params(struct tegra_sor *sor, in tegra_sor_compute_params() argument
826 static int tegra_sor_compute_config(struct tegra_sor *sor, in tegra_sor_compute_config() argument
855 if (tegra_sor_compute_params(sor, ¶ms, i)) in tegra_sor_compute_config()
874 dev_dbg(sor->dev, in tegra_sor_compute_config()
889 dev_err(sor->dev, in tegra_sor_compute_config()
894 dev_err(sor->dev, "watermark too high, forcing to %u\n", in tegra_sor_compute_config()
912 dev_dbg(sor->dev, "blank symbols: H:%u V:%u\n", config->hblank_symbols, in tegra_sor_compute_config()
918 static void tegra_sor_apply_config(struct tegra_sor *sor, in tegra_sor_apply_config() argument
923 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
926 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_apply_config()
928 value = tegra_sor_readl(sor, SOR_DP_CONFIG0); in tegra_sor_apply_config()
945 tegra_sor_writel(sor, value, SOR_DP_CONFIG0); in tegra_sor_apply_config()
947 value = tegra_sor_readl(sor, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
950 tegra_sor_writel(sor, value, SOR_DP_AUDIO_HBLANK_SYMBOLS); in tegra_sor_apply_config()
952 value = tegra_sor_readl(sor, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
955 tegra_sor_writel(sor, value, SOR_DP_AUDIO_VBLANK_SYMBOLS); in tegra_sor_apply_config()
958 static void tegra_sor_mode_set(struct tegra_sor *sor, in tegra_sor_mode_set() argument
962 struct tegra_dc *dc = to_tegra_dc(sor->output.encoder.crtc); in tegra_sor_mode_set()
966 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_mode_set()
1012 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_mode_set()
1020 tegra_sor_writel(sor, value, sor->soc->regs->head_state1 + dc->pipe); in tegra_sor_mode_set()
1027 tegra_sor_writel(sor, value, sor->soc->regs->head_state2 + dc->pipe); in tegra_sor_mode_set()
1034 tegra_sor_writel(sor, value, sor->soc->regs->head_state3 + dc->pipe); in tegra_sor_mode_set()
1041 tegra_sor_writel(sor, value, sor->soc->regs->head_state4 + dc->pipe); in tegra_sor_mode_set()
1044 tegra_sor_writel(sor, 0x001, sor->soc->regs->head_state5 + dc->pipe); in tegra_sor_mode_set()
1047 static int tegra_sor_detach(struct tegra_sor *sor) in tegra_sor_detach() argument
1052 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1054 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1055 tegra_sor_super_update(sor); in tegra_sor_detach()
1060 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_detach()
1069 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1071 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1072 tegra_sor_super_update(sor); in tegra_sor_detach()
1075 value = tegra_sor_readl(sor, SOR_SUPER_STATE1); in tegra_sor_detach()
1077 tegra_sor_writel(sor, value, SOR_SUPER_STATE1); in tegra_sor_detach()
1078 tegra_sor_super_update(sor); in tegra_sor_detach()
1083 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_detach()
1096 static int tegra_sor_power_down(struct tegra_sor *sor) in tegra_sor_power_down() argument
1101 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1104 tegra_sor_writel(sor, value, SOR_PWR); in tegra_sor_power_down()
1109 value = tegra_sor_readl(sor, SOR_PWR); in tegra_sor_power_down()
1120 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_power_down()
1122 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_power_down()
1126 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1129 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_power_down()
1134 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1139 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_power_down()
1149 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1151 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1155 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_power_down()
1157 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_power_down()
1159 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_power_down()
1162 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_power_down()
1169 static int tegra_sor_crc_wait(struct tegra_sor *sor, unsigned long timeout) in tegra_sor_crc_wait() argument
1176 value = tegra_sor_readl(sor, SOR_CRCA); in tegra_sor_crc_wait()
1189 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_crc() local
1190 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_crc()
1202 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_show_crc()
1204 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_show_crc()
1206 value = tegra_sor_readl(sor, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1208 tegra_sor_writel(sor, value, SOR_CRC_CNTRL); in tegra_sor_show_crc()
1210 value = tegra_sor_readl(sor, SOR_TEST); in tegra_sor_show_crc()
1212 tegra_sor_writel(sor, value, SOR_TEST); in tegra_sor_show_crc()
1214 err = tegra_sor_crc_wait(sor, 100); in tegra_sor_show_crc()
1218 tegra_sor_writel(sor, SOR_CRCA_RESET, SOR_CRCA); in tegra_sor_show_crc()
1219 value = tegra_sor_readl(sor, SOR_CRCB); in tegra_sor_show_crc()
1351 struct tegra_sor *sor = node->info_ent->data; in tegra_sor_show_regs() local
1352 struct drm_crtc *crtc = sor->output.encoder.crtc; in tegra_sor_show_regs()
1368 offset, tegra_sor_readl(sor, offset)); in tegra_sor_show_regs()
1387 struct tegra_sor *sor = to_sor(output); in tegra_sor_late_register() local
1390 sor->debugfs_files = kmemdup(debugfs_files, sizeof(debugfs_files), in tegra_sor_late_register()
1392 if (!sor->debugfs_files) in tegra_sor_late_register()
1396 sor->debugfs_files[i].data = sor; in tegra_sor_late_register()
1398 err = drm_debugfs_create_files(sor->debugfs_files, count, root, minor); in tegra_sor_late_register()
1405 kfree(sor->debugfs_files); in tegra_sor_late_register()
1406 sor->debugfs_files = NULL; in tegra_sor_late_register()
1415 struct tegra_sor *sor = to_sor(output); in tegra_sor_early_unregister() local
1417 drm_debugfs_remove_files(sor->debugfs_files, count, in tegra_sor_early_unregister()
1419 kfree(sor->debugfs_files); in tegra_sor_early_unregister()
1420 sor->debugfs_files = NULL; in tegra_sor_early_unregister()
1443 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_detect() local
1445 if (sor->aux) in tegra_sor_connector_detect()
1446 return drm_dp_aux_detect(sor->aux); in tegra_sor_connector_detect()
1480 struct tegra_sor *sor = to_sor(output); in tegra_sor_connector_get_modes() local
1483 if (sor->aux) in tegra_sor_connector_get_modes()
1484 drm_dp_aux_enable(sor->aux); in tegra_sor_connector_get_modes()
1488 if (sor->aux) in tegra_sor_connector_get_modes()
1489 drm_dp_aux_disable(sor->aux); in tegra_sor_connector_get_modes()
1514 struct tegra_sor *sor = to_sor(output); in tegra_sor_edp_disable() local
1521 err = tegra_sor_detach(sor); in tegra_sor_edp_disable()
1523 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_edp_disable()
1525 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_edp_disable()
1526 tegra_sor_update(sor); in tegra_sor_edp_disable()
1540 err = tegra_sor_power_down(sor); in tegra_sor_edp_disable()
1542 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_edp_disable()
1544 if (sor->aux) { in tegra_sor_edp_disable()
1545 err = drm_dp_aux_disable(sor->aux); in tegra_sor_edp_disable()
1547 dev_err(sor->dev, "failed to disable DP: %d\n", err); in tegra_sor_edp_disable()
1550 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_edp_disable()
1552 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_edp_disable()
1557 pm_runtime_put(sor->dev); in tegra_sor_edp_disable()
1607 struct tegra_sor *sor = to_sor(output); in tegra_sor_edp_enable() local
1618 pm_runtime_get_sync(sor->dev); in tegra_sor_edp_enable()
1623 err = drm_dp_aux_enable(sor->aux); in tegra_sor_edp_enable()
1625 dev_err(sor->dev, "failed to enable DP: %d\n", err); in tegra_sor_edp_enable()
1627 err = drm_dp_link_probe(sor->aux, &link); in tegra_sor_edp_enable()
1629 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); in tegra_sor_edp_enable()
1634 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_edp_enable()
1636 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_edp_enable()
1641 err = tegra_sor_compute_config(sor, mode, &config, &link); in tegra_sor_edp_enable()
1643 dev_err(sor->dev, "failed to compute configuration: %d\n", err); in tegra_sor_edp_enable()
1645 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1648 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1650 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1652 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1655 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1657 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_edp_enable()
1661 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1663 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1667 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1670 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_edp_enable()
1673 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1680 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1683 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1690 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1693 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1696 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1699 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1701 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1703 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1705 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1707 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1710 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_edp_enable()
1712 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_edp_enable()
1717 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1719 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1724 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1727 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_edp_enable()
1729 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1731 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1736 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1738 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_edp_enable()
1742 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_edp_enable()
1745 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_edp_enable()
1746 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_edp_enable()
1749 err = tegra_sor_set_parent_clock(sor, sor->clk_dp); in tegra_sor_edp_enable()
1751 dev_err(sor->dev, "failed to set parent clock: %d\n", err); in tegra_sor_edp_enable()
1754 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1771 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1773 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1776 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1781 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1784 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_edp_enable()
1792 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1795 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1797 tegra_sor_apply_config(sor, &config); in tegra_sor_edp_enable()
1800 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1803 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1812 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1815 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1817 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_edp_enable()
1819 err = drm_dp_link_probe(sor->aux, &link); in tegra_sor_edp_enable()
1821 dev_err(sor->dev, "failed to probe eDP link: %d\n", err); in tegra_sor_edp_enable()
1823 err = drm_dp_link_power_up(sor->aux, &link); in tegra_sor_edp_enable()
1825 dev_err(sor->dev, "failed to power up eDP link: %d\n", err); in tegra_sor_edp_enable()
1827 err = drm_dp_link_configure(sor->aux, &link); in tegra_sor_edp_enable()
1829 dev_err(sor->dev, "failed to configure eDP link: %d\n", err); in tegra_sor_edp_enable()
1834 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1837 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_edp_enable()
1839 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1846 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_edp_enable()
1857 tegra_sor_writel(sor, value, SOR_DP_TPG); in tegra_sor_edp_enable()
1859 err = tegra_sor_dp_train_fast(sor, &link); in tegra_sor_edp_enable()
1861 dev_err(sor->dev, "DP fast link training failed: %d\n", err); in tegra_sor_edp_enable()
1863 dev_dbg(sor->dev, "fast link training succeeded\n"); in tegra_sor_edp_enable()
1865 err = tegra_sor_power_up(sor, 250); in tegra_sor_edp_enable()
1867 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_edp_enable()
1872 tegra_sor_writel(sor, value, SOR_CSTM); in tegra_sor_edp_enable()
1875 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_edp_enable()
1878 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_edp_enable()
1880 tegra_sor_mode_set(sor, mode, state); in tegra_sor_edp_enable()
1883 err = tegra_sor_setup_pwm(sor, 250); in tegra_sor_edp_enable()
1885 dev_err(sor->dev, "failed to setup PWM: %d\n", err); in tegra_sor_edp_enable()
1887 tegra_sor_update(sor); in tegra_sor_edp_enable()
1895 err = tegra_sor_attach(sor); in tegra_sor_edp_enable()
1897 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_edp_enable()
1899 err = tegra_sor_wakeup(sor); in tegra_sor_edp_enable()
1901 dev_err(sor->dev, "failed to enable DC: %d\n", err); in tegra_sor_edp_enable()
1916 struct tegra_sor *sor = to_sor(output); in tegra_sor_encoder_atomic_check() local
1923 * For HBR2 modes, the SOR brick needs to use the x20 multiplier, so in tegra_sor_encoder_atomic_check()
1934 err = tegra_dc_state_setup_clock(dc, crtc_state, sor->clk_parent, in tegra_sor_encoder_atomic_check()
1973 static void tegra_sor_hdmi_write_infopack(struct tegra_sor *sor, in tegra_sor_hdmi_write_infopack() argument
1995 dev_err(sor->dev, "unsupported infoframe type: %02x\n", in tegra_sor_hdmi_write_infopack()
2003 tegra_sor_writel(sor, value, offset); in tegra_sor_hdmi_write_infopack()
2015 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2020 tegra_sor_writel(sor, value, offset++); in tegra_sor_hdmi_write_infopack()
2025 tegra_sor_hdmi_setup_avi_infoframe(struct tegra_sor *sor, in tegra_sor_hdmi_setup_avi_infoframe() argument
2034 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2038 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2042 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
2048 dev_err(sor->dev, "failed to pack AVI infoframe: %d\n", err); in tegra_sor_hdmi_setup_avi_infoframe()
2052 tegra_sor_hdmi_write_infopack(sor, buffer, err); in tegra_sor_hdmi_setup_avi_infoframe()
2055 value = tegra_sor_readl(sor, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2058 tegra_sor_writel(sor, value, SOR_HDMI_AVI_INFOFRAME_CTRL); in tegra_sor_hdmi_setup_avi_infoframe()
2063 static void tegra_sor_hdmi_disable_audio_infoframe(struct tegra_sor *sor) in tegra_sor_hdmi_disable_audio_infoframe() argument
2067 value = tegra_sor_readl(sor, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2069 tegra_sor_writel(sor, value, SOR_HDMI_AUDIO_INFOFRAME_CTRL); in tegra_sor_hdmi_disable_audio_infoframe()
2073 tegra_sor_hdmi_find_settings(struct tegra_sor *sor, unsigned long frequency) in tegra_sor_hdmi_find_settings() argument
2077 for (i = 0; i < sor->num_settings; i++) in tegra_sor_hdmi_find_settings()
2078 if (frequency <= sor->settings[i].frequency) in tegra_sor_hdmi_find_settings()
2079 return &sor->settings[i]; in tegra_sor_hdmi_find_settings()
2084 static void tegra_sor_hdmi_disable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_disable_scrambling() argument
2088 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2091 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_disable_scrambling()
2094 static void tegra_sor_hdmi_scdc_disable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_disable() argument
2096 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_disable()
2101 tegra_sor_hdmi_disable_scrambling(sor); in tegra_sor_hdmi_scdc_disable()
2104 static void tegra_sor_hdmi_scdc_stop(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_stop() argument
2106 if (sor->scdc_enabled) { in tegra_sor_hdmi_scdc_stop()
2107 cancel_delayed_work_sync(&sor->scdc); in tegra_sor_hdmi_scdc_stop()
2108 tegra_sor_hdmi_scdc_disable(sor); in tegra_sor_hdmi_scdc_stop()
2112 static void tegra_sor_hdmi_enable_scrambling(struct tegra_sor *sor) in tegra_sor_hdmi_enable_scrambling() argument
2116 value = tegra_sor_readl(sor, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2119 tegra_sor_writel(sor, value, SOR_HDMI2_CTRL); in tegra_sor_hdmi_enable_scrambling()
2122 static void tegra_sor_hdmi_scdc_enable(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_enable() argument
2124 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_enable()
2129 tegra_sor_hdmi_enable_scrambling(sor); in tegra_sor_hdmi_scdc_enable()
2134 struct tegra_sor *sor = container_of(work, struct tegra_sor, scdc.work); in tegra_sor_hdmi_scdc_work() local
2135 struct i2c_adapter *ddc = sor->output.ddc; in tegra_sor_hdmi_scdc_work()
2139 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_work()
2142 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_work()
2145 static void tegra_sor_hdmi_scdc_start(struct tegra_sor *sor) in tegra_sor_hdmi_scdc_start() argument
2147 struct drm_scdc *scdc = &sor->output.connector.display_info.hdmi.scdc; in tegra_sor_hdmi_scdc_start()
2150 mode = &sor->output.encoder.crtc->state->adjusted_mode; in tegra_sor_hdmi_scdc_start()
2153 schedule_delayed_work(&sor->scdc, msecs_to_jiffies(5000)); in tegra_sor_hdmi_scdc_start()
2154 tegra_sor_hdmi_scdc_enable(sor); in tegra_sor_hdmi_scdc_start()
2155 sor->scdc_enabled = true; in tegra_sor_hdmi_scdc_start()
2163 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_disable() local
2167 tegra_sor_hdmi_scdc_stop(sor); in tegra_sor_hdmi_disable()
2169 err = tegra_sor_detach(sor); in tegra_sor_hdmi_disable()
2171 dev_err(sor->dev, "failed to detach SOR: %d\n", err); in tegra_sor_hdmi_disable()
2173 tegra_sor_writel(sor, 0, SOR_STATE1); in tegra_sor_hdmi_disable()
2174 tegra_sor_update(sor); in tegra_sor_hdmi_disable()
2176 /* disable display to SOR clock */ in tegra_sor_hdmi_disable()
2179 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_disable()
2182 value &= ~SOR_ENABLE(sor->index); in tegra_sor_hdmi_disable()
2188 err = tegra_sor_power_down(sor); in tegra_sor_hdmi_disable()
2190 dev_err(sor->dev, "failed to power down SOR: %d\n", err); in tegra_sor_hdmi_disable()
2192 err = tegra_io_pad_power_disable(sor->pad); in tegra_sor_hdmi_disable()
2194 dev_err(sor->dev, "failed to power off I/O pad: %d\n", err); in tegra_sor_hdmi_disable()
2196 pm_runtime_put(sor->dev); in tegra_sor_hdmi_disable()
2205 struct tegra_sor *sor = to_sor(output); in tegra_sor_hdmi_enable() local
2217 pm_runtime_get_sync(sor->dev); in tegra_sor_hdmi_enable()
2220 err = tegra_sor_set_parent_clock(sor, sor->clk_safe); in tegra_sor_hdmi_enable()
2222 dev_err(sor->dev, "failed to set safe parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2226 div = clk_get_rate(sor->clk) / 1000000 * 4; in tegra_sor_hdmi_enable()
2228 err = tegra_io_pad_power_enable(sor->pad); in tegra_sor_hdmi_enable()
2230 dev_err(sor->dev, "failed to power on I/O pad: %d\n", err); in tegra_sor_hdmi_enable()
2234 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2236 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2240 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2242 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2244 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2247 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2249 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2251 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2255 value = tegra_sor_readl(sor, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2258 tegra_sor_writel(sor, value, sor->soc->regs->pll2); in tegra_sor_hdmi_enable()
2262 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2265 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2268 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2277 tegra_sor_writel(sor, value, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2280 value = tegra_sor_readl(sor, SOR_LANE_SEQ_CTL); in tegra_sor_hdmi_enable()
2287 value = tegra_sor_readl(sor, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2300 tegra_sor_writel(sor, value, SOR_CLK_CNTRL); in tegra_sor_hdmi_enable()
2302 /* SOR pad PLL stabilization time */ in tegra_sor_hdmi_enable()
2305 value = tegra_sor_readl(sor, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2308 tegra_sor_writel(sor, value, SOR_DP_LINKCTL0); in tegra_sor_hdmi_enable()
2310 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2315 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2319 tegra_sor_writel(sor, value, SOR_SEQ_CTL); in tegra_sor_hdmi_enable()
2323 tegra_sor_writel(sor, value, SOR_SEQ_INST(0)); in tegra_sor_hdmi_enable()
2324 tegra_sor_writel(sor, value, SOR_SEQ_INST(8)); in tegra_sor_hdmi_enable()
2326 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2329 tegra_sor_writel(sor, value, SOR_REFCLK); in tegra_sor_hdmi_enable()
2334 value |= SOR_XBAR_CTRL_LINK0_XSEL(i, sor->soc->xbar_cfg[i]) | in tegra_sor_hdmi_enable()
2337 tegra_sor_writel(sor, 0x00000000, SOR_XBAR_POL); in tegra_sor_hdmi_enable()
2338 tegra_sor_writel(sor, value, SOR_XBAR_CTRL); in tegra_sor_hdmi_enable()
2341 err = clk_set_parent(sor->clk, sor->clk_parent); in tegra_sor_hdmi_enable()
2343 dev_err(sor->dev, "failed to set parent clock: %d\n", err); in tegra_sor_hdmi_enable()
2347 err = tegra_sor_set_parent_clock(sor, sor->clk_pad); in tegra_sor_hdmi_enable()
2349 dev_err(sor->dev, "failed to set pad clock: %d\n", err); in tegra_sor_hdmi_enable()
2354 rate = clk_get_rate(sor->clk_parent); in tegra_sor_hdmi_enable()
2361 clk_set_rate(sor->clk, rate); in tegra_sor_hdmi_enable()
2363 if (!sor->soc->has_nvdisplay) { in tegra_sor_hdmi_enable()
2370 tegra_sor_writel(sor, value, SOR_INPUT_CONTROL); in tegra_sor_hdmi_enable()
2377 tegra_sor_writel(sor, value, SOR_HDMI_CTRL); in tegra_sor_hdmi_enable()
2398 err = tegra_sor_hdmi_setup_avi_infoframe(sor, mode); in tegra_sor_hdmi_enable()
2400 dev_err(sor->dev, "failed to setup AVI infoframe: %d\n", err); in tegra_sor_hdmi_enable()
2403 tegra_sor_hdmi_disable_audio_infoframe(sor); in tegra_sor_hdmi_enable()
2406 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2409 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2412 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2414 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2417 settings = tegra_sor_hdmi_find_settings(sor, mode->clock * 1000); in tegra_sor_hdmi_enable()
2419 dev_err(sor->dev, "no settings for pixel clock %d Hz\n", in tegra_sor_hdmi_enable()
2424 value = tegra_sor_readl(sor, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2431 tegra_sor_writel(sor, value, sor->soc->regs->pll0); in tegra_sor_hdmi_enable()
2434 value = tegra_sor_readl(sor, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2440 tegra_sor_writel(sor, value, sor->soc->regs->pll1); in tegra_sor_hdmi_enable()
2442 value = tegra_sor_readl(sor, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2451 tegra_sor_writel(sor, value, sor->soc->regs->pll3); in tegra_sor_hdmi_enable()
2457 tegra_sor_writel(sor, value, SOR_LANE_DRIVE_CURRENT0); in tegra_sor_hdmi_enable()
2463 tegra_sor_writel(sor, value, SOR_LANE_PREEMPHASIS0); in tegra_sor_hdmi_enable()
2465 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2469 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2471 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2474 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl2); in tegra_sor_hdmi_enable()
2477 value = tegra_sor_readl(sor, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2479 tegra_sor_writel(sor, value, sor->soc->regs->dp_padctl0); in tegra_sor_hdmi_enable()
2517 value = tegra_sor_readl(sor, SOR_STATE1); in tegra_sor_hdmi_enable()
2520 tegra_sor_writel(sor, value, SOR_STATE1); in tegra_sor_hdmi_enable()
2522 err = tegra_sor_power_up(sor, 250); in tegra_sor_hdmi_enable()
2524 dev_err(sor->dev, "failed to power up SOR: %d\n", err); in tegra_sor_hdmi_enable()
2527 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2530 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2533 value = tegra_sor_readl(sor, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2536 tegra_sor_writel(sor, value, sor->soc->regs->head_state0 + dc->pipe); in tegra_sor_hdmi_enable()
2538 tegra_sor_mode_set(sor, mode, state); in tegra_sor_hdmi_enable()
2540 tegra_sor_update(sor); in tegra_sor_hdmi_enable()
2542 /* program preamble timing in SOR (XXX) */ in tegra_sor_hdmi_enable()
2543 value = tegra_sor_readl(sor, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2545 tegra_sor_writel(sor, value, SOR_DP_SPARE0); in tegra_sor_hdmi_enable()
2547 err = tegra_sor_attach(sor); in tegra_sor_hdmi_enable()
2549 dev_err(sor->dev, "failed to attach SOR: %d\n", err); in tegra_sor_hdmi_enable()
2551 /* enable display to SOR clock and generate HDMI preamble */ in tegra_sor_hdmi_enable()
2554 if (!sor->soc->has_nvdisplay) in tegra_sor_hdmi_enable()
2557 value |= SOR_ENABLE(sor->index); in tegra_sor_hdmi_enable()
2562 value = tegra_dc_readl(dc, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2565 tegra_dc_writel(dc, value, DC_DISP_CORE_SOR_SET_CONTROL(sor->index)); in tegra_sor_hdmi_enable()
2570 err = tegra_sor_wakeup(sor); in tegra_sor_hdmi_enable()
2572 dev_err(sor->dev, "failed to wakeup SOR: %d\n", err); in tegra_sor_hdmi_enable()
2574 tegra_sor_hdmi_scdc_start(sor); in tegra_sor_hdmi_enable()
2587 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_init() local
2592 if (!sor->aux) { in tegra_sor_init()
2593 if (sor->soc->supports_hdmi) { in tegra_sor_init()
2597 } else if (sor->soc->supports_lvds) { in tegra_sor_init()
2602 if (sor->soc->supports_edp) { in tegra_sor_init()
2606 } else if (sor->soc->supports_dp) { in tegra_sor_init()
2612 sor->output.dev = sor->dev; in tegra_sor_init()
2614 drm_connector_init(drm, &sor->output.connector, in tegra_sor_init()
2617 drm_connector_helper_add(&sor->output.connector, in tegra_sor_init()
2619 sor->output.connector.dpms = DRM_MODE_DPMS_OFF; in tegra_sor_init()
2621 drm_encoder_init(drm, &sor->output.encoder, &tegra_sor_encoder_funcs, in tegra_sor_init()
2623 drm_encoder_helper_add(&sor->output.encoder, helpers); in tegra_sor_init()
2625 drm_connector_attach_encoder(&sor->output.connector, in tegra_sor_init()
2626 &sor->output.encoder); in tegra_sor_init()
2627 drm_connector_register(&sor->output.connector); in tegra_sor_init()
2629 err = tegra_output_init(drm, &sor->output); in tegra_sor_init()
2635 tegra_output_find_possible_crtcs(&sor->output, drm); in tegra_sor_init()
2637 if (sor->aux) { in tegra_sor_init()
2638 err = drm_dp_aux_attach(sor->aux, &sor->output); in tegra_sor_init()
2640 dev_err(sor->dev, "failed to attach DP: %d\n", err); in tegra_sor_init()
2649 if (sor->rst) { in tegra_sor_init()
2650 err = reset_control_assert(sor->rst); in tegra_sor_init()
2652 dev_err(sor->dev, "failed to assert SOR reset: %d\n", in tegra_sor_init()
2658 err = clk_prepare_enable(sor->clk); in tegra_sor_init()
2660 dev_err(sor->dev, "failed to enable clock: %d\n", err); in tegra_sor_init()
2666 if (sor->rst) { in tegra_sor_init()
2667 err = reset_control_deassert(sor->rst); in tegra_sor_init()
2669 dev_err(sor->dev, "failed to deassert SOR reset: %d\n", in tegra_sor_init()
2675 err = clk_prepare_enable(sor->clk_safe); in tegra_sor_init()
2679 err = clk_prepare_enable(sor->clk_dp); in tegra_sor_init()
2688 struct tegra_sor *sor = host1x_client_to_sor(client); in tegra_sor_exit() local
2691 tegra_output_exit(&sor->output); in tegra_sor_exit()
2693 if (sor->aux) { in tegra_sor_exit()
2694 err = drm_dp_aux_detach(sor->aux); in tegra_sor_exit()
2696 dev_err(sor->dev, "failed to detach DP: %d\n", err); in tegra_sor_exit()
2701 clk_disable_unprepare(sor->clk_safe); in tegra_sor_exit()
2702 clk_disable_unprepare(sor->clk_dp); in tegra_sor_exit()
2703 clk_disable_unprepare(sor->clk); in tegra_sor_exit()
2717 static int tegra_sor_hdmi_probe(struct tegra_sor *sor) in tegra_sor_hdmi_probe() argument
2721 sor->avdd_io_supply = devm_regulator_get(sor->dev, "avdd-io"); in tegra_sor_hdmi_probe()
2722 if (IS_ERR(sor->avdd_io_supply)) { in tegra_sor_hdmi_probe()
2723 dev_err(sor->dev, "cannot get AVDD I/O supply: %ld\n", in tegra_sor_hdmi_probe()
2724 PTR_ERR(sor->avdd_io_supply)); in tegra_sor_hdmi_probe()
2725 return PTR_ERR(sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2728 err = regulator_enable(sor->avdd_io_supply); in tegra_sor_hdmi_probe()
2730 dev_err(sor->dev, "failed to enable AVDD I/O supply: %d\n", in tegra_sor_hdmi_probe()
2735 sor->vdd_pll_supply = devm_regulator_get(sor->dev, "vdd-pll"); in tegra_sor_hdmi_probe()
2736 if (IS_ERR(sor->vdd_pll_supply)) { in tegra_sor_hdmi_probe()
2737 dev_err(sor->dev, "cannot get VDD PLL supply: %ld\n", in tegra_sor_hdmi_probe()
2738 PTR_ERR(sor->vdd_pll_supply)); in tegra_sor_hdmi_probe()
2739 return PTR_ERR(sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2742 err = regulator_enable(sor->vdd_pll_supply); in tegra_sor_hdmi_probe()
2744 dev_err(sor->dev, "failed to enable VDD PLL supply: %d\n", in tegra_sor_hdmi_probe()
2749 sor->hdmi_supply = devm_regulator_get(sor->dev, "hdmi"); in tegra_sor_hdmi_probe()
2750 if (IS_ERR(sor->hdmi_supply)) { in tegra_sor_hdmi_probe()
2751 dev_err(sor->dev, "cannot get HDMI supply: %ld\n", in tegra_sor_hdmi_probe()
2752 PTR_ERR(sor->hdmi_supply)); in tegra_sor_hdmi_probe()
2753 return PTR_ERR(sor->hdmi_supply); in tegra_sor_hdmi_probe()
2756 err = regulator_enable(sor->hdmi_supply); in tegra_sor_hdmi_probe()
2758 dev_err(sor->dev, "failed to enable HDMI supply: %d\n", err); in tegra_sor_hdmi_probe()
2762 INIT_DELAYED_WORK(&sor->scdc, tegra_sor_hdmi_scdc_work); in tegra_sor_hdmi_probe()
2767 static int tegra_sor_hdmi_remove(struct tegra_sor *sor) in tegra_sor_hdmi_remove() argument
2769 regulator_disable(sor->hdmi_supply); in tegra_sor_hdmi_remove()
2770 regulator_disable(sor->vdd_pll_supply); in tegra_sor_hdmi_remove()
2771 regulator_disable(sor->avdd_io_supply); in tegra_sor_hdmi_remove()
2899 { .compatible = "nvidia,tegra186-sor", .data = &tegra186_sor },
2901 { .compatible = "nvidia,tegra210-sor", .data = &tegra210_sor },
2902 { .compatible = "nvidia,tegra124-sor", .data = &tegra124_sor },
2907 static int tegra_sor_parse_dt(struct tegra_sor *sor) in tegra_sor_parse_dt() argument
2909 struct device_node *np = sor->dev->of_node; in tegra_sor_parse_dt()
2913 if (sor->soc->has_nvdisplay) { in tegra_sor_parse_dt()
2918 sor->index = value; in tegra_sor_parse_dt()
2924 sor->pad = TEGRA_IO_PAD_HDMI_DP0 + sor->index; in tegra_sor_parse_dt()
2926 if (sor->soc->supports_edp) in tegra_sor_parse_dt()
2927 sor->index = 0; in tegra_sor_parse_dt()
2929 sor->index = 1; in tegra_sor_parse_dt()
2938 struct tegra_sor *sor; in tegra_sor_probe() local
2942 sor = devm_kzalloc(&pdev->dev, sizeof(*sor), GFP_KERNEL); in tegra_sor_probe()
2943 if (!sor) in tegra_sor_probe()
2946 sor->soc = of_device_get_match_data(&pdev->dev); in tegra_sor_probe()
2947 sor->output.dev = sor->dev = &pdev->dev; in tegra_sor_probe()
2949 sor->settings = devm_kmemdup(&pdev->dev, sor->soc->settings, in tegra_sor_probe()
2950 sor->soc->num_settings * in tegra_sor_probe()
2951 sizeof(*sor->settings), in tegra_sor_probe()
2953 if (!sor->settings) in tegra_sor_probe()
2956 sor->num_settings = sor->soc->num_settings; in tegra_sor_probe()
2960 sor->aux = drm_dp_aux_find_by_of_node(np); in tegra_sor_probe()
2963 if (!sor->aux) in tegra_sor_probe()
2967 if (!sor->aux) { in tegra_sor_probe()
2968 if (sor->soc->supports_hdmi) { in tegra_sor_probe()
2969 sor->ops = &tegra_sor_hdmi_ops; in tegra_sor_probe()
2970 sor->pad = TEGRA_IO_PAD_HDMI; in tegra_sor_probe()
2971 } else if (sor->soc->supports_lvds) { in tegra_sor_probe()
2979 if (sor->soc->supports_edp) { in tegra_sor_probe()
2980 sor->ops = &tegra_sor_edp_ops; in tegra_sor_probe()
2981 sor->pad = TEGRA_IO_PAD_LVDS; in tegra_sor_probe()
2982 } else if (sor->soc->supports_dp) { in tegra_sor_probe()
2991 err = tegra_sor_parse_dt(sor); in tegra_sor_probe()
2995 err = tegra_output_probe(&sor->output); in tegra_sor_probe()
3001 if (sor->ops && sor->ops->probe) { in tegra_sor_probe()
3002 err = sor->ops->probe(sor); in tegra_sor_probe()
3005 sor->ops->name, err); in tegra_sor_probe()
3011 sor->regs = devm_ioremap_resource(&pdev->dev, regs); in tegra_sor_probe()
3012 if (IS_ERR(sor->regs)) { in tegra_sor_probe()
3013 err = PTR_ERR(sor->regs); in tegra_sor_probe()
3018 sor->rst = devm_reset_control_get(&pdev->dev, "sor"); in tegra_sor_probe()
3019 if (IS_ERR(sor->rst)) { in tegra_sor_probe()
3020 err = PTR_ERR(sor->rst); in tegra_sor_probe()
3027 sor->clk = devm_clk_get(&pdev->dev, NULL); in tegra_sor_probe()
3028 if (IS_ERR(sor->clk)) { in tegra_sor_probe()
3029 err = PTR_ERR(sor->clk); in tegra_sor_probe()
3034 if (sor->soc->supports_hdmi || sor->soc->supports_dp) { in tegra_sor_probe()
3048 sor->clk_out = devm_clk_get(&pdev->dev, name); in tegra_sor_probe()
3049 if (IS_ERR(sor->clk_out)) { in tegra_sor_probe()
3050 err = PTR_ERR(sor->clk_out); in tegra_sor_probe()
3051 dev_err(sor->dev, "failed to get %s clock: %d\n", in tegra_sor_probe()
3057 sor->clk_out = sor->clk; in tegra_sor_probe()
3060 sor->clk_parent = devm_clk_get(&pdev->dev, "parent"); in tegra_sor_probe()
3061 if (IS_ERR(sor->clk_parent)) { in tegra_sor_probe()
3062 err = PTR_ERR(sor->clk_parent); in tegra_sor_probe()
3067 sor->clk_safe = devm_clk_get(&pdev->dev, "safe"); in tegra_sor_probe()
3068 if (IS_ERR(sor->clk_safe)) { in tegra_sor_probe()
3069 err = PTR_ERR(sor->clk_safe); in tegra_sor_probe()
3074 sor->clk_dp = devm_clk_get(&pdev->dev, "dp"); in tegra_sor_probe()
3075 if (IS_ERR(sor->clk_dp)) { in tegra_sor_probe()
3076 err = PTR_ERR(sor->clk_dp); in tegra_sor_probe()
3085 sor->clk_pad = devm_clk_get(&pdev->dev, "pad"); in tegra_sor_probe()
3086 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3087 if (sor->clk_pad != ERR_PTR(-ENOENT)) { in tegra_sor_probe()
3088 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3097 sor->clk_pad = NULL; in tegra_sor_probe()
3101 * The bootloader may have set up the SOR such that it's module clock in tegra_sor_probe()
3103 * without properly having set up other bits of the SOR. in tegra_sor_probe()
3105 err = clk_set_parent(sor->clk_out, sor->clk_safe); in tegra_sor_probe()
3111 platform_set_drvdata(pdev, sor); in tegra_sor_probe()
3118 if (!sor->clk_pad) { in tegra_sor_probe()
3126 sor->clk_pad = tegra_clk_sor_pad_register(sor, in tegra_sor_probe()
3131 if (IS_ERR(sor->clk_pad)) { in tegra_sor_probe()
3132 err = PTR_ERR(sor->clk_pad); in tegra_sor_probe()
3133 dev_err(&pdev->dev, "failed to register SOR pad clock: %d\n", in tegra_sor_probe()
3138 INIT_LIST_HEAD(&sor->client.list); in tegra_sor_probe()
3139 sor->client.ops = &sor_client_ops; in tegra_sor_probe()
3140 sor->client.dev = &pdev->dev; in tegra_sor_probe()
3142 err = host1x_client_register(&sor->client); in tegra_sor_probe()
3152 if (sor->ops && sor->ops->remove) in tegra_sor_probe()
3153 sor->ops->remove(sor); in tegra_sor_probe()
3155 tegra_output_remove(&sor->output); in tegra_sor_probe()
3161 struct tegra_sor *sor = platform_get_drvdata(pdev); in tegra_sor_remove() local
3166 err = host1x_client_unregister(&sor->client); in tegra_sor_remove()
3173 if (sor->ops && sor->ops->remove) { in tegra_sor_remove()
3174 err = sor->ops->remove(sor); in tegra_sor_remove()
3176 dev_err(&pdev->dev, "failed to remove SOR: %d\n", err); in tegra_sor_remove()
3179 tegra_output_remove(&sor->output); in tegra_sor_remove()
3187 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_suspend() local
3190 if (sor->rst) { in tegra_sor_suspend()
3191 err = reset_control_assert(sor->rst); in tegra_sor_suspend()
3200 clk_disable_unprepare(sor->clk); in tegra_sor_suspend()
3207 struct tegra_sor *sor = dev_get_drvdata(dev); in tegra_sor_resume() local
3210 err = clk_prepare_enable(sor->clk); in tegra_sor_resume()
3218 if (sor->rst) { in tegra_sor_resume()
3219 err = reset_control_deassert(sor->rst); in tegra_sor_resume()
3222 clk_disable_unprepare(sor->clk); in tegra_sor_resume()
3237 .name = "tegra-sor",