Lines Matching full:dsi
20 * BCM2835 contains two DSI modules, DSI0 and DSI1. DSI0 is a
21 * single-lane DSI controller, while DSI1 is a more modern 4-lane DSI
501 /* General DSI hardware state. */
519 /* DSI channel for the panel we're connected to. */
526 /* Input clock from CPRMAN to the digital PHY, for the DSI
531 /* Input clock to the analog PHY, used to generate the DSI bit
536 /* HS Clocks generated within the DSI analog PHY. */
553 dsi_dma_workaround_write(struct vc4_dsi *dsi, u32 offset, u32 val) in dsi_dma_workaround_write() argument
555 struct dma_chan *chan = dsi->reg_dma_chan; in dsi_dma_workaround_write()
562 writel(val, dsi->regs + offset); in dsi_dma_workaround_write()
566 *dsi->reg_dma_mem = val; in dsi_dma_workaround_write()
569 dsi->reg_paddr + offset, in dsi_dma_workaround_write()
570 dsi->reg_dma_paddr, in dsi_dma_workaround_write()
588 #define DSI_READ(offset) readl(dsi->regs + (offset))
589 #define DSI_WRITE(offset, val) dsi_dma_workaround_write(dsi, offset, val)
591 DSI_READ(dsi->port ? DSI1_##offset : DSI0_##offset)
593 DSI_WRITE(dsi->port ? DSI1_##offset : DSI0_##offset, val)
594 #define DSI_PORT_BIT(bit) (dsi->port ? DSI1_##bit : DSI0_##bit)
596 /* VC4 DSI encoder KMS struct */
599 struct vc4_dsi *dsi; member
665 static void vc4_dsi_dump_regs(struct vc4_dsi *dsi) in vc4_dsi_dump_regs() argument
669 if (dsi->port == 0) { in vc4_dsi_dump_regs()
691 struct vc4_dsi *dsi = (dsi_index == 1 ? vc4->dsi1 : NULL); in vc4_dsi_debugfs_regs() local
694 if (!dsi) in vc4_dsi_debugfs_regs()
697 if (dsi->port == 0) { in vc4_dsi_debugfs_regs()
724 static void vc4_dsi_latch_ulps(struct vc4_dsi *dsi, bool latch) in vc4_dsi_latch_ulps() argument
737 static void vc4_dsi_ulps(struct vc4_dsi *dsi, bool ulps) in vc4_dsi_ulps() argument
739 bool non_continuous = dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS; in vc4_dsi_ulps()
742 (dsi->lanes > 1 ? DSI_PHYC_DLANE1_ULPS : 0) | in vc4_dsi_ulps()
743 (dsi->lanes > 2 ? DSI_PHYC_DLANE2_ULPS : 0) | in vc4_dsi_ulps()
744 (dsi->lanes > 3 ? DSI_PHYC_DLANE3_ULPS : 0)); in vc4_dsi_ulps()
747 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_ULPS : 0) | in vc4_dsi_ulps()
748 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_ULPS : 0) | in vc4_dsi_ulps()
749 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_ULPS : 0)); in vc4_dsi_ulps()
752 (dsi->lanes > 1 ? DSI1_STAT_PHY_D1_STOP : 0) | in vc4_dsi_ulps()
753 (dsi->lanes > 2 ? DSI1_STAT_PHY_D2_STOP : 0) | in vc4_dsi_ulps()
754 (dsi->lanes > 3 ? DSI1_STAT_PHY_D3_STOP : 0)); in vc4_dsi_ulps()
766 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
767 "Timeout waiting for DSI ULPS entry: STAT 0x%08x", in vc4_dsi_ulps()
770 vc4_dsi_latch_ulps(dsi, false); in vc4_dsi_ulps()
774 /* The DSI module can't be disabled while the module is in vc4_dsi_ulps()
779 vc4_dsi_latch_ulps(dsi, ulps); in vc4_dsi_ulps()
785 dev_warn(&dsi->pdev->dev, in vc4_dsi_ulps()
786 "Timeout waiting for DSI STOP entry: STAT 0x%08x", in vc4_dsi_ulps()
814 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_disable() local
815 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_disable()
817 drm_bridge_disable(dsi->bridge); in vc4_dsi_encoder_disable()
818 vc4_dsi_ulps(dsi, true); in vc4_dsi_encoder_disable()
819 drm_bridge_post_disable(dsi->bridge); in vc4_dsi_encoder_disable()
821 clk_disable_unprepare(dsi->pll_phy_clock); in vc4_dsi_encoder_disable()
822 clk_disable_unprepare(dsi->escape_clock); in vc4_dsi_encoder_disable()
823 clk_disable_unprepare(dsi->pixel_clock); in vc4_dsi_encoder_disable()
829 * DSI PLL divider.
833 * divider. PLLD_DSI1, which drives our DSI bit clock (and therefore
834 * the pixel clock), only has an integer divider off of DSI.
846 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_mode_fixup() local
847 struct clk *phy_parent = clk_get_parent(dsi->pll_phy_clock); in vc4_dsi_encoder_mode_fixup()
850 unsigned long pll_clock = pixel_clock_hz * dsi->divider; in vc4_dsi_encoder_mode_fixup()
867 pixel_clock_hz = pll_clock / dsi->divider; in vc4_dsi_encoder_mode_fixup()
884 struct vc4_dsi *dsi = vc4_encoder->dsi; in vc4_dsi_encoder_enable() local
885 struct device *dev = &dsi->pdev->dev; in vc4_dsi_encoder_enable()
898 DRM_ERROR("Failed to runtime PM enable on DSI%d\n", dsi->port); in vc4_dsi_encoder_enable()
903 DRM_INFO("DSI regs before:\n"); in vc4_dsi_encoder_enable()
904 vc4_dsi_dump_regs(dsi); in vc4_dsi_encoder_enable()
911 phy_clock = (pixel_clock_hz + 1000) * dsi->divider; in vc4_dsi_encoder_enable()
912 ret = clk_set_rate(dsi->pll_phy_clock, phy_clock); in vc4_dsi_encoder_enable()
914 dev_err(&dsi->pdev->dev, in vc4_dsi_encoder_enable()
918 /* Reset the DSI and all its fifos. */ in vc4_dsi_encoder_enable()
931 if (dsi->port == 0) { in vc4_dsi_encoder_enable()
935 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
938 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) in vc4_dsi_encoder_enable()
956 if (dsi->lanes < 4) in vc4_dsi_encoder_enable()
958 if (dsi->lanes < 3) in vc4_dsi_encoder_enable()
960 if (dsi->lanes < 2) in vc4_dsi_encoder_enable()
973 ret = clk_prepare_enable(dsi->escape_clock); in vc4_dsi_encoder_enable()
975 DRM_ERROR("Failed to turn on DSI escape clock: %d\n", ret); in vc4_dsi_encoder_enable()
979 ret = clk_prepare_enable(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
981 DRM_ERROR("Failed to turn on DSI PLL: %d\n", ret); in vc4_dsi_encoder_enable()
985 hs_clock = clk_get_rate(dsi->pll_phy_clock); in vc4_dsi_encoder_enable()
992 * pixel clock for pushing pixels into DSI. in vc4_dsi_encoder_enable()
995 ret = clk_set_rate(dsi->pixel_clock, dsip_clock); in vc4_dsi_encoder_enable()
1001 ret = clk_prepare_enable(dsi->pixel_clock); in vc4_dsi_encoder_enable()
1003 DRM_ERROR("Failed to turn on DSI pixel clock: %d\n", ret); in vc4_dsi_encoder_enable()
1007 /* How many ns one DSI unit interval is. Note that the clock in vc4_dsi_encoder_enable()
1071 (dsi->lanes >= 2 ? DSI_PHYC_DLANE1_ENABLE : 0) | in vc4_dsi_encoder_enable()
1072 (dsi->lanes >= 3 ? DSI_PHYC_DLANE2_ENABLE : 0) | in vc4_dsi_encoder_enable()
1073 (dsi->lanes >= 4 ? DSI_PHYC_DLANE3_ENABLE : 0) | in vc4_dsi_encoder_enable()
1075 ((dsi->mode_flags & MIPI_DSI_CLOCK_NON_CONTINUOUS) ? in vc4_dsi_encoder_enable()
1077 (dsi->port == 0 ? in vc4_dsi_encoder_enable()
1103 if (dsi->port == 0) in vc4_dsi_encoder_enable()
1109 if (dsi->port == 0) { in vc4_dsi_encoder_enable()
1116 vc4_dsi_ulps(dsi, false); in vc4_dsi_encoder_enable()
1118 drm_bridge_pre_enable(dsi->bridge); in vc4_dsi_encoder_enable()
1120 if (dsi->mode_flags & MIPI_DSI_MODE_VIDEO) { in vc4_dsi_encoder_enable()
1122 VC4_SET_FIELD(dsi->divider, in vc4_dsi_encoder_enable()
1124 VC4_SET_FIELD(dsi->format, DSI_DISP0_PFORMAT) | in vc4_dsi_encoder_enable()
1135 drm_bridge_enable(dsi->bridge); in vc4_dsi_encoder_enable()
1138 DRM_INFO("DSI regs after:\n"); in vc4_dsi_encoder_enable()
1139 vc4_dsi_dump_regs(dsi); in vc4_dsi_encoder_enable()
1146 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_transfer() local
1224 dsi->xfer_result = 0; in vc4_dsi_host_transfer()
1225 reinit_completion(&dsi->xfer_completion); in vc4_dsi_host_transfer()
1239 if (!wait_for_completion_timeout(&dsi->xfer_completion, in vc4_dsi_host_transfer()
1241 dev_err(&dsi->pdev->dev, "transfer interrupt wait timeout"); in vc4_dsi_host_transfer()
1242 dev_err(&dsi->pdev->dev, "instat: 0x%08x\n", in vc4_dsi_host_transfer()
1246 ret = dsi->xfer_result; in vc4_dsi_host_transfer()
1263 DRM_ERROR("DSI returned %db, expecting %db\n", in vc4_dsi_host_transfer()
1286 DRM_ERROR("DSI transfer failed, resetting: %d\n", ret); in vc4_dsi_host_transfer()
1302 struct vc4_dsi *dsi = host_to_dsi(host); in vc4_dsi_host_attach() local
1304 dsi->lanes = device->lanes; in vc4_dsi_host_attach()
1305 dsi->channel = device->channel; in vc4_dsi_host_attach()
1306 dsi->mode_flags = device->mode_flags; in vc4_dsi_host_attach()
1310 dsi->format = DSI_PFORMAT_RGB888; in vc4_dsi_host_attach()
1311 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1314 dsi->format = DSI_PFORMAT_RGB666; in vc4_dsi_host_attach()
1315 dsi->divider = 24 / dsi->lanes; in vc4_dsi_host_attach()
1318 dsi->format = DSI_PFORMAT_RGB666_PACKED; in vc4_dsi_host_attach()
1319 dsi->divider = 18 / dsi->lanes; in vc4_dsi_host_attach()
1322 dsi->format = DSI_PFORMAT_RGB565; in vc4_dsi_host_attach()
1323 dsi->divider = 16 / dsi->lanes; in vc4_dsi_host_attach()
1326 dev_err(&dsi->pdev->dev, "Unknown DSI format: %d.\n", in vc4_dsi_host_attach()
1327 dsi->format); in vc4_dsi_host_attach()
1331 if (!(dsi->mode_flags & MIPI_DSI_MODE_VIDEO)) { in vc4_dsi_host_attach()
1332 dev_err(&dsi->pdev->dev, in vc4_dsi_host_attach()
1363 static void dsi_handle_error(struct vc4_dsi *dsi, in dsi_handle_error() argument
1370 DRM_ERROR("DSI%d: %s error\n", dsi->port, type); in dsi_handle_error()
1382 struct vc4_dsi *dsi = data; in vc4_dsi_irq_defer_to_thread_handler() local
1397 struct vc4_dsi *dsi = data; in vc4_dsi_irq_handler() local
1403 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1405 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1407 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1409 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1411 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1413 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1415 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1417 dsi_handle_error(dsi, &ret, stat, in vc4_dsi_irq_handler()
1421 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1424 complete(&dsi->xfer_completion); in vc4_dsi_irq_handler()
1425 dsi->xfer_result = -ETIMEDOUT; in vc4_dsi_irq_handler()
1435 * @dsi: DSI encoder
1438 vc4_dsi_init_phy_clocks(struct vc4_dsi *dsi) in vc4_dsi_init_phy_clocks() argument
1440 struct device *dev = &dsi->pdev->dev; in vc4_dsi_init_phy_clocks()
1441 const char *parent_name = __clk_get_name(dsi->pll_phy_clock); in vc4_dsi_init_phy_clocks()
1452 dsi->clk_onecell = devm_kzalloc(dev, in vc4_dsi_init_phy_clocks()
1453 sizeof(*dsi->clk_onecell) + in vc4_dsi_init_phy_clocks()
1457 if (!dsi->clk_onecell) in vc4_dsi_init_phy_clocks()
1459 dsi->clk_onecell->num = ARRAY_SIZE(phy_clocks); in vc4_dsi_init_phy_clocks()
1462 struct clk_fixed_factor *fix = &dsi->phy_clocks[i]; in vc4_dsi_init_phy_clocks()
1471 * setting both our parent DSI PLL's rate and this in vc4_dsi_init_phy_clocks()
1482 if (dsi->port == 1) in vc4_dsi_init_phy_clocks()
1492 dsi->clk_onecell->hws[i] = &fix->hw; in vc4_dsi_init_phy_clocks()
1497 dsi->clk_onecell); in vc4_dsi_init_phy_clocks()
1505 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_bind() local
1516 dsi->port = (uintptr_t)match->data; in vc4_dsi_bind()
1523 vc4_dsi_encoder->dsi = dsi; in vc4_dsi_bind()
1524 dsi->encoder = &vc4_dsi_encoder->base.base; in vc4_dsi_bind()
1526 dsi->regs = vc4_ioremap_regs(pdev, 0); in vc4_dsi_bind()
1527 if (IS_ERR(dsi->regs)) in vc4_dsi_bind()
1528 return PTR_ERR(dsi->regs); in vc4_dsi_bind()
1540 if (dsi->port == 1) { in vc4_dsi_bind()
1541 dsi->reg_dma_mem = dma_alloc_coherent(dev, 4, in vc4_dsi_bind()
1542 &dsi->reg_dma_paddr, in vc4_dsi_bind()
1544 if (!dsi->reg_dma_mem) { in vc4_dsi_bind()
1551 dsi->reg_dma_chan = dma_request_chan_by_mask(&dma_mask); in vc4_dsi_bind()
1552 if (IS_ERR(dsi->reg_dma_chan)) { in vc4_dsi_bind()
1553 ret = PTR_ERR(dsi->reg_dma_chan); in vc4_dsi_bind()
1564 dsi->reg_paddr = be32_to_cpup(of_get_address(dev->of_node, in vc4_dsi_bind()
1568 init_completion(&dsi->xfer_completion); in vc4_dsi_bind()
1574 if (dsi->reg_dma_mem) in vc4_dsi_bind()
1579 "vc4 dsi", dsi); in vc4_dsi_bind()
1582 vc4_dsi_irq_handler, 0, "vc4 dsi", dsi); in vc4_dsi_bind()
1589 dsi->escape_clock = devm_clk_get(dev, "escape"); in vc4_dsi_bind()
1590 if (IS_ERR(dsi->escape_clock)) { in vc4_dsi_bind()
1591 ret = PTR_ERR(dsi->escape_clock); in vc4_dsi_bind()
1597 dsi->pll_phy_clock = devm_clk_get(dev, "phy"); in vc4_dsi_bind()
1598 if (IS_ERR(dsi->pll_phy_clock)) { in vc4_dsi_bind()
1599 ret = PTR_ERR(dsi->pll_phy_clock); in vc4_dsi_bind()
1605 dsi->pixel_clock = devm_clk_get(dev, "pixel"); in vc4_dsi_bind()
1606 if (IS_ERR(dsi->pixel_clock)) { in vc4_dsi_bind()
1607 ret = PTR_ERR(dsi->pixel_clock); in vc4_dsi_bind()
1614 &panel, &dsi->bridge); in vc4_dsi_bind()
1618 * dev from being registered. Of course that means the DSI in vc4_dsi_bind()
1629 dsi->bridge = devm_drm_panel_bridge_add(dev, panel, in vc4_dsi_bind()
1631 if (IS_ERR(dsi->bridge)) in vc4_dsi_bind()
1632 return PTR_ERR(dsi->bridge); in vc4_dsi_bind()
1636 ret = clk_set_rate(dsi->escape_clock, 100 * 1000000); in vc4_dsi_bind()
1642 ret = vc4_dsi_init_phy_clocks(dsi); in vc4_dsi_bind()
1646 if (dsi->port == 1) in vc4_dsi_bind()
1647 vc4->dsi1 = dsi; in vc4_dsi_bind()
1649 drm_encoder_init(drm, dsi->encoder, &vc4_dsi_encoder_funcs, in vc4_dsi_bind()
1651 drm_encoder_helper_add(dsi->encoder, &vc4_dsi_encoder_helper_funcs); in vc4_dsi_bind()
1653 ret = drm_bridge_attach(dsi->encoder, dsi->bridge, NULL); in vc4_dsi_bind()
1663 dsi->encoder->bridge = NULL; in vc4_dsi_bind()
1675 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_unbind() local
1677 if (dsi->bridge) in vc4_dsi_unbind()
1680 vc4_dsi_encoder_destroy(dsi->encoder); in vc4_dsi_unbind()
1682 if (dsi->port == 1) in vc4_dsi_unbind()
1694 struct vc4_dsi *dsi; in vc4_dsi_dev_probe() local
1697 dsi = devm_kzalloc(dev, sizeof(*dsi), GFP_KERNEL); in vc4_dsi_dev_probe()
1698 if (!dsi) in vc4_dsi_dev_probe()
1700 dev_set_drvdata(dev, dsi); in vc4_dsi_dev_probe()
1702 dsi->pdev = pdev; in vc4_dsi_dev_probe()
1704 /* Note, the initialization sequence for DSI and panels is in vc4_dsi_dev_probe()
1713 dsi->dsi_host.ops = &vc4_dsi_host_ops; in vc4_dsi_dev_probe()
1714 dsi->dsi_host.dev = dev; in vc4_dsi_dev_probe()
1715 mipi_dsi_host_register(&dsi->dsi_host); in vc4_dsi_dev_probe()
1719 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_probe()
1729 struct vc4_dsi *dsi = dev_get_drvdata(dev); in vc4_dsi_dev_remove() local
1732 mipi_dsi_host_unregister(&dsi->dsi_host); in vc4_dsi_dev_remove()