Lines Matching +full:8 +full:bit
30 ('3' << 8) | \
41 # define V3D_IDENT1_QUPS_MASK VC4_MASK(11, 8)
42 # define V3D_IDENT1_QUPS_SHIFT 8
51 # define V3D_L2CACTL_L2CCLR BIT(2)
52 # define V3D_L2CACTL_L2CDIS BIT(1)
53 # define V3D_L2CACTL_L2CENA BIT(0)
60 # define V3D_SLCACTL_UCC_MASK VC4_MASK(11, 8)
61 # define V3D_SLCACTL_UCC_SHIFT 8
68 # define V3D_INT_SPILLUSE BIT(3)
69 # define V3D_INT_OUTOMEM BIT(2)
70 # define V3D_INT_FLDONE BIT(1)
71 # define V3D_INT_FRDONE BIT(0)
76 # define V3D_CTRSTA BIT(15)
77 # define V3D_CTSEMA BIT(12)
78 # define V3D_CTRTSD BIT(8)
79 # define V3D_CTRUN BIT(5)
80 # define V3D_CTSUBS BIT(4)
81 # define V3D_CTERR BIT(3)
82 # define V3D_CTMODE BIT(0)
101 # define V3D_BMOOM BIT(8)
102 # define V3D_RMBUSY BIT(3)
103 # define V3D_RMACTIVE BIT(2)
104 # define V3D_BMBUSY BIT(1)
105 # define V3D_BMACTIVE BIT(0)
125 # define V3D_PCTRE_EN BIT(31)
126 #define V3D_PCTR(x) (0x00680 + ((x) * 8))
127 #define V3D_PCTRS(x) (0x00684 + ((x) * 8))
146 # define PV_CONTROL_CLR_AT_START BIT(14)
147 # define PV_CONTROL_TRIGGER_UNDERFLOW BIT(13)
148 # define PV_CONTROL_WAIT_HSTART BIT(12)
156 # define PV_CONTROL_FIFO_CLR BIT(1)
157 # define PV_CONTROL_EN BIT(0)
162 # define PV_VCONTROL_ODD_FIRST BIT(5)
163 # define PV_VCONTROL_INTERLACE BIT(4)
164 # define PV_VCONTROL_DSI BIT(3)
165 # define PV_VCONTROL_COMMAND BIT(2)
166 # define PV_VCONTROL_CONTINUOUS BIT(1)
167 # define PV_VCONTROL_VIDEN BIT(0)
200 # define PV_INT_VID_IDLE BIT(9)
201 # define PV_INT_VFP_END BIT(8)
202 # define PV_INT_VFP_START BIT(7)
203 # define PV_INT_VACT_START BIT(6)
204 # define PV_INT_VBP_START BIT(5)
205 # define PV_INT_VSYNC_START BIT(4)
206 # define PV_INT_HFP_START BIT(3)
207 # define PV_INT_HACT_START BIT(2)
208 # define PV_INT_HBP_START BIT(1)
209 # define PV_INT_HSYNC_START BIT(0)
217 # define SCALER_DISPCTRL_ENABLE BIT(31)
218 # define SCALER_DISPCTRL_DSP2EISLUR BIT(15)
219 # define SCALER_DISPCTRL_DSP1EISLUR BIT(14)
227 # define SCALER_DISPCTRL_DSP0EISLUR BIT(13)
228 # define SCALER_DISPCTRL_DSP2EIEOLN BIT(12)
229 # define SCALER_DISPCTRL_DSP2EIEOF BIT(11)
230 # define SCALER_DISPCTRL_DSP1EIEOLN BIT(10)
231 # define SCALER_DISPCTRL_DSP1EIEOF BIT(9)
235 # define SCALER_DISPCTRL_DSP0EIEOLN BIT(8)
237 # define SCALER_DISPCTRL_DSP0EIEOF BIT(7)
239 # define SCALER_DISPCTRL_SLVRDEIRQ BIT(6)
240 # define SCALER_DISPCTRL_SLVWREIRQ BIT(5)
241 # define SCALER_DISPCTRL_DMAEIRQ BIT(4)
242 # define SCALER_DISPCTRL_DISP2EIRQ BIT(3)
243 # define SCALER_DISPCTRL_DISP1EIRQ BIT(2)
247 # define SCALER_DISPCTRL_DISP0EIRQ BIT(1)
249 # define SCALER_DISPCTRL_SCLEIRQ BIT(0)
252 # define SCALER_DISPSTAT_COBLOW2 BIT(29)
253 # define SCALER_DISPSTAT_EOLN2 BIT(28)
254 # define SCALER_DISPSTAT_ESFRAME2 BIT(27)
255 # define SCALER_DISPSTAT_ESLINE2 BIT(26)
256 # define SCALER_DISPSTAT_EUFLOW2 BIT(25)
257 # define SCALER_DISPSTAT_EOF2 BIT(24)
259 # define SCALER_DISPSTAT_COBLOW1 BIT(21)
260 # define SCALER_DISPSTAT_EOLN1 BIT(20)
261 # define SCALER_DISPSTAT_ESFRAME1 BIT(19)
262 # define SCALER_DISPSTAT_ESLINE1 BIT(18)
263 # define SCALER_DISPSTAT_EUFLOW1 BIT(17)
264 # define SCALER_DISPSTAT_EOF1 BIT(16)
273 # define SCALER_DISPSTAT_COBLOW0 BIT(13)
275 # define SCALER_DISPSTAT_EOLN0 BIT(12)
279 # define SCALER_DISPSTAT_ESFRAME0 BIT(11)
283 # define SCALER_DISPSTAT_ESLINE0 BIT(10)
287 # define SCALER_DISPSTAT_EUFLOW0 BIT(9)
289 # define SCALER_DISPSTAT_EOF0 BIT(8)
292 # define SCALER_DISPSTAT_DMA_ERROR BIT(7)
294 # define SCALER_DISPSTAT_IRQSLVRD BIT(6)
296 # define SCALER_DISPSTAT_IRQSLVWR BIT(5)
300 # define SCALER_DISPSTAT_IRQDMA BIT(4)
301 # define SCALER_DISPSTAT_IRQDISP2 BIT(3)
302 # define SCALER_DISPSTAT_IRQDISP1 BIT(2)
304 * corresponding interrupt bit is enabled in DISPCTRL.
306 # define SCALER_DISPSTAT_IRQDISP0 BIT(1)
308 # define SCALER_DISPSTAT_IRQSCL BIT(0)
331 # define SCALER_DISPCTRLX_ENABLE BIT(31)
332 # define SCALER_DISPCTRLX_RESET BIT(30)
336 # define SCALER_DISPCTRLX_ONESHOT BIT(29)
340 # define SCALER_DISPCTRLX_ONECTX BIT(28)
342 # define SCALER_DISPCTRLX_FIFO32 BIT(27)
346 # define SCALER_DISPCTRLX_FIFOREG BIT(26)
354 # define SCALER_DISPBKGND_AUTOHS BIT(31)
355 # define SCALER_DISPBKGND_INTERLACE BIT(30)
356 # define SCALER_DISPBKGND_GAMMA BIT(29)
363 # define SCALER_DISPBKGND_FILL BIT(24)
372 # define SCALER_DISPSTATX_FULL BIT(29)
373 # define SCALER_DISPSTATX_EMPTY BIT(28)
414 # define SCALER_GAMADDR_AUTOINC BIT(31)
418 # define SCALER_GAMADDR_SRAMENB BIT(30)
422 # define SCALER_OLEDOFFS_YUVCLAMP BIT(31)
432 /* Offsets are 8-bit 2s-complement. */
435 # define SCALER_OLEDOFFS_GREEN_MASK VC4_MASK(15, 8)
436 # define SCALER_OLEDOFFS_GREEN_SHIFT 8
471 # define SCALER_DISPSLAVE_ISSUE_VSTART BIT(31)
472 # define SCALER_DISPSLAVE_ISSUE_HSTART BIT(30)
474 # define SCALER_DISPSLAVE_EOL BIT(26)
476 # define SCALER_DISPSLAVE_EMPTY BIT(25)
478 # define SCALER_DISPSLAVE_VALID BIT(24)
489 # define VC4_HDMI_SW_RESET_FORMAT_DETECT BIT(1)
490 # define VC4_HDMI_SW_RESET_HDMI BIT(0)
495 # define VC4_HDMI_HOTPLUG_CONNECTED BIT(0)
503 # define VC4_HDMI_MAI_CONFIG_FORMAT_REVERSE BIT(27)
504 # define VC4_HDMI_MAI_CONFIG_BIT_REVERSE BIT(26)
512 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_SAMPLE_FLAT BIT(29)
513 # define VC4_HDMI_AUDIO_PACKET_ZERO_DATA_ON_INACTIVE_CHANNELS BIT(24)
514 # define VC4_HDMI_AUDIO_PACKET_FORCE_SAMPLE_PRESENT BIT(19)
515 # define VC4_HDMI_AUDIO_PACKET_FORCE_B_FRAME BIT(18)
519 # define VC4_HDMI_AUDIO_PACKET_AUDIO_LAYOUT BIT(9)
521 # define VC4_HDMI_AUDIO_PACKET_FORCE_AUDIO_LAYOUT BIT(8)
526 # define VC4_HDMI_RAM_PACKET_ENABLE BIT(16)
534 # define VC4_HDMI_CRP_USE_MAI_BUS_SYNC_FOR_CTS BIT(26)
536 # define VC4_HDMI_CRP_CFG_DISABLE BIT(25)
540 # define VC4_HDMI_CRP_CFG_EXTERNAL_CTS_EN BIT(24)
544 /* 20-bit fields containing CTS values to be transmitted if !EXTERNAL_CTS_EN */
547 /* 20-bit fields containing number of clocks to send CTS0/1 before
554 # define VC4_HDMI_HORZA_VPOS BIT(14)
555 # define VC4_HDMI_HORZA_HPOS BIT(13)
572 # define VC4_HDMI_FIFO_CTL_RECENTER_DONE BIT(14)
573 # define VC4_HDMI_FIFO_CTL_USE_EMPTY BIT(13)
574 # define VC4_HDMI_FIFO_CTL_ON_VB BIT(7)
575 # define VC4_HDMI_FIFO_CTL_RECENTER BIT(6)
576 # define VC4_HDMI_FIFO_CTL_FIFO_RESET BIT(5)
577 # define VC4_HDMI_FIFO_CTL_USE_PLL_LOCK BIT(4)
578 # define VC4_HDMI_FIFO_CTL_INV_CLK_XFR BIT(3)
579 # define VC4_HDMI_FIFO_CTL_CAPTURE_PTR BIT(2)
580 # define VC4_HDMI_FIFO_CTL_USE_FULL BIT(1)
581 # define VC4_HDMI_FIFO_CTL_MASTER_SLAVE_N BIT(0)
585 # define VC4_HDMI_SCHEDULER_CONTROL_MANUAL_FORMAT BIT(15)
586 # define VC4_HDMI_SCHEDULER_CONTROL_IGNORE_VSYNC_PREDICTS BIT(5)
587 # define VC4_HDMI_SCHEDULER_CONTROL_VERT_ALWAYS_KEEPOUT BIT(3)
588 # define VC4_HDMI_SCHEDULER_CONTROL_HDMI_ACTIVE BIT(1)
589 # define VC4_HDMI_SCHEDULER_CONTROL_MODE_HDMI BIT(0)
609 # define VC4_HDMI_VERTB_VBP_MASK VC4_MASK(8, 0)
614 # define VC4_HDMI_CEC_TX_EOM BIT(31)
619 # define VC4_HDMI_CEC_TX_STATUS_GOOD BIT(30)
620 # define VC4_HDMI_CEC_RX_EOM BIT(29)
621 # define VC4_HDMI_CEC_RX_STATUS_GOOD BIT(28)
625 /* Sets continuous receive mode. Generates interrupt after each 8
632 # define VC4_HDMI_CEC_RX_CONTINUE BIT(23)
633 # define VC4_HDMI_CEC_TX_CONTINUE BIT(22)
635 # define VC4_HDMI_CEC_CLEAR_RECEIVE_OFF BIT(21)
639 # define VC4_HDMI_CEC_START_XMIT_BEGIN BIT(20)
645 /* Divides off of HSM clock to generate CEC bit clock. */
646 /* With the current defaults the CEC bit clock is 40 kHz = 25 usec */
650 /* Set these fields to how many bit clock cycles get to that many
670 # define VC4_HDMI_CEC_CNT_TO_2050_US_MASK VC4_MASK(15, 8)
671 # define VC4_HDMI_CEC_CNT_TO_2050_US_SHIFT 8
680 # define VC4_HDMI_CEC_CNT_TO_3600_US_MASK VC4_MASK(15, 8)
681 # define VC4_HDMI_CEC_CNT_TO_3600_US_SHIFT 8
686 # define VC4_HDMI_CEC_TX_SW_RESET BIT(27)
687 # define VC4_HDMI_CEC_RX_SW_RESET BIT(26)
688 # define VC4_HDMI_CEC_PAD_SW_RESET BIT(25)
689 # define VC4_HDMI_CEC_MUX_TP_OUT_CEC BIT(24)
690 # define VC4_HDMI_CEC_RX_CEC_INT BIT(23)
693 # define VC4_HDMI_CEC_CNT_TO_4700_US_MASK VC4_MASK(15, 8)
694 # define VC4_HDMI_CEC_CNT_TO_4700_US_SHIFT 8
698 /* Transmit data, first byte is low byte of the 32-bit reg. MSB of
713 # define VC4_HDMI_TX_PHY_RNG_PWRDN BIT(25)
719 # define VC4_HDMI_CPU_CEC BIT(6)
720 # define VC4_HDMI_CPU_HOTPLUG BIT(0)
732 # define VC4_HD_CECRXD BIT(9)
734 # define VC4_HD_CECOVR BIT(8)
737 # define VC4_HD_M_SW_RST BIT(2)
738 # define VC4_HD_M_ENABLE BIT(0)
744 # define VC4_HD_MAI_CTL_DLATE BIT(15)
745 # define VC4_HD_MAI_CTL_BUSY BIT(14)
746 # define VC4_HD_MAI_CTL_CHALIGN BIT(13)
747 # define VC4_HD_MAI_CTL_WHOLSMP BIT(12)
748 # define VC4_HD_MAI_CTL_FULL BIT(11)
749 # define VC4_HD_MAI_CTL_EMPTY BIT(10)
750 # define VC4_HD_MAI_CTL_FLUSH BIT(9)
751 /* If set, MAI bus generates SPDIF (bit 31) parity instead of passing
754 # define VC4_HD_MAI_CTL_PAREN BIT(8)
757 # define VC4_HD_MAI_CTL_ENABLE BIT(3)
758 /* Underflow error status bit, write 1 to clear. */
759 # define VC4_HD_MAI_CTL_ERRORE BIT(2)
760 /* Overflow error status bit, write 1 to clear. */
761 # define VC4_HD_MAI_CTL_ERRORF BIT(1)
762 /* Single-shot reset bit. Read value is undefined. */
763 # define VC4_HD_MAI_CTL_RESET BIT(0)
770 # define VC4_HD_MAI_THR_DREQHIGH_MASK VC4_MASK(13, 8)
771 # define VC4_HD_MAI_THR_DREQHIGH_SHIFT 8
787 # define VC4_HD_MAI_SMP_N_MASK VC4_MASK(31, 8)
788 # define VC4_HD_MAI_SMP_N_SHIFT 8
793 # define VC4_HD_VID_CTL_ENABLE BIT(31)
794 # define VC4_HD_VID_CTL_UNDERFLOW_ENABLE BIT(30)
795 # define VC4_HD_VID_CTL_FRAME_COUNTER_RESET BIT(29)
796 # define VC4_HD_VID_CTL_VSYNC_LOW BIT(28)
797 # define VC4_HD_VID_CTL_HSYNC_LOW BIT(27)
808 # define VC4_HD_CSC_CTL_PADMSB BIT(4)
814 # define VC4_HD_CSC_CTL_RGB2YCC BIT(1)
815 # define VC4_HD_CSC_CTL_ENABLE BIT(0)
830 /* 8bpp */
843 HVS_PIXEL_FORMAT_YCBCR_YUV420_3PLANE = 8,
871 #define SCALER_CTL0_END BIT(31)
872 #define SCALER_CTL0_VALID BIT(30)
884 #define SCALER_CTL0_ALPHA_MASK BIT(19)
885 #define SCALER_CTL0_HFLIP BIT(16)
886 #define SCALER_CTL0_VFLIP BIT(15)
905 #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8)
906 #define SCALER_CTL0_SCL1_SHIFT 8
921 #define SCALER_CTL0_UNITY BIT(4)
947 #define SCALER_POS2_ALPHA_PREMULT BIT(29)
948 #define SCALER_POS2_ALPHA_MIX BIT(28)
956 /* Color Space Conversion words. Some values are S2.8 signed
960 /* bottom 8 bits of S2.8 contribution of Cr to Blue */
967 #define SCALER_CSC0_COEF_CB_OFS_MASK VC4_MASK(15, 8)
968 #define SCALER_CSC0_COEF_CB_OFS_SHIFT 8
976 /* S2.8 contribution of Cb to Green */
979 /* S2.8 contribution of Cr to Green */
982 /* S2.8 contribution of Y to all of RGB */
985 /* top 2 bits of S2.8 contribution of Cr to Blue */
992 /* S2.8 contribution of Cb to Red */
995 /* S2.8 contribution of Cr to Red */
998 /* S2.8 contribution of Cb to Blue */
1005 #define SCALER_TPZ0_VERT_RECALC BIT(31)
1006 #define SCALER_TPZ0_SCALE_MASK VC4_MASK(28, 8)
1007 #define SCALER_TPZ0_SCALE_SHIFT 8
1013 /* Skips interpolating coefficients to 64 phases, so just 8 are used.
1016 #define SCALER_PPF_NOINTERP BIT(31)
1020 #define SCALER_PPF_AGC BIT(30)
1021 #define SCALER_PPF_SCALE_MASK VC4_MASK(24, 8)
1022 #define SCALER_PPF_SCALE_SHIFT 8
1028 #define SCALER_PPF_KERNEL_UNCACHED BIT(31)
1043 #define SCALER_PITCH0_TILE_LINE_DIR BIT(15)
1044 #define SCALER_PITCH0_TILE_INITIAL_LINE_DIR BIT(14)