Lines Matching full:ipu
35 #include <video/imx-ipu-v3.h>
36 #include "ipu-prv.h"
38 static inline u32 ipu_cm_read(struct ipu_soc *ipu, unsigned offset) in ipu_cm_read() argument
40 return readl(ipu->cm_reg + offset); in ipu_cm_read()
43 static inline void ipu_cm_write(struct ipu_soc *ipu, u32 value, unsigned offset) in ipu_cm_write() argument
45 writel(value, ipu->cm_reg + offset); in ipu_cm_write()
48 int ipu_get_num(struct ipu_soc *ipu) in ipu_get_num() argument
50 return ipu->id; in ipu_get_num()
54 void ipu_srm_dp_update(struct ipu_soc *ipu, bool sync) in ipu_srm_dp_update() argument
58 val = ipu_cm_read(ipu, IPU_SRM_PRI2); in ipu_srm_dp_update()
62 ipu_cm_write(ipu, val, IPU_SRM_PRI2); in ipu_srm_dp_update()
270 struct ipuv3_channel *ipu_idmac_get(struct ipu_soc *ipu, unsigned num) in ipu_idmac_get() argument
274 dev_dbg(ipu->dev, "%s %d\n", __func__, num); in ipu_idmac_get()
279 mutex_lock(&ipu->channel_lock); in ipu_idmac_get()
281 list_for_each_entry(channel, &ipu->channels, list) { in ipu_idmac_get()
295 channel->ipu = ipu; in ipu_idmac_get()
296 list_add(&channel->list, &ipu->channels); in ipu_idmac_get()
299 mutex_unlock(&ipu->channel_lock); in ipu_idmac_get()
307 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_put() local
309 dev_dbg(ipu->dev, "%s %d\n", __func__, channel->num); in ipu_idmac_put()
311 mutex_lock(&ipu->channel_lock); in ipu_idmac_put()
316 mutex_unlock(&ipu->channel_lock); in ipu_idmac_put()
335 struct ipu_soc *ipu = channel->ipu; in __ipu_idmac_reset_current_buffer() local
338 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_CUR_BUF(chno)); in __ipu_idmac_reset_current_buffer()
344 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_set_double_buffer() local
348 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
350 reg = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
355 ipu_cm_write(ipu, reg, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_set_double_buffer()
359 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_set_double_buffer()
389 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_lock_enable() local
417 if (bursts && ipu->ipu_type != IPUV3H) in ipu_idmac_lock_enable()
427 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_lock_enable()
429 regval = ipu_idmac_read(ipu, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
432 ipu_idmac_write(ipu, regval, idmac_lock_en_info[i].reg); in ipu_idmac_lock_enable()
434 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_lock_enable()
440 int ipu_module_enable(struct ipu_soc *ipu, u32 mask) in ipu_module_enable() argument
445 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_enable()
447 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_enable()
454 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_enable()
456 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_enable()
458 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_enable()
460 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_enable()
466 int ipu_module_disable(struct ipu_soc *ipu, u32 mask) in ipu_module_disable() argument
471 spin_lock_irqsave(&ipu->lock, lock_flags); in ipu_module_disable()
473 val = ipu_cm_read(ipu, IPU_CONF); in ipu_module_disable()
475 ipu_cm_write(ipu, val, IPU_CONF); in ipu_module_disable()
477 val = ipu_cm_read(ipu, IPU_DISP_GEN); in ipu_module_disable()
484 ipu_cm_write(ipu, val, IPU_DISP_GEN); in ipu_module_disable()
486 spin_unlock_irqrestore(&ipu->lock, lock_flags); in ipu_module_disable()
494 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_get_current_buffer() local
497 return (ipu_cm_read(ipu, IPU_CHA_CUR_BUF(chno)) & idma_mask(chno)) ? 1 : 0; in ipu_idmac_get_current_buffer()
503 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_buffer_is_ready() local
507 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
510 reg = ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
513 reg = ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
516 reg = ipu_cm_read(ipu, IPU_CHA_BUF2_RDY(channel->num)); in ipu_idmac_buffer_is_ready()
519 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_buffer_is_ready()
527 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_select_buffer() local
531 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_select_buffer()
535 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_select_buffer()
537 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_select_buffer()
539 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_select_buffer()
545 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_clear_buffer() local
549 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_clear_buffer()
551 ipu_cm_write(ipu, 0xF0300000, IPU_GPR); /* write one to clear */ in ipu_idmac_clear_buffer()
554 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF0_RDY(chno)); in ipu_idmac_clear_buffer()
557 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF1_RDY(chno)); in ipu_idmac_clear_buffer()
560 ipu_cm_write(ipu, idma_mask(chno), IPU_CHA_BUF2_RDY(chno)); in ipu_idmac_clear_buffer()
565 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_clear_buffer()
567 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_clear_buffer()
573 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_channel() local
577 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_channel()
579 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
581 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_enable_channel()
583 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_channel()
589 bool ipu_idmac_channel_busy(struct ipu_soc *ipu, unsigned int chno) in ipu_idmac_channel_busy() argument
591 return (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(chno)) & idma_mask(chno)); in ipu_idmac_channel_busy()
597 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_wait_busy() local
601 while (ipu_idmac_read(ipu, IDMAC_CHA_BUSY(channel->num)) & in ipu_idmac_wait_busy()
614 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_disable_channel() local
618 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_disable_channel()
621 val = ipu_idmac_read(ipu, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
623 ipu_idmac_write(ipu, val, IDMAC_CHA_EN(channel->num)); in ipu_idmac_disable_channel()
628 ipu_cm_write(ipu, 0xf0000000, IPU_GPR); /* write one to clear */ in ipu_idmac_disable_channel()
630 if (ipu_cm_read(ipu, IPU_CHA_BUF0_RDY(channel->num)) & in ipu_idmac_disable_channel()
632 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
636 if (ipu_cm_read(ipu, IPU_CHA_BUF1_RDY(channel->num)) & in ipu_idmac_disable_channel()
638 ipu_cm_write(ipu, idma_mask(channel->num), in ipu_idmac_disable_channel()
642 ipu_cm_write(ipu, 0x0, IPU_GPR); /* write one to set */ in ipu_idmac_disable_channel()
645 val = ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
647 ipu_cm_write(ipu, val, IPU_CHA_DB_MODE_SEL(channel->num)); in ipu_idmac_disable_channel()
649 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_disable_channel()
663 struct ipu_soc *ipu = channel->ipu; in ipu_idmac_enable_watermark() local
667 spin_lock_irqsave(&ipu->lock, flags); in ipu_idmac_enable_watermark()
669 val = ipu_idmac_read(ipu, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
674 ipu_idmac_write(ipu, val, IDMAC_WM_EN(channel->num)); in ipu_idmac_enable_watermark()
676 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_idmac_enable_watermark()
680 static int ipu_memory_reset(struct ipu_soc *ipu) in ipu_memory_reset() argument
684 ipu_cm_write(ipu, 0x807FFFFF, IPU_MEM_RST); in ipu_memory_reset()
687 while (ipu_cm_read(ipu, IPU_MEM_RST) & 0x80000000) { in ipu_memory_reset()
700 void ipu_set_csi_src_mux(struct ipu_soc *ipu, int csi_id, bool mipi_csi2) in ipu_set_csi_src_mux() argument
708 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_csi_src_mux()
710 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_csi_src_mux()
715 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_csi_src_mux()
717 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_csi_src_mux()
724 void ipu_set_ic_src_mux(struct ipu_soc *ipu, int csi_id, bool vdi) in ipu_set_ic_src_mux() argument
729 spin_lock_irqsave(&ipu->lock, flags); in ipu_set_ic_src_mux()
731 val = ipu_cm_read(ipu, IPU_CONF); in ipu_set_ic_src_mux()
742 ipu_cm_write(ipu, val, IPU_CONF); in ipu_set_ic_src_mux()
744 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_set_ic_src_mux()
802 int ipu_fsu_link(struct ipu_soc *ipu, int src_ch, int sink_ch) in ipu_fsu_link() argument
812 spin_lock_irqsave(&ipu->lock, flags); in ipu_fsu_link()
815 src_reg = ipu_cm_read(ipu, link->src.reg); in ipu_fsu_link()
818 ipu_cm_write(ipu, src_reg, link->src.reg); in ipu_fsu_link()
822 sink_reg = ipu_cm_read(ipu, link->sink.reg); in ipu_fsu_link()
825 ipu_cm_write(ipu, sink_reg, link->sink.reg); in ipu_fsu_link()
828 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_fsu_link()
836 int ipu_fsu_unlink(struct ipu_soc *ipu, int src_ch, int sink_ch) in ipu_fsu_unlink() argument
846 spin_lock_irqsave(&ipu->lock, flags); in ipu_fsu_unlink()
849 src_reg = ipu_cm_read(ipu, link->src.reg); in ipu_fsu_unlink()
851 ipu_cm_write(ipu, src_reg, link->src.reg); in ipu_fsu_unlink()
855 sink_reg = ipu_cm_read(ipu, link->sink.reg); in ipu_fsu_unlink()
857 ipu_cm_write(ipu, sink_reg, link->sink.reg); in ipu_fsu_unlink()
860 spin_unlock_irqrestore(&ipu->lock, flags); in ipu_fsu_unlink()
868 return ipu_fsu_link(src->ipu, src->num, sink->num); in ipu_idmac_link()
875 return ipu_fsu_unlink(src->ipu, src->num, sink->num); in ipu_idmac_unlink()
944 { .compatible = "fsl,imx51-ipu", .data = &ipu_type_imx51, },
945 { .compatible = "fsl,imx53-ipu", .data = &ipu_type_imx53, },
946 { .compatible = "fsl,imx6q-ipu", .data = &ipu_type_imx6q, },
947 { .compatible = "fsl,imx6qp-ipu", .data = &ipu_type_imx6q, },
952 static int ipu_submodules_init(struct ipu_soc *ipu, in ipu_submodules_init() argument
959 const struct ipu_devtype *devtype = ipu->devtype; in ipu_submodules_init()
961 ret = ipu_cpmem_init(ipu, dev, ipu_base + devtype->cpmem_ofs); in ipu_submodules_init()
967 ret = ipu_csi_init(ipu, dev, 0, ipu_base + devtype->csi0_ofs, in ipu_submodules_init()
974 ret = ipu_csi_init(ipu, dev, 1, ipu_base + devtype->csi1_ofs, in ipu_submodules_init()
981 ret = ipu_ic_init(ipu, dev, in ipu_submodules_init()
989 ret = ipu_vdi_init(ipu, dev, ipu_base + devtype->vdi_ofs, in ipu_submodules_init()
997 ret = ipu_image_convert_init(ipu, dev); in ipu_submodules_init()
1003 ret = ipu_di_init(ipu, dev, 0, ipu_base + devtype->disp0_ofs, in ipu_submodules_init()
1010 ret = ipu_di_init(ipu, dev, 1, ipu_base + devtype->disp1_ofs, in ipu_submodules_init()
1017 ret = ipu_dc_init(ipu, dev, ipu_base + devtype->cm_ofs + in ipu_submodules_init()
1024 ret = ipu_dmfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
1031 ret = ipu_dp_init(ipu, dev, ipu_base + devtype->srm_ofs); in ipu_submodules_init()
1037 ret = ipu_smfc_init(ipu, dev, ipu_base + in ipu_submodules_init()
1047 ipu_dp_exit(ipu); in ipu_submodules_init()
1049 ipu_dmfc_exit(ipu); in ipu_submodules_init()
1051 ipu_dc_exit(ipu); in ipu_submodules_init()
1053 ipu_di_exit(ipu, 1); in ipu_submodules_init()
1055 ipu_di_exit(ipu, 0); in ipu_submodules_init()
1057 ipu_image_convert_exit(ipu); in ipu_submodules_init()
1059 ipu_vdi_exit(ipu); in ipu_submodules_init()
1061 ipu_ic_exit(ipu); in ipu_submodules_init()
1063 ipu_csi_exit(ipu, 1); in ipu_submodules_init()
1065 ipu_csi_exit(ipu, 0); in ipu_submodules_init()
1067 ipu_cpmem_exit(ipu); in ipu_submodules_init()
1073 static void ipu_irq_handle(struct ipu_soc *ipu, const int *regs, int num_regs) in ipu_irq_handle() argument
1080 status = ipu_cm_read(ipu, IPU_INT_STAT(regs[i])); in ipu_irq_handle()
1081 status &= ipu_cm_read(ipu, IPU_INT_CTRL(regs[i])); in ipu_irq_handle()
1084 irq = irq_linear_revmap(ipu->domain, in ipu_irq_handle()
1094 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_irq_handler() local
1100 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_irq_handler()
1107 struct ipu_soc *ipu = irq_desc_get_handler_data(desc); in ipu_err_irq_handler() local
1113 ipu_irq_handle(ipu, int_reg, ARRAY_SIZE(int_reg)); in ipu_err_irq_handler()
1118 int ipu_map_irq(struct ipu_soc *ipu, int irq) in ipu_map_irq() argument
1122 virq = irq_linear_revmap(ipu->domain, irq); in ipu_map_irq()
1124 virq = irq_create_mapping(ipu->domain, irq); in ipu_map_irq()
1130 int ipu_idmac_channel_irq(struct ipu_soc *ipu, struct ipuv3_channel *channel, in ipu_idmac_channel_irq() argument
1133 return ipu_map_irq(ipu, irq_type + channel->num); in ipu_idmac_channel_irq()
1137 static void ipu_submodules_exit(struct ipu_soc *ipu) in ipu_submodules_exit() argument
1139 ipu_smfc_exit(ipu); in ipu_submodules_exit()
1140 ipu_dp_exit(ipu); in ipu_submodules_exit()
1141 ipu_dmfc_exit(ipu); in ipu_submodules_exit()
1142 ipu_dc_exit(ipu); in ipu_submodules_exit()
1143 ipu_di_exit(ipu, 1); in ipu_submodules_exit()
1144 ipu_di_exit(ipu, 0); in ipu_submodules_exit()
1145 ipu_image_convert_exit(ipu); in ipu_submodules_exit()
1146 ipu_vdi_exit(ipu); in ipu_submodules_exit()
1147 ipu_ic_exit(ipu); in ipu_submodules_exit()
1148 ipu_csi_exit(ipu, 1); in ipu_submodules_exit()
1149 ipu_csi_exit(ipu, 0); in ipu_submodules_exit()
1150 ipu_cpmem_exit(ipu); in ipu_submodules_exit()
1212 static int ipu_add_client_devices(struct ipu_soc *ipu, unsigned long ipu_base) in ipu_add_client_devices() argument
1214 struct device *dev = ipu->dev; in ipu_add_client_devices()
1266 static int ipu_irq_init(struct ipu_soc *ipu) in ipu_irq_init() argument
1282 ipu->domain = irq_domain_add_linear(ipu->dev->of_node, IPU_NUM_IRQS, in ipu_irq_init()
1283 &irq_generic_chip_ops, ipu); in ipu_irq_init()
1284 if (!ipu->domain) { in ipu_irq_init()
1285 dev_err(ipu->dev, "failed to add irq domain\n"); in ipu_irq_init()
1289 ret = irq_alloc_domain_generic_chips(ipu->domain, 32, 1, "IPU", in ipu_irq_init()
1292 dev_err(ipu->dev, "failed to alloc generic irq chips\n"); in ipu_irq_init()
1293 irq_domain_remove(ipu->domain); in ipu_irq_init()
1299 ipu_cm_write(ipu, 0, IPU_INT_CTRL(i / 32)); in ipu_irq_init()
1300 ipu_cm_write(ipu, ~unused[i / 32], IPU_INT_STAT(i / 32)); in ipu_irq_init()
1304 gc = irq_get_domain_generic_chip(ipu->domain, i); in ipu_irq_init()
1305 gc->reg_base = ipu->cm_reg; in ipu_irq_init()
1315 irq_set_chained_handler_and_data(ipu->irq_sync, ipu_irq_handler, ipu); in ipu_irq_init()
1316 irq_set_chained_handler_and_data(ipu->irq_err, ipu_err_irq_handler, in ipu_irq_init()
1317 ipu); in ipu_irq_init()
1322 static void ipu_irq_exit(struct ipu_soc *ipu) in ipu_irq_exit() argument
1326 irq_set_chained_handler_and_data(ipu->irq_err, NULL, NULL); in ipu_irq_exit()
1327 irq_set_chained_handler_and_data(ipu->irq_sync, NULL, NULL); in ipu_irq_exit()
1332 irq = irq_linear_revmap(ipu->domain, i); in ipu_irq_exit()
1337 irq_domain_remove(ipu->domain); in ipu_irq_exit()
1340 void ipu_dump(struct ipu_soc *ipu) in ipu_dump() argument
1344 dev_dbg(ipu->dev, "IPU_CONF = \t0x%08X\n", in ipu_dump()
1345 ipu_cm_read(ipu, IPU_CONF)); in ipu_dump()
1346 dev_dbg(ipu->dev, "IDMAC_CONF = \t0x%08X\n", in ipu_dump()
1347 ipu_idmac_read(ipu, IDMAC_CONF)); in ipu_dump()
1348 dev_dbg(ipu->dev, "IDMAC_CHA_EN1 = \t0x%08X\n", in ipu_dump()
1349 ipu_idmac_read(ipu, IDMAC_CHA_EN(0))); in ipu_dump()
1350 dev_dbg(ipu->dev, "IDMAC_CHA_EN2 = \t0x%08X\n", in ipu_dump()
1351 ipu_idmac_read(ipu, IDMAC_CHA_EN(32))); in ipu_dump()
1352 dev_dbg(ipu->dev, "IDMAC_CHA_PRI1 = \t0x%08X\n", in ipu_dump()
1353 ipu_idmac_read(ipu, IDMAC_CHA_PRI(0))); in ipu_dump()
1354 dev_dbg(ipu->dev, "IDMAC_CHA_PRI2 = \t0x%08X\n", in ipu_dump()
1355 ipu_idmac_read(ipu, IDMAC_CHA_PRI(32))); in ipu_dump()
1356 dev_dbg(ipu->dev, "IDMAC_BAND_EN1 = \t0x%08X\n", in ipu_dump()
1357 ipu_idmac_read(ipu, IDMAC_BAND_EN(0))); in ipu_dump()
1358 dev_dbg(ipu->dev, "IDMAC_BAND_EN2 = \t0x%08X\n", in ipu_dump()
1359 ipu_idmac_read(ipu, IDMAC_BAND_EN(32))); in ipu_dump()
1360 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL0 = \t0x%08X\n", in ipu_dump()
1361 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(0))); in ipu_dump()
1362 dev_dbg(ipu->dev, "IPU_CHA_DB_MODE_SEL1 = \t0x%08X\n", in ipu_dump()
1363 ipu_cm_read(ipu, IPU_CHA_DB_MODE_SEL(32))); in ipu_dump()
1364 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW1 = \t0x%08X\n", in ipu_dump()
1365 ipu_cm_read(ipu, IPU_FS_PROC_FLOW1)); in ipu_dump()
1366 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW2 = \t0x%08X\n", in ipu_dump()
1367 ipu_cm_read(ipu, IPU_FS_PROC_FLOW2)); in ipu_dump()
1368 dev_dbg(ipu->dev, "IPU_FS_PROC_FLOW3 = \t0x%08X\n", in ipu_dump()
1369 ipu_cm_read(ipu, IPU_FS_PROC_FLOW3)); in ipu_dump()
1370 dev_dbg(ipu->dev, "IPU_FS_DISP_FLOW1 = \t0x%08X\n", in ipu_dump()
1371 ipu_cm_read(ipu, IPU_FS_DISP_FLOW1)); in ipu_dump()
1373 dev_dbg(ipu->dev, "IPU_INT_CTRL(%d) = \t%08X\n", i, in ipu_dump()
1374 ipu_cm_read(ipu, IPU_INT_CTRL(i))); in ipu_dump()
1381 struct ipu_soc *ipu; in ipu_probe() local
1403 ipu = devm_kzalloc(&pdev->dev, sizeof(*ipu), GFP_KERNEL); in ipu_probe()
1404 if (!ipu) in ipu_probe()
1407 ipu->id = of_alias_get_id(np, "ipu"); in ipu_probe()
1408 if (ipu->id < 0) in ipu_probe()
1409 ipu->id = 0; in ipu_probe()
1411 if (of_device_is_compatible(np, "fsl,imx6qp-ipu") && in ipu_probe()
1413 ipu->prg_priv = ipu_prg_lookup_by_phandle(&pdev->dev, in ipu_probe()
1414 "fsl,prg", ipu->id); in ipu_probe()
1415 if (!ipu->prg_priv) in ipu_probe()
1419 ipu->devtype = devtype; in ipu_probe()
1420 ipu->ipu_type = devtype->type; in ipu_probe()
1422 spin_lock_init(&ipu->lock); in ipu_probe()
1423 mutex_init(&ipu->channel_lock); in ipu_probe()
1424 INIT_LIST_HEAD(&ipu->channels); in ipu_probe()
1455 ipu->cm_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1457 ipu->idmac_reg = devm_ioremap(&pdev->dev, in ipu_probe()
1461 if (!ipu->cm_reg || !ipu->idmac_reg) in ipu_probe()
1464 ipu->clk = devm_clk_get(&pdev->dev, "bus"); in ipu_probe()
1465 if (IS_ERR(ipu->clk)) { in ipu_probe()
1466 ret = PTR_ERR(ipu->clk); in ipu_probe()
1471 platform_set_drvdata(pdev, ipu); in ipu_probe()
1473 ret = clk_prepare_enable(ipu->clk); in ipu_probe()
1479 ipu->dev = &pdev->dev; in ipu_probe()
1480 ipu->irq_sync = irq_sync; in ipu_probe()
1481 ipu->irq_err = irq_err; in ipu_probe()
1488 ret = ipu_memory_reset(ipu); in ipu_probe()
1492 ret = ipu_irq_init(ipu); in ipu_probe()
1497 ipu_cm_write(ipu, 0x00400000L | (IPU_MCU_T_DEFAULT << 18), in ipu_probe()
1500 ret = ipu_submodules_init(ipu, pdev, ipu_base, ipu->clk); in ipu_probe()
1504 ret = ipu_add_client_devices(ipu, ipu_base); in ipu_probe()
1516 ipu_submodules_exit(ipu); in ipu_probe()
1518 ipu_irq_exit(ipu); in ipu_probe()
1521 clk_disable_unprepare(ipu->clk); in ipu_probe()
1527 struct ipu_soc *ipu = platform_get_drvdata(pdev); in ipu_remove() local
1530 ipu_submodules_exit(ipu); in ipu_remove()
1531 ipu_irq_exit(ipu); in ipu_remove()
1533 clk_disable_unprepare(ipu->clk); in ipu_remove()
1568 MODULE_DESCRIPTION("i.MX IPU v3 driver");