Lines Matching +full:0 +full:- +full:1
4 * Copyright (c) 2006-2008 Hans de Goede <hdegoede@redhat.com>
38 #include <linux/hwmon-sysfs.h>
43 #define ABIT_UGURU3_SETTINGS_BANK 0x01
44 #define ABIT_UGURU3_SENSORS_BANK 0x08
45 #define ABIT_UGURU3_MISC_BANK 0x09
46 #define ABIT_UGURU3_ALARMS_START 0x1E
47 #define ABIT_UGURU3_SETTINGS_START 0x24
48 #define ABIT_UGURU3_VALUES_START 0x80
49 #define ABIT_UGURU3_BOARD_ID 0x0A
51 #define ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE 0x01 /* temp over warn */
52 #define ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE 0x02 /* volt over max */
53 #define ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE 0x04 /* volt under min */
54 #define ABIT_UGURU3_TEMP_HIGH_ALARM_FLAG 0x10 /* temp is over warn */
55 #define ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG 0x20 /* volt is over max */
56 #define ABIT_UGURU3_VOLT_LOW_ALARM_FLAG 0x40 /* volt is under min */
57 #define ABIT_UGURU3_FAN_LOW_ALARM_ENABLE 0x01 /* fan under min */
58 #define ABIT_UGURU3_BEEP_ENABLE 0x08 /* beep if alarm */
59 #define ABIT_UGURU3_SHUTDOWN_ENABLE 0x80 /* shutdown if alarm */
61 #define ABIT_UGURU3_IN_SENSOR 0
62 #define ABIT_UGURU3_TEMP_SENSOR 1
68 * cpu-speed independent, since the ISA-bus and not the CPU should be the
73 * Normally the 0xAC at the end of synchronize() is reported after the
83 } while (0)
88 * sum of strlen +1 of: in??_input\0, in??_{min,max}\0, in??_{min,max}_alarm\0,
89 * in??_{min,max}_alarm_enable\0, in??_beep\0, in??_shutdown\0, in??_label\0
94 * sum of strlen +1 of: temp??_input\0, temp??_max\0, temp??_crit\0,
95 * temp??_alarm\0, temp??_alarm_enable\0, temp??_beep\0, temp??_shutdown\0,
96 * temp??_label\0
100 * sum of strlen +1 of: fan??_input\0, fan??_min\0, fan??_alarm\0,
101 * fan??_alarm_enable\0, fan??_beep\0, fan??_shutdown\0, fan??_label\0
109 (ABIT_UGURU3_MAX_NO_SENSORS - 16) * ABIT_UGURU3_TEMP_NAMES_LENGTH)
117 /* Two i/o-ports are used by uGuru */
118 #define ABIT_UGURU3_BASE 0x00E0
119 #define ABIT_UGURU3_CMD 0x00
120 #define ABIT_UGURU3_DATA 0x04
124 * of the DATA register (0-255) on failure.
126 #define ABIT_UGURU3_SUCCESS -1
128 #define ABIT_UGURU3_STATUS_READY_FOR_READ 0x01
129 #define ABIT_UGURU3_STATUS_BUSY 0x02
147 const char *dmi_name[ABIT_UGURU3_MAX_DMI_NAMES + 1];
148 /* + 1 -> end of sensors indicated by a sensor with name == NULL */
149 struct abituguru3_sensor_info sensors[ABIT_UGURU3_MAX_NO_SENSORS + 1];
161 char valid; /* !=0 if following fields are valid */
183 /* Alarms for all 48 sensors (1 bit per sensor) */
200 { 0x000C, { NULL } /* Unknown, need DMI string */, {
201 { "CPU Core", 0, 0, 10, 1, 0 },
202 { "DDR", 1, 0, 10, 1, 0 },
203 { "DDR VTT", 2, 0, 10, 1, 0 },
204 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
205 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
206 { "MCH 2.5V", 5, 0, 20, 1, 0 },
207 { "ICH 1.05V", 6, 0, 10, 1, 0 },
208 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
209 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
210 { "ATX +5V", 9, 0, 30, 1, 0 },
211 { "+3.3V", 10, 0, 20, 1, 0 },
212 { "5VSB", 11, 0, 30, 1, 0 },
213 { "CPU", 24, 1, 1, 1, 0 },
214 { "System", 25, 1, 1, 1, 0 },
215 { "PWM", 26, 1, 1, 1, 0 },
216 { "CPU Fan", 32, 2, 60, 1, 0 },
217 { "NB Fan", 33, 2, 60, 1, 0 },
218 { "SYS FAN", 34, 2, 60, 1, 0 },
219 { "AUX1 Fan", 35, 2, 60, 1, 0 },
220 { NULL, 0, 0, 0, 0, 0 } }
222 { 0x000D, { NULL } /* Abit AW8, need DMI string */, {
223 { "CPU Core", 0, 0, 10, 1, 0 },
224 { "DDR", 1, 0, 10, 1, 0 },
225 { "DDR VTT", 2, 0, 10, 1, 0 },
226 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
227 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
228 { "MCH 2.5V", 5, 0, 20, 1, 0 },
229 { "ICH 1.05V", 6, 0, 10, 1, 0 },
230 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
231 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
232 { "ATX +5V", 9, 0, 30, 1, 0 },
233 { "+3.3V", 10, 0, 20, 1, 0 },
234 { "5VSB", 11, 0, 30, 1, 0 },
235 { "CPU", 24, 1, 1, 1, 0 },
236 { "System", 25, 1, 1, 1, 0 },
237 { "PWM1", 26, 1, 1, 1, 0 },
238 { "PWM2", 27, 1, 1, 1, 0 },
239 { "PWM3", 28, 1, 1, 1, 0 },
240 { "PWM4", 29, 1, 1, 1, 0 },
241 { "CPU Fan", 32, 2, 60, 1, 0 },
242 { "NB Fan", 33, 2, 60, 1, 0 },
243 { "SYS Fan", 34, 2, 60, 1, 0 },
244 { "AUX1 Fan", 35, 2, 60, 1, 0 },
245 { "AUX2 Fan", 36, 2, 60, 1, 0 },
246 { "AUX3 Fan", 37, 2, 60, 1, 0 },
247 { "AUX4 Fan", 38, 2, 60, 1, 0 },
248 { "AUX5 Fan", 39, 2, 60, 1, 0 },
249 { NULL, 0, 0, 0, 0, 0 } }
251 { 0x000E, { NULL } /* AL-8, need DMI string */, {
252 { "CPU Core", 0, 0, 10, 1, 0 },
253 { "DDR", 1, 0, 10, 1, 0 },
254 { "DDR VTT", 2, 0, 10, 1, 0 },
255 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
256 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
257 { "MCH 2.5V", 5, 0, 20, 1, 0 },
258 { "ICH 1.05V", 6, 0, 10, 1, 0 },
259 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
260 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
261 { "ATX +5V", 9, 0, 30, 1, 0 },
262 { "+3.3V", 10, 0, 20, 1, 0 },
263 { "5VSB", 11, 0, 30, 1, 0 },
264 { "CPU", 24, 1, 1, 1, 0 },
265 { "System", 25, 1, 1, 1, 0 },
266 { "PWM", 26, 1, 1, 1, 0 },
267 { "CPU Fan", 32, 2, 60, 1, 0 },
268 { "NB Fan", 33, 2, 60, 1, 0 },
269 { "SYS Fan", 34, 2, 60, 1, 0 },
270 { NULL, 0, 0, 0, 0, 0 } }
272 { 0x000F, { NULL } /* Unknown, need DMI string */, {
274 { "CPU Core", 0, 0, 10, 1, 0 },
275 { "DDR", 1, 0, 10, 1, 0 },
276 { "DDR VTT", 2, 0, 10, 1, 0 },
277 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
278 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
279 { "MCH 2.5V", 5, 0, 20, 1, 0 },
280 { "ICH 1.05V", 6, 0, 10, 1, 0 },
281 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
282 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
283 { "ATX +5V", 9, 0, 30, 1, 0 },
284 { "+3.3V", 10, 0, 20, 1, 0 },
285 { "5VSB", 11, 0, 30, 1, 0 },
286 { "CPU", 24, 1, 1, 1, 0 },
287 { "System", 25, 1, 1, 1, 0 },
288 { "PWM", 26, 1, 1, 1, 0 },
289 { "CPU Fan", 32, 2, 60, 1, 0 },
290 { "NB Fan", 33, 2, 60, 1, 0 },
291 { "SYS Fan", 34, 2, 60, 1, 0 },
292 { NULL, 0, 0, 0, 0, 0 } }
294 { 0x0010, { NULL } /* Abit NI8 SLI GR, need DMI string */, {
295 { "CPU Core", 0, 0, 10, 1, 0 },
296 { "DDR", 1, 0, 10, 1, 0 },
297 { "DDR VTT", 2, 0, 10, 1, 0 },
298 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
299 { "NB 1.4V", 4, 0, 10, 1, 0 },
300 { "SB 1.5V", 6, 0, 10, 1, 0 },
301 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
302 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
303 { "ATX +5V", 9, 0, 30, 1, 0 },
304 { "+3.3V", 10, 0, 20, 1, 0 },
305 { "5VSB", 11, 0, 30, 1, 0 },
306 { "CPU", 24, 1, 1, 1, 0 },
307 { "SYS", 25, 1, 1, 1, 0 },
308 { "PWM", 26, 1, 1, 1, 0 },
309 { "CPU Fan", 32, 2, 60, 1, 0 },
310 { "NB Fan", 33, 2, 60, 1, 0 },
311 { "SYS Fan", 34, 2, 60, 1, 0 },
312 { "AUX1 Fan", 35, 2, 60, 1, 0 },
313 { "OTES1 Fan", 36, 2, 60, 1, 0 },
314 { NULL, 0, 0, 0, 0, 0 } }
316 { 0x0011, { "AT8 32X", NULL }, {
317 { "CPU Core", 0, 0, 10, 1, 0 },
318 { "DDR", 1, 0, 20, 1, 0 },
319 { "DDR VTT", 2, 0, 10, 1, 0 },
320 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
321 { "NB 1.8V", 4, 0, 10, 1, 0 },
322 { "NB 1.8V Dual", 5, 0, 10, 1, 0 },
323 { "HTV 1.2", 3, 0, 10, 1, 0 },
324 { "PCIE 1.2V", 12, 0, 10, 1, 0 },
325 { "NB 1.2V", 13, 0, 10, 1, 0 },
326 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
327 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
328 { "ATX +5V", 9, 0, 30, 1, 0 },
329 { "+3.3V", 10, 0, 20, 1, 0 },
330 { "5VSB", 11, 0, 30, 1, 0 },
331 { "CPU", 24, 1, 1, 1, 0 },
332 { "NB", 25, 1, 1, 1, 0 },
333 { "System", 26, 1, 1, 1, 0 },
334 { "PWM", 27, 1, 1, 1, 0 },
335 { "CPU Fan", 32, 2, 60, 1, 0 },
336 { "NB Fan", 33, 2, 60, 1, 0 },
337 { "SYS Fan", 34, 2, 60, 1, 0 },
338 { "AUX1 Fan", 35, 2, 60, 1, 0 },
339 { "AUX2 Fan", 36, 2, 60, 1, 0 },
340 { "AUX3 Fan", 37, 2, 60, 1, 0 },
341 { NULL, 0, 0, 0, 0, 0 } }
343 { 0x0012, { NULL } /* Abit AN8 32X, need DMI string */, {
344 { "CPU Core", 0, 0, 10, 1, 0 },
345 { "DDR", 1, 0, 20, 1, 0 },
346 { "DDR VTT", 2, 0, 10, 1, 0 },
347 { "HyperTransport", 3, 0, 10, 1, 0 },
348 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
349 { "NB", 4, 0, 10, 1, 0 },
350 { "SB", 6, 0, 10, 1, 0 },
351 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
352 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
353 { "ATX +5V", 9, 0, 30, 1, 0 },
354 { "+3.3V", 10, 0, 20, 1, 0 },
355 { "5VSB", 11, 0, 30, 1, 0 },
356 { "CPU", 24, 1, 1, 1, 0 },
357 { "SYS", 25, 1, 1, 1, 0 },
358 { "PWM", 26, 1, 1, 1, 0 },
359 { "CPU Fan", 32, 2, 60, 1, 0 },
360 { "NB Fan", 33, 2, 60, 1, 0 },
361 { "SYS Fan", 34, 2, 60, 1, 0 },
362 { "AUX1 Fan", 36, 2, 60, 1, 0 },
363 { NULL, 0, 0, 0, 0, 0 } }
365 { 0x0013, { NULL } /* Abit AW8D, need DMI string */, {
366 { "CPU Core", 0, 0, 10, 1, 0 },
367 { "DDR", 1, 0, 10, 1, 0 },
368 { "DDR VTT", 2, 0, 10, 1, 0 },
369 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
370 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
371 { "MCH 2.5V", 5, 0, 20, 1, 0 },
372 { "ICH 1.05V", 6, 0, 10, 1, 0 },
373 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
374 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
375 { "ATX +5V", 9, 0, 30, 1, 0 },
376 { "+3.3V", 10, 0, 20, 1, 0 },
377 { "5VSB", 11, 0, 30, 1, 0 },
378 { "CPU", 24, 1, 1, 1, 0 },
379 { "System", 25, 1, 1, 1, 0 },
380 { "PWM1", 26, 1, 1, 1, 0 },
381 { "PWM2", 27, 1, 1, 1, 0 },
382 { "PWM3", 28, 1, 1, 1, 0 },
383 { "PWM4", 29, 1, 1, 1, 0 },
384 { "CPU Fan", 32, 2, 60, 1, 0 },
385 { "NB Fan", 33, 2, 60, 1, 0 },
386 { "SYS Fan", 34, 2, 60, 1, 0 },
387 { "AUX1 Fan", 35, 2, 60, 1, 0 },
388 { "AUX2 Fan", 36, 2, 60, 1, 0 },
389 { "AUX3 Fan", 37, 2, 60, 1, 0 },
390 { "AUX4 Fan", 38, 2, 60, 1, 0 },
391 { "AUX5 Fan", 39, 2, 60, 1, 0 },
392 { NULL, 0, 0, 0, 0, 0 } }
394 { 0x0014, { "AB9", "AB9 Pro", NULL }, {
395 { "CPU Core", 0, 0, 10, 1, 0 },
396 { "DDR", 1, 0, 10, 1, 0 },
397 { "DDR VTT", 2, 0, 10, 1, 0 },
398 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
399 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
400 { "MCH 2.5V", 5, 0, 20, 1, 0 },
401 { "ICH 1.05V", 6, 0, 10, 1, 0 },
402 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
403 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
404 { "ATX +5V", 9, 0, 30, 1, 0 },
405 { "+3.3V", 10, 0, 20, 1, 0 },
406 { "5VSB", 11, 0, 30, 1, 0 },
407 { "CPU", 24, 1, 1, 1, 0 },
408 { "System", 25, 1, 1, 1, 0 },
409 { "PWM", 26, 1, 1, 1, 0 },
410 { "CPU Fan", 32, 2, 60, 1, 0 },
411 { "NB Fan", 33, 2, 60, 1, 0 },
412 { "SYS Fan", 34, 2, 60, 1, 0 },
413 { NULL, 0, 0, 0, 0, 0 } }
415 { 0x0015, { NULL } /* Unknown, need DMI string */, {
416 { "CPU Core", 0, 0, 10, 1, 0 },
417 { "DDR", 1, 0, 20, 1, 0 },
418 { "DDR VTT", 2, 0, 10, 1, 0 },
419 { "HyperTransport", 3, 0, 10, 1, 0 },
420 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
421 { "NB", 4, 0, 10, 1, 0 },
422 { "SB", 6, 0, 10, 1, 0 },
423 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
424 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
425 { "ATX +5V", 9, 0, 30, 1, 0 },
426 { "+3.3V", 10, 0, 20, 1, 0 },
427 { "5VSB", 11, 0, 30, 1, 0 },
428 { "CPU", 24, 1, 1, 1, 0 },
429 { "SYS", 25, 1, 1, 1, 0 },
430 { "PWM", 26, 1, 1, 1, 0 },
431 { "CPU Fan", 32, 2, 60, 1, 0 },
432 { "NB Fan", 33, 2, 60, 1, 0 },
433 { "SYS Fan", 34, 2, 60, 1, 0 },
434 { "AUX1 Fan", 33, 2, 60, 1, 0 },
435 { "AUX2 Fan", 35, 2, 60, 1, 0 },
436 { "AUX3 Fan", 36, 2, 60, 1, 0 },
437 { NULL, 0, 0, 0, 0, 0 } }
439 { 0x0016, { "AW9D-MAX", NULL }, {
440 { "CPU Core", 0, 0, 10, 1, 0 },
441 { "DDR2", 1, 0, 20, 1, 0 },
442 { "DDR2 VTT", 2, 0, 10, 1, 0 },
443 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
444 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
445 { "MCH 2.5V", 5, 0, 20, 1, 0 },
446 { "ICH 1.05V", 6, 0, 10, 1, 0 },
447 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
448 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
449 { "ATX +5V", 9, 0, 30, 1, 0 },
450 { "+3.3V", 10, 0, 20, 1, 0 },
451 { "5VSB", 11, 0, 30, 1, 0 },
452 { "CPU", 24, 1, 1, 1, 0 },
453 { "System", 25, 1, 1, 1, 0 },
454 { "PWM1", 26, 1, 1, 1, 0 },
455 { "PWM2", 27, 1, 1, 1, 0 },
456 { "PWM3", 28, 1, 1, 1, 0 },
457 { "PWM4", 29, 1, 1, 1, 0 },
458 { "CPU Fan", 32, 2, 60, 1, 0 },
459 { "NB Fan", 33, 2, 60, 1, 0 },
460 { "SYS Fan", 34, 2, 60, 1, 0 },
461 { "AUX1 Fan", 35, 2, 60, 1, 0 },
462 { "AUX2 Fan", 36, 2, 60, 1, 0 },
463 { "AUX3 Fan", 37, 2, 60, 1, 0 },
464 { "OTES1 Fan", 38, 2, 60, 1, 0 },
465 { NULL, 0, 0, 0, 0, 0 } }
467 { 0x0017, { NULL } /* Unknown, need DMI string */, {
468 { "CPU Core", 0, 0, 10, 1, 0 },
469 { "DDR2", 1, 0, 20, 1, 0 },
470 { "DDR2 VTT", 2, 0, 10, 1, 0 },
471 { "HyperTransport", 3, 0, 10, 1, 0 },
472 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
473 { "NB 1.8V", 4, 0, 10, 1, 0 },
474 { "NB 1.2V ", 13, 0, 10, 1, 0 },
475 { "SB 1.2V", 5, 0, 10, 1, 0 },
476 { "PCIE 1.2V", 12, 0, 10, 1, 0 },
477 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
478 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
479 { "ATX +5V", 9, 0, 30, 1, 0 },
480 { "ATX +3.3V", 10, 0, 20, 1, 0 },
481 { "ATX 5VSB", 11, 0, 30, 1, 0 },
482 { "CPU", 24, 1, 1, 1, 0 },
483 { "System", 26, 1, 1, 1, 0 },
484 { "PWM", 27, 1, 1, 1, 0 },
485 { "CPU FAN", 32, 2, 60, 1, 0 },
486 { "SYS FAN", 34, 2, 60, 1, 0 },
487 { "AUX1 FAN", 35, 2, 60, 1, 0 },
488 { "AUX2 FAN", 36, 2, 60, 1, 0 },
489 { "AUX3 FAN", 37, 2, 60, 1, 0 },
490 { NULL, 0, 0, 0, 0, 0 } }
492 { 0x0018, { "AB9 QuadGT", NULL }, {
493 { "CPU Core", 0, 0, 10, 1, 0 },
494 { "DDR2", 1, 0, 20, 1, 0 },
495 { "DDR2 VTT", 2, 0, 10, 1, 0 },
496 { "CPU VTT", 3, 0, 10, 1, 0 },
497 { "MCH 1.25V", 4, 0, 10, 1, 0 },
498 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
499 { "ICH 1.05V", 6, 0, 10, 1, 0 },
500 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
501 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
502 { "ATX +5V", 9, 0, 30, 1, 0 },
503 { "+3.3V", 10, 0, 20, 1, 0 },
504 { "5VSB", 11, 0, 30, 1, 0 },
505 { "CPU", 24, 1, 1, 1, 0 },
506 { "System", 25, 1, 1, 1, 0 },
507 { "PWM Phase1", 26, 1, 1, 1, 0 },
508 { "PWM Phase2", 27, 1, 1, 1, 0 },
509 { "PWM Phase3", 28, 1, 1, 1, 0 },
510 { "PWM Phase4", 29, 1, 1, 1, 0 },
511 { "PWM Phase5", 30, 1, 1, 1, 0 },
512 { "CPU Fan", 32, 2, 60, 1, 0 },
513 { "SYS Fan", 34, 2, 60, 1, 0 },
514 { "AUX1 Fan", 33, 2, 60, 1, 0 },
515 { "AUX2 Fan", 35, 2, 60, 1, 0 },
516 { "AUX3 Fan", 36, 2, 60, 1, 0 },
517 { NULL, 0, 0, 0, 0, 0 } }
519 { 0x0019, { "IN9 32X MAX", NULL }, {
520 { "CPU Core", 7, 0, 10, 1, 0 },
521 { "DDR2", 13, 0, 20, 1, 0 },
522 { "DDR2 VTT", 14, 0, 10, 1, 0 },
523 { "CPU VTT", 3, 0, 20, 1, 0 },
524 { "NB 1.2V", 4, 0, 10, 1, 0 },
525 { "SB 1.5V", 6, 0, 10, 1, 0 },
526 { "HyperTransport", 5, 0, 10, 1, 0 },
527 { "ATX +12V (24-Pin)", 12, 0, 60, 1, 0 },
528 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
529 { "ATX +5V", 9, 0, 30, 1, 0 },
530 { "ATX +3.3V", 10, 0, 20, 1, 0 },
531 { "ATX 5VSB", 11, 0, 30, 1, 0 },
532 { "CPU", 24, 1, 1, 1, 0 },
533 { "System", 25, 1, 1, 1, 0 },
534 { "PWM Phase1", 26, 1, 1, 1, 0 },
535 { "PWM Phase2", 27, 1, 1, 1, 0 },
536 { "PWM Phase3", 28, 1, 1, 1, 0 },
537 { "PWM Phase4", 29, 1, 1, 1, 0 },
538 { "PWM Phase5", 30, 1, 1, 1, 0 },
539 { "CPU FAN", 32, 2, 60, 1, 0 },
540 { "SYS FAN", 34, 2, 60, 1, 0 },
541 { "AUX1 FAN", 33, 2, 60, 1, 0 },
542 { "AUX2 FAN", 35, 2, 60, 1, 0 },
543 { "AUX3 FAN", 36, 2, 60, 1, 0 },
544 { NULL, 0, 0, 0, 0, 0 } }
546 { 0x001A, { "IP35 Pro", "IP35 Pro XE", NULL }, {
547 { "CPU Core", 0, 0, 10, 1, 0 },
548 { "DDR2", 1, 0, 20, 1, 0 },
549 { "DDR2 VTT", 2, 0, 10, 1, 0 },
550 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
551 { "MCH 1.25V", 4, 0, 10, 1, 0 },
552 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
553 { "ICH 1.05V", 6, 0, 10, 1, 0 },
554 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
555 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
556 { "ATX +5V", 9, 0, 30, 1, 0 },
557 { "+3.3V", 10, 0, 20, 1, 0 },
558 { "5VSB", 11, 0, 30, 1, 0 },
559 { "CPU", 24, 1, 1, 1, 0 },
560 { "System", 25, 1, 1, 1, 0 },
561 { "PWM", 26, 1, 1, 1, 0 },
562 { "PWM Phase2", 27, 1, 1, 1, 0 },
563 { "PWM Phase3", 28, 1, 1, 1, 0 },
564 { "PWM Phase4", 29, 1, 1, 1, 0 },
565 { "PWM Phase5", 30, 1, 1, 1, 0 },
566 { "CPU Fan", 32, 2, 60, 1, 0 },
567 { "SYS Fan", 34, 2, 60, 1, 0 },
568 { "AUX1 Fan", 33, 2, 60, 1, 0 },
569 { "AUX2 Fan", 35, 2, 60, 1, 0 },
570 { "AUX3 Fan", 36, 2, 60, 1, 0 },
571 { "AUX4 Fan", 37, 2, 60, 1, 0 },
572 { NULL, 0, 0, 0, 0, 0 } }
574 { 0x001B, { NULL } /* Unknown, need DMI string */, {
575 { "CPU Core", 0, 0, 10, 1, 0 },
576 { "DDR3", 1, 0, 20, 1, 0 },
577 { "DDR3 VTT", 2, 0, 10, 1, 0 },
578 { "CPU VTT", 3, 0, 10, 1, 0 },
579 { "MCH 1.25V", 4, 0, 10, 1, 0 },
580 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
581 { "ICH 1.05V", 6, 0, 10, 1, 0 },
582 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
583 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
584 { "ATX +5V", 9, 0, 30, 1, 0 },
585 { "+3.3V", 10, 0, 20, 1, 0 },
586 { "5VSB", 11, 0, 30, 1, 0 },
587 { "CPU", 24, 1, 1, 1, 0 },
588 { "System", 25, 1, 1, 1, 0 },
589 { "PWM Phase1", 26, 1, 1, 1, 0 },
590 { "PWM Phase2", 27, 1, 1, 1, 0 },
591 { "PWM Phase3", 28, 1, 1, 1, 0 },
592 { "PWM Phase4", 29, 1, 1, 1, 0 },
593 { "PWM Phase5", 30, 1, 1, 1, 0 },
594 { "CPU Fan", 32, 2, 60, 1, 0 },
595 { "SYS Fan", 34, 2, 60, 1, 0 },
596 { "AUX1 Fan", 33, 2, 60, 1, 0 },
597 { "AUX2 Fan", 35, 2, 60, 1, 0 },
598 { "AUX3 Fan", 36, 2, 60, 1, 0 },
599 { NULL, 0, 0, 0, 0, 0 } }
601 { 0x001C, { "IX38 QuadGT", NULL }, {
602 { "CPU Core", 0, 0, 10, 1, 0 },
603 { "DDR2", 1, 0, 20, 1, 0 },
604 { "DDR2 VTT", 2, 0, 10, 1, 0 },
605 { "CPU VTT", 3, 0, 10, 1, 0 },
606 { "MCH 1.25V", 4, 0, 10, 1, 0 },
607 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
608 { "ICH 1.05V", 6, 0, 10, 1, 0 },
609 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
610 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
611 { "ATX +5V", 9, 0, 30, 1, 0 },
612 { "+3.3V", 10, 0, 20, 1, 0 },
613 { "5VSB", 11, 0, 30, 1, 0 },
614 { "CPU", 24, 1, 1, 1, 0 },
615 { "System", 25, 1, 1, 1, 0 },
616 { "PWM Phase1", 26, 1, 1, 1, 0 },
617 { "PWM Phase2", 27, 1, 1, 1, 0 },
618 { "PWM Phase3", 28, 1, 1, 1, 0 },
619 { "PWM Phase4", 29, 1, 1, 1, 0 },
620 { "PWM Phase5", 30, 1, 1, 1, 0 },
621 { "CPU Fan", 32, 2, 60, 1, 0 },
622 { "SYS Fan", 34, 2, 60, 1, 0 },
623 { "AUX1 Fan", 33, 2, 60, 1, 0 },
624 { "AUX2 Fan", 35, 2, 60, 1, 0 },
625 { "AUX3 Fan", 36, 2, 60, 1, 0 },
626 { NULL, 0, 0, 0, 0, 0 } }
628 { 0x0000, { NULL }, { { NULL, 0, 0, 0, 0, 0 } } }
634 module_param(force, bool, 0);
636 /* Default verbose is 1, since this driver is still in the testing phase */
637 static bool verbose = 1;
651 while ((x = inb_p(data->addr + ABIT_UGURU3_DATA)) & in abituguru3_wait_while_busy()
653 timeout--; in abituguru3_wait_while_busy()
654 if (timeout == 0) in abituguru3_wait_while_busy()
660 if (timeout == 1) in abituguru3_wait_while_busy()
661 msleep(1); in abituguru3_wait_while_busy()
672 while (!((x = inb_p(data->addr + ABIT_UGURU3_DATA)) & in abituguru3_wait_for_read()
674 timeout--; in abituguru3_wait_for_read()
675 if (timeout == 0) in abituguru3_wait_for_read()
681 if (timeout == 1) in abituguru3_wait_for_read()
682 msleep(1); in abituguru3_wait_for_read()
698 "wait, status: 0x%02x\n", x); in abituguru3_synchronize()
699 return -EIO; in abituguru3_synchronize()
702 outb(0x20, data->addr + ABIT_UGURU3_DATA); in abituguru3_synchronize()
705 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x20, " in abituguru3_synchronize()
706 "status: 0x%02x\n", x); in abituguru3_synchronize()
707 return -EIO; in abituguru3_synchronize()
710 outb(0x10, data->addr + ABIT_UGURU3_CMD); in abituguru3_synchronize()
713 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x10, " in abituguru3_synchronize()
714 "status: 0x%02x\n", x); in abituguru3_synchronize()
715 return -EIO; in abituguru3_synchronize()
718 outb(0x00, data->addr + ABIT_UGURU3_CMD); in abituguru3_synchronize()
721 ABIT_UGURU3_DEBUG("synchronize timeout after sending 0x00, " in abituguru3_synchronize()
722 "status: 0x%02x\n", x); in abituguru3_synchronize()
723 return -EIO; in abituguru3_synchronize()
729 "status: 0x%02x\n", x); in abituguru3_synchronize()
730 return -EIO; in abituguru3_synchronize()
733 while ((x = inb(data->addr + ABIT_UGURU3_CMD)) != 0xAC) { in abituguru3_synchronize()
734 timeout--; in abituguru3_synchronize()
735 if (timeout == 0) { in abituguru3_synchronize()
737 "hold 0xAC after synchronize, cmd: 0x%02x\n", in abituguru3_synchronize()
739 return -EIO; in abituguru3_synchronize()
741 msleep(1); in abituguru3_synchronize()
743 return 0; in abituguru3_synchronize()
759 outb(0x1A, data->addr + ABIT_UGURU3_DATA); in abituguru3_read()
762 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " in abituguru3_read()
763 "sending 0x1A, status: 0x%02x\n", (unsigned int)bank, in abituguru3_read()
765 return -EIO; in abituguru3_read()
768 outb(bank, data->addr + ABIT_UGURU3_CMD); in abituguru3_read()
771 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " in abituguru3_read()
772 "sending the bank, status: 0x%02x\n", in abituguru3_read()
774 return -EIO; in abituguru3_read()
777 outb(offset, data->addr + ABIT_UGURU3_CMD); in abituguru3_read()
780 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " in abituguru3_read()
781 "sending the offset, status: 0x%02x\n", in abituguru3_read()
783 return -EIO; in abituguru3_read()
786 outb(count, data->addr + ABIT_UGURU3_CMD); in abituguru3_read()
789 ABIT_UGURU3_DEBUG("read from 0x%02x:0x%02x timed out after " in abituguru3_read()
790 "sending the count, status: 0x%02x\n", in abituguru3_read()
792 return -EIO; in abituguru3_read()
795 for (i = 0; i < count; i++) { in abituguru3_read()
799 "0x%02x:0x%02x, status: 0x%02x\n", i, in abituguru3_read()
803 buf[i] = inb(data->addr + ABIT_UGURU3_CMD); in abituguru3_read()
809 * Sensor settings are stored 1 byte per offset with the bytes
818 for (i = 0; i < offset_count; i++) { in abituguru3_read_increment_offset()
822 if (x < 0) in abituguru3_read_increment_offset()
833 * sensor_device_attribute_2->index: index into the data->sensors array
834 * sensor_device_attribute_2->nr: register offset, bitmask or NA.
847 return -EIO; in show_value()
849 sensor = &data->sensors[attr->index]; in show_value()
852 if (attr->nr) in show_value()
853 value = data->settings[sensor->port][attr->nr]; in show_value()
855 value = data->value[sensor->port]; in show_value()
858 value = (value * sensor->multiplier) / sensor->divisor + in show_value()
859 sensor->offset; in show_value()
865 if (sensor->type == ABIT_UGURU3_TEMP_SENSOR) in show_value()
879 return -EIO; in show_alarm()
881 port = data->sensors[attr->index].port; in show_alarm()
885 * given in attr->nr also check if the alarm matches the type of alarm in show_alarm()
889 if ((data->alarms[port / 8] & (0x01 << (port % 8))) && in show_alarm()
890 (!attr->nr || (data->settings[port][0] & attr->nr))) in show_alarm()
891 return sprintf(buf, "1\n"); in show_alarm()
893 return sprintf(buf, "0\n"); in show_alarm()
902 if (data->settings[data->sensors[attr->index].port][0] & attr->nr) in show_mask()
903 return sprintf(buf, "1\n"); in show_mask()
905 return sprintf(buf, "0\n"); in show_mask()
914 return sprintf(buf, "%s\n", data->sensors[attr->index].name); in show_label()
926 SENSOR_ATTR_2(in%d_input, 0444, show_value, NULL, 0, 0),
927 SENSOR_ATTR_2(in%d_min, 0444, show_value, NULL, 1, 0),
928 SENSOR_ATTR_2(in%d_max, 0444, show_value, NULL, 2, 0),
930 ABIT_UGURU3_VOLT_LOW_ALARM_FLAG, 0),
932 ABIT_UGURU3_VOLT_HIGH_ALARM_FLAG, 0),
934 ABIT_UGURU3_BEEP_ENABLE, 0),
936 ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
938 ABIT_UGURU3_VOLT_LOW_ALARM_ENABLE, 0),
940 ABIT_UGURU3_VOLT_HIGH_ALARM_ENABLE, 0),
941 SENSOR_ATTR_2(in%d_label, 0444, show_label, NULL, 0, 0)
943 SENSOR_ATTR_2(temp%d_input, 0444, show_value, NULL, 0, 0),
944 SENSOR_ATTR_2(temp%d_max, 0444, show_value, NULL, 1, 0),
945 SENSOR_ATTR_2(temp%d_crit, 0444, show_value, NULL, 2, 0),
946 SENSOR_ATTR_2(temp%d_alarm, 0444, show_alarm, NULL, 0, 0),
948 ABIT_UGURU3_BEEP_ENABLE, 0),
950 ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
952 ABIT_UGURU3_TEMP_HIGH_ALARM_ENABLE, 0),
953 SENSOR_ATTR_2(temp%d_label, 0444, show_label, NULL, 0, 0)
955 SENSOR_ATTR_2(fan%d_input, 0444, show_value, NULL, 0, 0),
956 SENSOR_ATTR_2(fan%d_min, 0444, show_value, NULL, 1, 0),
957 SENSOR_ATTR_2(fan%d_alarm, 0444, show_alarm, NULL, 0, 0),
959 ABIT_UGURU3_BEEP_ENABLE, 0),
961 ABIT_UGURU3_SHUTDOWN_ENABLE, 0),
963 ABIT_UGURU3_FAN_LOW_ALARM_ENABLE, 0),
964 SENSOR_ATTR_2(fan%d_label, 0444, show_label, NULL, 0, 0)
968 SENSOR_ATTR_2(name, 0444, show_name, NULL, 0, 0),
974 int sensor_index[3] = { 0, 1, 1 }; in abituguru3_probe()
976 int i, j, type, used, sysfs_names_free, sysfs_attr_i, res = -ENODEV; in abituguru3_probe()
981 data = devm_kzalloc(&pdev->dev, sizeof(struct abituguru3_data), in abituguru3_probe()
984 return -ENOMEM; in abituguru3_probe()
986 data->addr = platform_get_resource(pdev, IORESOURCE_IO, 0)->start; in abituguru3_probe()
987 mutex_init(&data->update_lock); in abituguru3_probe()
997 if (!abituguru3_update_device(&pdev->dev)) in abituguru3_probe()
1001 id = ((u16)buf[0] << 8) | (u16)buf[1]; in abituguru3_probe()
1002 for (i = 0; abituguru3_motherboards[i].id; i++) in abituguru3_probe()
1010 data->sensors = abituguru3_motherboards[i].sensors; in abituguru3_probe()
1015 sysfs_attr_i = 0; in abituguru3_probe()
1016 sysfs_filename = data->sysfs_names; in abituguru3_probe()
1018 for (i = 0; data->sensors[i].name; i++) { in abituguru3_probe()
1023 res = -ENAMETOOLONG; in abituguru3_probe()
1026 type = data->sensors[i].type; in abituguru3_probe()
1027 for (j = 0; j < no_sysfs_attr[type]; j++) { in abituguru3_probe()
1030 name, sensor_index[type]) + 1; in abituguru3_probe()
1031 data->sysfs_attr[sysfs_attr_i] = in abituguru3_probe()
1033 data->sysfs_attr[sysfs_attr_i].dev_attr.attr.name = in abituguru3_probe()
1035 data->sysfs_attr[sysfs_attr_i].index = i; in abituguru3_probe()
1037 sysfs_names_free -= used; in abituguru3_probe()
1043 if (sysfs_names_free < 0) { in abituguru3_probe()
1046 res = -ENAMETOOLONG; in abituguru3_probe()
1051 for (i = 0; i < sysfs_attr_i; i++) in abituguru3_probe()
1052 if (device_create_file(&pdev->dev, in abituguru3_probe()
1053 &data->sysfs_attr[i].dev_attr)) in abituguru3_probe()
1055 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) in abituguru3_probe()
1056 if (device_create_file(&pdev->dev, in abituguru3_probe()
1060 data->hwmon_dev = hwmon_device_register(&pdev->dev); in abituguru3_probe()
1061 if (IS_ERR(data->hwmon_dev)) { in abituguru3_probe()
1062 res = PTR_ERR(data->hwmon_dev); in abituguru3_probe()
1066 return 0; /* success */ in abituguru3_probe()
1069 for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++) in abituguru3_probe()
1070 device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr); in abituguru3_probe()
1071 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) in abituguru3_probe()
1072 device_remove_file(&pdev->dev, in abituguru3_probe()
1082 hwmon_device_unregister(data->hwmon_dev); in abituguru3_remove()
1083 for (i = 0; data->sysfs_attr[i].dev_attr.attr.name; i++) in abituguru3_remove()
1084 device_remove_file(&pdev->dev, &data->sysfs_attr[i].dev_attr); in abituguru3_remove()
1085 for (i = 0; i < ARRAY_SIZE(abituguru3_sysfs_attr); i++) in abituguru3_remove()
1086 device_remove_file(&pdev->dev, in abituguru3_remove()
1088 return 0; in abituguru3_remove()
1096 mutex_lock(&data->update_lock); in abituguru3_update_device()
1097 if (!data->valid || time_after(jiffies, data->last_updated + HZ)) { in abituguru3_update_device()
1098 /* Clear data->valid while updating */ in abituguru3_update_device()
1099 data->valid = 0; in abituguru3_update_device()
1104 1, data->alarms, 48/8) != (48/8)) in abituguru3_update_device()
1107 for (i = 0; i < 32; i++) { in abituguru3_update_device()
1110 1, &data->value[i]) != 1) in abituguru3_update_device()
1115 1, in abituguru3_update_device()
1116 data->settings[i], 3) != 3) in abituguru3_update_device()
1120 for (i = 0; i < 16; i++) { in abituguru3_update_device()
1123 1, &data->value[32 + i]) != 1) in abituguru3_update_device()
1128 i * 2, 1, in abituguru3_update_device()
1129 data->settings[32 + i], 2) != 2) in abituguru3_update_device()
1132 data->last_updated = jiffies; in abituguru3_update_device()
1133 data->valid = 1; in abituguru3_update_device()
1136 mutex_unlock(&data->update_lock); in abituguru3_update_device()
1137 if (data->valid) in abituguru3_update_device()
1151 mutex_lock(&data->update_lock); in abituguru3_suspend()
1152 return 0; in abituguru3_suspend()
1158 mutex_unlock(&data->update_lock); in abituguru3_resume()
1159 return 0; in abituguru3_resume()
1180 int i, err = (force) ? 1 : -ENODEV; in abituguru3_dmi_detect()
1199 while (sublen > 0 && board_name[sublen - 1] == ' ') in abituguru3_dmi_detect()
1200 sublen--; in abituguru3_dmi_detect()
1202 for (i = 0; abituguru3_motherboards[i].id; i++) { in abituguru3_dmi_detect()
1208 return 0; in abituguru3_dmi_detect()
1213 return 1; in abituguru3_dmi_detect()
1224 * See if there is an uguru3 there. An idle uGuru3 will hold 0x00 or in abituguru3_detect()
1225 * 0x08 at DATA and 0xAC at CMD. Sometimes the uGuru3 will hold 0x05 in abituguru3_detect()
1226 * or 0x55 at CMD instead, why is unknown. in abituguru3_detect()
1230 if (((data_val == 0x00) || (data_val == 0x08)) && in abituguru3_detect()
1231 ((cmd_val == 0xAC) || (cmd_val == 0x05) || in abituguru3_detect()
1232 (cmd_val == 0x55))) in abituguru3_detect()
1233 return 0; in abituguru3_detect()
1235 ABIT_UGURU3_DEBUG("no Abit uGuru3 found, data = 0x%02X, cmd = " in abituguru3_detect()
1236 "0x%02X\n", (unsigned int)data_val, (unsigned int)cmd_val); in abituguru3_detect()
1240 return 0; in abituguru3_detect()
1244 return -ENODEV; in abituguru3_detect()
1256 if (err < 0) in abituguru3_init()
1263 if (err > 0) { in abituguru3_init()
1280 err = -ENOMEM; in abituguru3_init()
1285 res.end = ABIT_UGURU3_BASE + ABIT_UGURU3_REGION_LENGTH - 1; in abituguru3_init()
1288 err = platform_device_add_resources(abituguru3_pdev, &res, 1); in abituguru3_init()
1300 return 0; in abituguru3_init()