Lines Matching +full:10 +full:v
92 (11 + 2 * 9 + 2 * 15 + 2 * 22 + 10 + 14 + 11)
103 #define ABIT_UGURU3_FAN_NAMES_LENGTH (12 + 10 + 12 + 19 + 11 + 15 + 12)
166 * automatically. We have max 10 entries per sensor (for in sensors)
169 * 10];
201 { "CPU Core", 0, 0, 10, 1, 0 },
202 { "DDR", 1, 0, 10, 1, 0 },
203 { "DDR VTT", 2, 0, 10, 1, 0 },
204 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
205 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
206 { "MCH 2.5V", 5, 0, 20, 1, 0 },
207 { "ICH 1.05V", 6, 0, 10, 1, 0 },
208 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
209 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
210 { "ATX +5V", 9, 0, 30, 1, 0 },
211 { "+3.3V", 10, 0, 20, 1, 0 },
223 { "CPU Core", 0, 0, 10, 1, 0 },
224 { "DDR", 1, 0, 10, 1, 0 },
225 { "DDR VTT", 2, 0, 10, 1, 0 },
226 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
227 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
228 { "MCH 2.5V", 5, 0, 20, 1, 0 },
229 { "ICH 1.05V", 6, 0, 10, 1, 0 },
230 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
231 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
232 { "ATX +5V", 9, 0, 30, 1, 0 },
233 { "+3.3V", 10, 0, 20, 1, 0 },
252 { "CPU Core", 0, 0, 10, 1, 0 },
253 { "DDR", 1, 0, 10, 1, 0 },
254 { "DDR VTT", 2, 0, 10, 1, 0 },
255 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
256 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
257 { "MCH 2.5V", 5, 0, 20, 1, 0 },
258 { "ICH 1.05V", 6, 0, 10, 1, 0 },
259 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
260 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
261 { "ATX +5V", 9, 0, 30, 1, 0 },
262 { "+3.3V", 10, 0, 20, 1, 0 },
274 { "CPU Core", 0, 0, 10, 1, 0 },
275 { "DDR", 1, 0, 10, 1, 0 },
276 { "DDR VTT", 2, 0, 10, 1, 0 },
277 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
278 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
279 { "MCH 2.5V", 5, 0, 20, 1, 0 },
280 { "ICH 1.05V", 6, 0, 10, 1, 0 },
281 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
282 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
283 { "ATX +5V", 9, 0, 30, 1, 0 },
284 { "+3.3V", 10, 0, 20, 1, 0 },
295 { "CPU Core", 0, 0, 10, 1, 0 },
296 { "DDR", 1, 0, 10, 1, 0 },
297 { "DDR VTT", 2, 0, 10, 1, 0 },
298 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
299 { "NB 1.4V", 4, 0, 10, 1, 0 },
300 { "SB 1.5V", 6, 0, 10, 1, 0 },
301 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
302 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
303 { "ATX +5V", 9, 0, 30, 1, 0 },
304 { "+3.3V", 10, 0, 20, 1, 0 },
317 { "CPU Core", 0, 0, 10, 1, 0 },
319 { "DDR VTT", 2, 0, 10, 1, 0 },
320 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
321 { "NB 1.8V", 4, 0, 10, 1, 0 },
322 { "NB 1.8V Dual", 5, 0, 10, 1, 0 },
323 { "HTV 1.2", 3, 0, 10, 1, 0 },
324 { "PCIE 1.2V", 12, 0, 10, 1, 0 },
325 { "NB 1.2V", 13, 0, 10, 1, 0 },
326 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
327 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
328 { "ATX +5V", 9, 0, 30, 1, 0 },
329 { "+3.3V", 10, 0, 20, 1, 0 },
344 { "CPU Core", 0, 0, 10, 1, 0 },
346 { "DDR VTT", 2, 0, 10, 1, 0 },
347 { "HyperTransport", 3, 0, 10, 1, 0 },
348 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
349 { "NB", 4, 0, 10, 1, 0 },
350 { "SB", 6, 0, 10, 1, 0 },
351 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
352 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
353 { "ATX +5V", 9, 0, 30, 1, 0 },
354 { "+3.3V", 10, 0, 20, 1, 0 },
366 { "CPU Core", 0, 0, 10, 1, 0 },
367 { "DDR", 1, 0, 10, 1, 0 },
368 { "DDR VTT", 2, 0, 10, 1, 0 },
369 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
370 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
371 { "MCH 2.5V", 5, 0, 20, 1, 0 },
372 { "ICH 1.05V", 6, 0, 10, 1, 0 },
373 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
374 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
375 { "ATX +5V", 9, 0, 30, 1, 0 },
376 { "+3.3V", 10, 0, 20, 1, 0 },
395 { "CPU Core", 0, 0, 10, 1, 0 },
396 { "DDR", 1, 0, 10, 1, 0 },
397 { "DDR VTT", 2, 0, 10, 1, 0 },
398 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
399 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
400 { "MCH 2.5V", 5, 0, 20, 1, 0 },
401 { "ICH 1.05V", 6, 0, 10, 1, 0 },
402 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
403 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
404 { "ATX +5V", 9, 0, 30, 1, 0 },
405 { "+3.3V", 10, 0, 20, 1, 0 },
416 { "CPU Core", 0, 0, 10, 1, 0 },
418 { "DDR VTT", 2, 0, 10, 1, 0 },
419 { "HyperTransport", 3, 0, 10, 1, 0 },
420 { "CPU VDDA 2.5V", 5, 0, 20, 1, 0 },
421 { "NB", 4, 0, 10, 1, 0 },
422 { "SB", 6, 0, 10, 1, 0 },
423 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
424 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
425 { "ATX +5V", 9, 0, 30, 1, 0 },
426 { "+3.3V", 10, 0, 20, 1, 0 },
440 { "CPU Core", 0, 0, 10, 1, 0 },
442 { "DDR2 VTT", 2, 0, 10, 1, 0 },
443 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
444 { "MCH & PCIE 1.5V", 4, 0, 10, 1, 0 },
445 { "MCH 2.5V", 5, 0, 20, 1, 0 },
446 { "ICH 1.05V", 6, 0, 10, 1, 0 },
447 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
448 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
449 { "ATX +5V", 9, 0, 30, 1, 0 },
450 { "+3.3V", 10, 0, 20, 1, 0 },
468 { "CPU Core", 0, 0, 10, 1, 0 },
470 { "DDR2 VTT", 2, 0, 10, 1, 0 },
471 { "HyperTransport", 3, 0, 10, 1, 0 },
472 { "CPU VDDA 2.5V", 6, 0, 20, 1, 0 },
473 { "NB 1.8V", 4, 0, 10, 1, 0 },
474 { "NB 1.2V ", 13, 0, 10, 1, 0 },
475 { "SB 1.2V", 5, 0, 10, 1, 0 },
476 { "PCIE 1.2V", 12, 0, 10, 1, 0 },
477 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
478 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
479 { "ATX +5V", 9, 0, 30, 1, 0 },
480 { "ATX +3.3V", 10, 0, 20, 1, 0 },
493 { "CPU Core", 0, 0, 10, 1, 0 },
495 { "DDR2 VTT", 2, 0, 10, 1, 0 },
496 { "CPU VTT", 3, 0, 10, 1, 0 },
497 { "MCH 1.25V", 4, 0, 10, 1, 0 },
498 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
499 { "ICH 1.05V", 6, 0, 10, 1, 0 },
500 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
501 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
502 { "ATX +5V", 9, 0, 30, 1, 0 },
503 { "+3.3V", 10, 0, 20, 1, 0 },
520 { "CPU Core", 7, 0, 10, 1, 0 },
522 { "DDR2 VTT", 14, 0, 10, 1, 0 },
524 { "NB 1.2V", 4, 0, 10, 1, 0 },
525 { "SB 1.5V", 6, 0, 10, 1, 0 },
526 { "HyperTransport", 5, 0, 10, 1, 0 },
527 { "ATX +12V (24-Pin)", 12, 0, 60, 1, 0 },
528 { "ATX +12V (4-pin)", 8, 0, 60, 1, 0 },
529 { "ATX +5V", 9, 0, 30, 1, 0 },
530 { "ATX +3.3V", 10, 0, 20, 1, 0 },
547 { "CPU Core", 0, 0, 10, 1, 0 },
549 { "DDR2 VTT", 2, 0, 10, 1, 0 },
550 { "CPU VTT 1.2V", 3, 0, 10, 1, 0 },
551 { "MCH 1.25V", 4, 0, 10, 1, 0 },
552 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
553 { "ICH 1.05V", 6, 0, 10, 1, 0 },
554 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
555 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
556 { "ATX +5V", 9, 0, 30, 1, 0 },
557 { "+3.3V", 10, 0, 20, 1, 0 },
575 { "CPU Core", 0, 0, 10, 1, 0 },
577 { "DDR3 VTT", 2, 0, 10, 1, 0 },
578 { "CPU VTT", 3, 0, 10, 1, 0 },
579 { "MCH 1.25V", 4, 0, 10, 1, 0 },
580 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
581 { "ICH 1.05V", 6, 0, 10, 1, 0 },
582 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
583 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
584 { "ATX +5V", 9, 0, 30, 1, 0 },
585 { "+3.3V", 10, 0, 20, 1, 0 },
602 { "CPU Core", 0, 0, 10, 1, 0 },
604 { "DDR2 VTT", 2, 0, 10, 1, 0 },
605 { "CPU VTT", 3, 0, 10, 1, 0 },
606 { "MCH 1.25V", 4, 0, 10, 1, 0 },
607 { "ICHIO 1.5V", 5, 0, 10, 1, 0 },
608 { "ICH 1.05V", 6, 0, 10, 1, 0 },
609 { "ATX +12V (24-Pin)", 7, 0, 60, 1, 0 },
610 { "ATX +12V (8-pin)", 8, 0, 60, 1, 0 },
611 { "ATX +5V", 9, 0, 30, 1, 0 },
612 { "+3.3V", 10, 0, 20, 1, 0 },
925 struct sensor_device_attribute_2 abituguru3_sysfs_templ[3][10] = { {
973 const int no_sysfs_attr[3] = { 10, 8, 7 }; in abituguru3_probe()