Lines Matching +full:0 +full:x00100
20 #define REG_CTRL 0x00
21 #define REG_CTRL_EN 0x00001
22 #define REG_CTRL_SLAVE 0x00002
23 #define REG_CTRL_AUTOACK 0x00004
24 #define REG_CTRL_AUTOSE 0x00008
25 #define REG_CTRL_AUTOSN 0x00010
26 #define REG_CTRL_ARBDIS 0x00020
27 #define REG_CTRL_GCAMEN 0x00040
28 #define REG_CTRL_CLHR__MASK 0x00300
29 #define REG_CTRL_BITO__MASK 0x03000
30 #define REG_CTRL_BITO_OFF 0x00000
31 #define REG_CTRL_BITO_40PCC 0x01000
32 #define REG_CTRL_BITO_80PCC 0x02000
33 #define REG_CTRL_BITO_160PCC 0x03000
34 #define REG_CTRL_GIBITO 0x08000
35 #define REG_CTRL_CLTO__MASK 0x70000
36 #define REG_CTRL_CLTO_OFF 0x00000
38 #define REG_CMD 0x04
39 #define REG_CMD_START 0x00001
40 #define REG_CMD_STOP 0x00002
41 #define REG_CMD_ACK 0x00004
42 #define REG_CMD_NACK 0x00008
43 #define REG_CMD_CONT 0x00010
44 #define REG_CMD_ABORT 0x00020
45 #define REG_CMD_CLEARTX 0x00040
46 #define REG_CMD_CLEARPC 0x00080
48 #define REG_STATE 0x08
49 #define REG_STATE_BUSY 0x00001
50 #define REG_STATE_MASTER 0x00002
51 #define REG_STATE_TRANSMITTER 0x00004
52 #define REG_STATE_NACKED 0x00008
53 #define REG_STATE_BUSHOLD 0x00010
54 #define REG_STATE_STATE__MASK 0x000e0
55 #define REG_STATE_STATE_IDLE 0x00000
56 #define REG_STATE_STATE_WAIT 0x00020
57 #define REG_STATE_STATE_START 0x00040
58 #define REG_STATE_STATE_ADDR 0x00060
59 #define REG_STATE_STATE_ADDRACK 0x00080
60 #define REG_STATE_STATE_DATA 0x000a0
61 #define REG_STATE_STATE_DATAACK 0x000c0
63 #define REG_STATUS 0x0c
64 #define REG_STATUS_PSTART 0x00001
65 #define REG_STATUS_PSTOP 0x00002
66 #define REG_STATUS_PACK 0x00004
67 #define REG_STATUS_PNACK 0x00008
68 #define REG_STATUS_PCONT 0x00010
69 #define REG_STATUS_PABORT 0x00020
70 #define REG_STATUS_TXC 0x00040
71 #define REG_STATUS_TXBL 0x00080
72 #define REG_STATUS_RXDATAV 0x00100
74 #define REG_CLKDIV 0x10
75 #define REG_CLKDIV_DIV__MASK 0x001ff
78 #define REG_SADDR 0x14
79 #define REG_SADDRMASK 0x18
80 #define REG_RXDATA 0x1c
81 #define REG_RXDATAP 0x20
82 #define REG_TXDATA 0x24
83 #define REG_IF 0x28
84 #define REG_IF_START 0x00001
85 #define REG_IF_RSTART 0x00002
86 #define REG_IF_ADDR 0x00004
87 #define REG_IF_TXC 0x00008
88 #define REG_IF_TXBL 0x00010
89 #define REG_IF_RXDATAV 0x00020
90 #define REG_IF_ACK 0x00040
91 #define REG_IF_NACK 0x00080
92 #define REG_IF_MSTOP 0x00100
93 #define REG_IF_ARBLOST 0x00200
94 #define REG_IF_BUSERR 0x00400
95 #define REG_IF_BUSHOLD 0x00800
96 #define REG_IF_TXOF 0x01000
97 #define REG_IF_RXUF 0x02000
98 #define REG_IF_BITO 0x04000
99 #define REG_IF_CLTO 0x08000
100 #define REG_IF_SSTOP 0x10000
102 #define REG_IFS 0x2c
103 #define REG_IFC 0x30
104 #define REG_IFC__MASK 0x1ffcf
106 #define REG_IEN 0x34
108 #define REG_ROUTE 0x38
109 #define REG_ROUTE_SDAPEN 0x00001
110 #define REG_ROUTE_SCLPEN 0x00002
111 #define REG_ROUTE_LOCATION__MASK 0x00700
156 ddata->current_word = 0; in efm32_i2c_send_next_byte()
179 ddata->current_word = 0; in efm32_i2c_recv_next_byte()
268 ddata->current_word = 0; in efm32_i2c_master_xfer()
269 ddata->current_msg = 0; in efm32_i2c_master_xfer()
341 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); in efm32_i2c_probe()
347 if (resource_size(res) < 0x42) { in efm32_i2c_probe()
356 ret = platform_get_irq(pdev, 0); in efm32_i2c_probe()
357 if (ret <= 0) { in efm32_i2c_probe()
367 if (ret < 0) { in efm32_i2c_probe()
406 if (clkdiv >= 0x200) { in efm32_i2c_probe()
423 REG_CTRL_BITO_160PCC | 0 * REG_CTRL_GIBITO); in efm32_i2c_probe()
432 ret = request_irq(ddata->irq, efm32_i2c_irq, 0, DRIVER_NAME, ddata); in efm32_i2c_probe()
433 if (ret < 0) { in efm32_i2c_probe()
456 return 0; in efm32_i2c_remove()