Lines Matching +full:enable +full:- +full:ssc
26 /* SSC registers */
50 /* SSC Control */
65 /* SSC Interrupt Enable */
79 /* SSC Status */
96 /* SSC I2C Control */
106 /* SSC Tx FIFO Status */
109 /* SSC Rx FIFO Status */
112 /* SSC Clear bit operation */
119 /* SSC Clock Prescaler */
133 * struct st_i2c_timings - per-Mode tuning parameters
155 * struct st_i2c_client - client specific data
156 * @addr: 8-bit slave addr, including r/w bit
173 * struct st_i2c_dev - private data of the controller
179 * @clk: hw ssc block clock
184 * @busy: I2C transfer on-going
214 * compatible with some out-of-spec devices,
247 if (readl_relaxed(i2c_dev->base + SSC_STA) & SSC_STA_RIR) in st_i2c_flush_rx_fifo()
250 count = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT) & in st_i2c_flush_rx_fifo()
254 readl_relaxed(i2c_dev->base + SSC_RBUF); in st_i2c_flush_rx_fifo()
265 st_i2c_set_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); in st_i2c_soft_reset()
266 st_i2c_clr_bits(i2c_dev->base + SSC_CTL, SSC_CTL_SR); in st_i2c_soft_reset()
270 * st_i2c_hw_config() - Prepare SSC block, calculate and apply tuning timings
277 struct st_i2c_timings *t = &i2c_timings[i2c_dev->mode]; in st_i2c_hw_config()
283 writel_relaxed(val, i2c_dev->base + SSC_CLR); in st_i2c_hw_config()
285 /* SSC Control register setup */ in st_i2c_hw_config()
287 writel_relaxed(val, i2c_dev->base + SSC_CTL); in st_i2c_hw_config()
289 rate = clk_get_rate(i2c_dev->clk); in st_i2c_hw_config()
293 val = rate / (2 * t->rate); in st_i2c_hw_config()
294 writel_relaxed(val, i2c_dev->base + SSC_BRG); in st_i2c_hw_config()
296 /* Pre-scaler baudrate */ in st_i2c_hw_config()
297 writel_relaxed(1, i2c_dev->base + SSC_PRE_SCALER_BRG); in st_i2c_hw_config()
299 /* Enable I2C mode */ in st_i2c_hw_config()
300 writel_relaxed(SSC_I2C_I2CM, i2c_dev->base + SSC_I2C); in st_i2c_hw_config()
303 val = t->rep_start_hold / ns_per_clk; in st_i2c_hw_config()
304 writel_relaxed(val, i2c_dev->base + SSC_REP_START_HOLD); in st_i2c_hw_config()
307 val = t->rep_start_setup / ns_per_clk; in st_i2c_hw_config()
308 writel_relaxed(val, i2c_dev->base + SSC_REP_START_SETUP); in st_i2c_hw_config()
311 val = t->start_hold / ns_per_clk; in st_i2c_hw_config()
312 writel_relaxed(val, i2c_dev->base + SSC_START_HOLD); in st_i2c_hw_config()
315 val = t->data_setup_time / ns_per_clk; in st_i2c_hw_config()
316 writel_relaxed(val, i2c_dev->base + SSC_DATA_SETUP); in st_i2c_hw_config()
319 val = t->stop_setup_time / ns_per_clk; in st_i2c_hw_config()
320 writel_relaxed(val, i2c_dev->base + SSC_STOP_SETUP); in st_i2c_hw_config()
323 val = t->bus_free_time / ns_per_clk; in st_i2c_hw_config()
324 writel_relaxed(val, i2c_dev->base + SSC_BUS_FREE); in st_i2c_hw_config()
328 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER); in st_i2c_hw_config()
329 writel_relaxed(val, i2c_dev->base + SSC_PRSCALER_DATAOUT); in st_i2c_hw_config()
332 val = i2c_dev->scl_min_width_us * rate / 100000000; in st_i2c_hw_config()
333 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH); in st_i2c_hw_config()
336 val = i2c_dev->sda_min_width_us * rate / 100000000; in st_i2c_hw_config()
337 writel_relaxed(val, i2c_dev->base + SSC_NOISE_SUPP_WIDTH_DATAOUT); in st_i2c_hw_config()
345 dev_dbg(i2c_dev->dev, "Trying to recover bus\n"); in st_i2c_recover_bus()
355 writel_relaxed(0, i2c_dev->base + SSC_IEN); in st_i2c_recover_bus()
360 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); in st_i2c_recover_bus()
362 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM); in st_i2c_recover_bus()
365 writel_relaxed(0, i2c_dev->base + SSC_TBUF); in st_i2c_recover_bus()
367 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_I2CM); in st_i2c_recover_bus()
378 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_wait_free_bus()
385 dev_err(i2c_dev->dev, "bus not free (status = 0x%08x)\n", sta); in st_i2c_wait_free_bus()
387 ret = i2c_recover_bus(&i2c_dev->adap); in st_i2c_wait_free_bus()
389 dev_err(i2c_dev->dev, "Failed to recover the bus (%d)\n", ret); in st_i2c_wait_free_bus()
393 return -EBUSY; in st_i2c_wait_free_bus()
397 * st_i2c_write_tx_fifo() - Write a byte in the Tx FIFO
405 writel_relaxed(tbuf | 1, i2c_dev->base + SSC_TBUF); in st_i2c_write_tx_fifo()
409 * st_i2c_wr_fill_tx_fifo() - Fill the Tx FIFO in write mode
417 struct st_i2c_client *c = &i2c_dev->client; in st_i2c_wr_fill_tx_fifo()
421 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_wr_fill_tx_fifo()
425 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); in st_i2c_wr_fill_tx_fifo()
428 if (c->count < (SSC_TXFIFO_SIZE - tx_fstat)) in st_i2c_wr_fill_tx_fifo()
429 i = c->count; in st_i2c_wr_fill_tx_fifo()
431 i = SSC_TXFIFO_SIZE - tx_fstat; in st_i2c_wr_fill_tx_fifo()
433 for (; i > 0; i--, c->count--, c->buf++) in st_i2c_wr_fill_tx_fifo()
434 st_i2c_write_tx_fifo(i2c_dev, *c->buf); in st_i2c_wr_fill_tx_fifo()
438 * st_i2c_rd_fill_tx_fifo() - Fill the Tx FIFO in read mode
447 struct st_i2c_client *c = &i2c_dev->client; in st_i2c_rd_fill_tx_fifo()
451 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_rd_fill_tx_fifo()
455 tx_fstat = readl_relaxed(i2c_dev->base + SSC_TX_FSTAT); in st_i2c_rd_fill_tx_fifo()
458 if (max < (SSC_TXFIFO_SIZE - tx_fstat)) in st_i2c_rd_fill_tx_fifo()
461 i = SSC_TXFIFO_SIZE - tx_fstat; in st_i2c_rd_fill_tx_fifo()
463 for (; i > 0; i--, c->xfered++) in st_i2c_rd_fill_tx_fifo()
469 struct st_i2c_client *c = &i2c_dev->client; in st_i2c_read_rx_fifo()
473 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_read_rx_fifo()
477 i = readl_relaxed(i2c_dev->base + SSC_RX_FSTAT); in st_i2c_read_rx_fifo()
481 for (; (i > 0) && (c->count > 0); i--, c->count--) { in st_i2c_read_rx_fifo()
482 rbuf = readl_relaxed(i2c_dev->base + SSC_RBUF) >> 1; in st_i2c_read_rx_fifo()
483 *c->buf++ = (u8)rbuf & 0xff; in st_i2c_read_rx_fifo()
487 dev_err(i2c_dev->dev, "Unexpected %d bytes in rx fifo\n", i); in st_i2c_read_rx_fifo()
493 * st_i2c_terminate_xfer() - Send either STOP or REPSTART condition
498 struct st_i2c_client *c = &i2c_dev->client; in st_i2c_terminate_xfer()
500 st_i2c_clr_bits(i2c_dev->base + SSC_IEN, SSC_IEN_TEEN); in st_i2c_terminate_xfer()
501 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); in st_i2c_terminate_xfer()
503 if (c->stop) { in st_i2c_terminate_xfer()
504 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_STOPEN); in st_i2c_terminate_xfer()
505 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); in st_i2c_terminate_xfer()
507 st_i2c_set_bits(i2c_dev->base + SSC_IEN, SSC_IEN_REPSTRTEN); in st_i2c_terminate_xfer()
508 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_REPSTRTG); in st_i2c_terminate_xfer()
513 * st_i2c_handle_write() - Handle FIFO empty interrupt in case of write
518 struct st_i2c_client *c = &i2c_dev->client; in st_i2c_handle_write()
522 if (!c->count) in st_i2c_handle_write()
530 * st_i2c_handle_write() - Handle FIFO enmpty interrupt in case of read
535 struct st_i2c_client *c = &i2c_dev->client; in st_i2c_handle_read()
539 if (!c->xfered) { in st_i2c_handle_read()
540 readl_relaxed(i2c_dev->base + SSC_RBUF); in st_i2c_handle_read()
541 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_TXENB); in st_i2c_handle_read()
546 if (!c->count) { in st_i2c_handle_read()
549 } else if (c->count == 1) { in st_i2c_handle_read()
551 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, SSC_I2C_ACKG); in st_i2c_handle_read()
555 writel_relaxed(ien, i2c_dev->base + SSC_IEN); in st_i2c_handle_read()
557 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count); in st_i2c_handle_read()
559 st_i2c_rd_fill_tx_fifo(i2c_dev, c->count - 1); in st_i2c_handle_read()
564 * st_i2c_isr() - Interrupt routine
571 struct st_i2c_client *c = &i2c_dev->client; in st_i2c_isr_thread()
575 ien = readl_relaxed(i2c_dev->base + SSC_IEN); in st_i2c_isr_thread()
576 sta = readl_relaxed(i2c_dev->base + SSC_STA); in st_i2c_isr_thread()
581 dev_dbg(i2c_dev->dev, "spurious it (sta=0x%04x, ien=0x%04x)\n", in st_i2c_isr_thread()
588 if (c->addr & I2C_M_RD) in st_i2c_isr_thread()
596 writel_relaxed(0, i2c_dev->base + SSC_IEN); in st_i2c_isr_thread()
597 complete(&i2c_dev->complete); in st_i2c_isr_thread()
601 writel_relaxed(SSC_CLR_NACK, i2c_dev->base + SSC_CLR); in st_i2c_isr_thread()
604 if ((c->addr & I2C_M_RD) && (c->count == 1) && (c->xfered)) { in st_i2c_isr_thread()
610 writel_relaxed(it, i2c_dev->base + SSC_IEN); in st_i2c_isr_thread()
612 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); in st_i2c_isr_thread()
613 c->result = -EIO; in st_i2c_isr_thread()
617 writel_relaxed(SSC_CLR_SSCARBL, i2c_dev->base + SSC_CLR); in st_i2c_isr_thread()
620 writel_relaxed(it, i2c_dev->base + SSC_IEN); in st_i2c_isr_thread()
622 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STOPG); in st_i2c_isr_thread()
623 c->result = -EAGAIN; in st_i2c_isr_thread()
627 dev_err(i2c_dev->dev, in st_i2c_isr_thread()
633 * before re-enabling interrupt at GIC level, and thus avoid spurious in st_i2c_isr_thread()
636 readl(i2c_dev->base + SSC_IEN); in st_i2c_isr_thread()
642 * st_i2c_xfer_msg() - Transfer a single I2C message
651 struct st_i2c_client *c = &i2c_dev->client; in st_i2c_xfer_msg()
656 c->addr = i2c_8bit_addr_from_msg(msg); in st_i2c_xfer_msg()
657 c->buf = msg->buf; in st_i2c_xfer_msg()
658 c->count = msg->len; in st_i2c_xfer_msg()
659 c->xfered = 0; in st_i2c_xfer_msg()
660 c->result = 0; in st_i2c_xfer_msg()
661 c->stop = is_last; in st_i2c_xfer_msg()
663 reinit_completion(&i2c_dev->complete); in st_i2c_xfer_msg()
666 st_i2c_set_bits(i2c_dev->base + SSC_CTL, ctl); in st_i2c_xfer_msg()
669 if (c->addr & I2C_M_RD) in st_i2c_xfer_msg()
671 st_i2c_set_bits(i2c_dev->base + SSC_I2C, i2c); in st_i2c_xfer_msg()
674 st_i2c_write_tx_fifo(i2c_dev, c->addr); in st_i2c_xfer_msg()
676 /* Pre-fill Tx fifo with data in case of write */ in st_i2c_xfer_msg()
677 if (!(c->addr & I2C_M_RD)) in st_i2c_xfer_msg()
681 writel_relaxed(it, i2c_dev->base + SSC_IEN); in st_i2c_xfer_msg()
688 st_i2c_set_bits(i2c_dev->base + SSC_I2C, SSC_I2C_STRTG); in st_i2c_xfer_msg()
691 timeout = wait_for_completion_timeout(&i2c_dev->complete, in st_i2c_xfer_msg()
692 i2c_dev->adap.timeout); in st_i2c_xfer_msg()
693 ret = c->result; in st_i2c_xfer_msg()
696 dev_err(i2c_dev->dev, "Write to slave 0x%x timed out\n", in st_i2c_xfer_msg()
697 c->addr); in st_i2c_xfer_msg()
698 ret = -ETIMEDOUT; in st_i2c_xfer_msg()
702 st_i2c_clr_bits(i2c_dev->base + SSC_I2C, i2c); in st_i2c_xfer_msg()
705 i2c_dev->base + SSC_CLR); in st_i2c_xfer_msg()
711 * st_i2c_xfer() - Transfer a single I2C message
722 i2c_dev->busy = true; in st_i2c_xfer()
724 ret = clk_prepare_enable(i2c_dev->clk); in st_i2c_xfer()
726 dev_err(i2c_dev->dev, "Failed to prepare_enable clock\n"); in st_i2c_xfer()
730 pinctrl_pm_select_default_state(i2c_dev->dev); in st_i2c_xfer()
735 ret = st_i2c_xfer_msg(i2c_dev, &msgs[i], i == 0, i == num - 1); in st_i2c_xfer()
737 pinctrl_pm_select_idle_state(i2c_dev->dev); in st_i2c_xfer()
739 clk_disable_unprepare(i2c_dev->clk); in st_i2c_xfer()
741 i2c_dev->busy = false; in st_i2c_xfer()
751 if (i2c_dev->busy) in st_i2c_suspend()
752 return -EBUSY; in st_i2c_suspend()
793 ret = of_property_read_u32(np, "st,i2c-min-scl-pulse-width-us", in st_i2c_of_get_deglitch()
794 &i2c_dev->scl_min_width_us); in st_i2c_of_get_deglitch()
795 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { in st_i2c_of_get_deglitch()
796 dev_err(i2c_dev->dev, "st,i2c-min-scl-pulse-width-us invalid\n"); in st_i2c_of_get_deglitch()
800 ret = of_property_read_u32(np, "st,i2c-min-sda-pulse-width-us", in st_i2c_of_get_deglitch()
801 &i2c_dev->sda_min_width_us); in st_i2c_of_get_deglitch()
802 if ((ret == -ENODATA) || (ret == -EOVERFLOW)) { in st_i2c_of_get_deglitch()
803 dev_err(i2c_dev->dev, "st,i2c-min-sda-pulse-width-us invalid\n"); in st_i2c_of_get_deglitch()
812 struct device_node *np = pdev->dev.of_node; in st_i2c_probe()
819 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in st_i2c_probe()
821 return -ENOMEM; in st_i2c_probe()
824 i2c_dev->base = devm_ioremap_resource(&pdev->dev, res); in st_i2c_probe()
825 if (IS_ERR(i2c_dev->base)) in st_i2c_probe()
826 return PTR_ERR(i2c_dev->base); in st_i2c_probe()
828 i2c_dev->irq = irq_of_parse_and_map(np, 0); in st_i2c_probe()
829 if (!i2c_dev->irq) { in st_i2c_probe()
830 dev_err(&pdev->dev, "IRQ missing or invalid\n"); in st_i2c_probe()
831 return -EINVAL; in st_i2c_probe()
834 i2c_dev->clk = of_clk_get_by_name(np, "ssc"); in st_i2c_probe()
835 if (IS_ERR(i2c_dev->clk)) { in st_i2c_probe()
836 dev_err(&pdev->dev, "Unable to request clock\n"); in st_i2c_probe()
837 return PTR_ERR(i2c_dev->clk); in st_i2c_probe()
840 i2c_dev->mode = I2C_MODE_STANDARD; in st_i2c_probe()
841 ret = of_property_read_u32(np, "clock-frequency", &clk_rate); in st_i2c_probe()
843 i2c_dev->mode = I2C_MODE_FAST; in st_i2c_probe()
845 i2c_dev->dev = &pdev->dev; in st_i2c_probe()
847 ret = devm_request_threaded_irq(&pdev->dev, i2c_dev->irq, in st_i2c_probe()
849 IRQF_ONESHOT, pdev->name, i2c_dev); in st_i2c_probe()
851 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); in st_i2c_probe()
855 pinctrl_pm_select_default_state(i2c_dev->dev); in st_i2c_probe()
857 pinctrl_pm_select_idle_state(i2c_dev->dev); in st_i2c_probe()
863 adap = &i2c_dev->adap; in st_i2c_probe()
865 snprintf(adap->name, sizeof(adap->name), "ST I2C(%pa)", &res->start); in st_i2c_probe()
866 adap->owner = THIS_MODULE; in st_i2c_probe()
867 adap->timeout = 2 * HZ; in st_i2c_probe()
868 adap->retries = 0; in st_i2c_probe()
869 adap->algo = &st_i2c_algo; in st_i2c_probe()
870 adap->bus_recovery_info = &st_i2c_recovery_info; in st_i2c_probe()
871 adap->dev.parent = &pdev->dev; in st_i2c_probe()
872 adap->dev.of_node = pdev->dev.of_node; in st_i2c_probe()
874 init_completion(&i2c_dev->complete); in st_i2c_probe()
882 dev_info(i2c_dev->dev, "%s initialized\n", adap->name); in st_i2c_probe()
891 i2c_del_adapter(&i2c_dev->adap); in st_i2c_remove()
897 { .compatible = "st,comms-ssc-i2c", },
898 { .compatible = "st,comms-ssc4-i2c", },
905 .name = "st-i2c",