Lines Matching +full:i2c +full:- +full:fast +full:- +full:mode
2 * drivers/i2c/busses/i2c-tegra.c
23 #include <linux/i2c.h>
121 #define I2C_MST_FIFO_CONTROL_RX_TRIG(x) (((x) - 1) << 4)
122 #define I2C_MST_FIFO_CONTROL_TX_TRIG(x) (((x) - 1) << 16)
148 * @has_single_clk_source: The I2C controller has single clock source. Tegra30
149 * and earlier SoCs have two clock sources i.e. div-clk and
150 * fast-clk.
153 * @clk_divisor_hs_mode: Clock divisor in HS mode.
154 * @clk_divisor_std_fast_mode: Clock divisor in standard/fast mode. It is
155 * applicable if there is no fast clock source i.e. single clock
157 * @clk_divisor_fast_plus_mode: Clock divisor in fast mode plus. It is
158 * applicable if there is no fast clock source (i.e. single
160 * @has_multi_master_mode: The I2C controller supports running in single-master
161 * or multi-master mode.
162 * @has_slcg_override_reg: The I2C controller supports a register that
164 * @has_mst_fifo: The I2C controller contains the new MST FIFO interface that
167 * @quirks: i2c adapter quirks for limiting write/read transfer size and not
185 * struct tegra_i2c_dev - per device I2C context
187 * @hw: Tegra I2C HW feature
188 * @adapter: core I2C layer adapter information
189 * @div_clk: clock reference for div clock of I2C controller
190 * @fast_clk: clock reference for fast clock of I2C controller
191 * @rst: reset control for the I2C controller
193 * @cont_id: I2C controller ID, used for packet header
196 * @is_dvc: identifies the DVC I2C controller, has a different register layout
202 * @bus_clk_rate: current I2C bus clock rate
203 * @clk_divisor_non_hs_mode: clock divider for non-high-speed modes
204 * @is_multimaster_mode: track if I2C controller is in multi-master mode
233 writel(val, i2c_dev->base + reg); in dvc_writel()
238 return readl(i2c_dev->base + reg); in dvc_readl()
243 * to the I2C block inside the DVC block
248 if (i2c_dev->is_dvc) in tegra_i2c_reg_addr()
256 writel(val, i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
260 readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_writel()
265 return readl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg)); in i2c_readl()
271 writesl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_writesl()
277 readsl(i2c_dev->base + tegra_i2c_reg_addr(i2c_dev, reg), data, len); in i2c_readsl()
302 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_flush_fifos()
318 dev_warn(i2c_dev->dev, "timeout waiting for fifo flush\n"); in tegra_i2c_flush_fifos()
319 return -ETIMEDOUT; in tegra_i2c_flush_fifos()
330 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_empty_rx_fifo()
331 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_empty_rx_fifo()
334 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_empty_rx_fifo()
352 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_empty_rx_fifo()
353 rx_fifo_avail -= words_to_transfer; in tegra_i2c_empty_rx_fifo()
365 rx_fifo_avail--; in tegra_i2c_empty_rx_fifo()
369 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_empty_rx_fifo()
370 i2c_dev->msg_buf = buf; in tegra_i2c_empty_rx_fifo()
379 u8 *buf = i2c_dev->msg_buf; in tegra_i2c_fill_tx_fifo()
380 size_t buf_remaining = i2c_dev->msg_buf_remaining; in tegra_i2c_fill_tx_fifo()
383 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_fill_tx_fifo()
406 * buf_remaining as 0 and doesn't call us back re-entrantly. in tegra_i2c_fill_tx_fifo()
408 buf_remaining -= words_to_transfer * BYTES_PER_FIFO_WORD; in tegra_i2c_fill_tx_fifo()
409 tx_fifo_avail -= words_to_transfer; in tegra_i2c_fill_tx_fifo()
410 i2c_dev->msg_buf_remaining = buf_remaining; in tegra_i2c_fill_tx_fifo()
411 i2c_dev->msg_buf = buf + in tegra_i2c_fill_tx_fifo()
431 i2c_dev->msg_buf_remaining = 0; in tegra_i2c_fill_tx_fifo()
432 i2c_dev->msg_buf = NULL; in tegra_i2c_fill_tx_fifo()
442 * One of the Tegra I2C blocks is inside the DVC (Digital Voltage Controller)
443 * block. This block is identical to the rest of the I2C blocks, except that
444 * it only supports master mode, it has registers moved around, and it needs
445 * some extra init to get it into I2C mode. The register moves are handled
467 ret = pinctrl_pm_select_default_state(i2c_dev->dev); in tegra_i2c_runtime_resume()
471 if (!i2c_dev->hw->has_single_clk_source) { in tegra_i2c_runtime_resume()
472 ret = clk_enable(i2c_dev->fast_clk); in tegra_i2c_runtime_resume()
474 dev_err(i2c_dev->dev, in tegra_i2c_runtime_resume()
475 "Enabling fast clk failed, err %d\n", ret); in tegra_i2c_runtime_resume()
480 ret = clk_enable(i2c_dev->div_clk); in tegra_i2c_runtime_resume()
482 dev_err(i2c_dev->dev, in tegra_i2c_runtime_resume()
484 clk_disable(i2c_dev->fast_clk); in tegra_i2c_runtime_resume()
495 clk_disable(i2c_dev->div_clk); in tegra_i2c_runtime_suspend()
496 if (!i2c_dev->hw->has_single_clk_source) in tegra_i2c_runtime_suspend()
497 clk_disable(i2c_dev->fast_clk); in tegra_i2c_runtime_suspend()
499 return pinctrl_pm_select_idle_state(i2c_dev->dev); in tegra_i2c_runtime_suspend()
509 if (i2c_dev->hw->has_config_load_reg) { in tegra_i2c_wait_for_config_load()
511 addr = i2c_dev->base + reg_offset; in tegra_i2c_wait_for_config_load()
521 dev_warn(i2c_dev->dev, in tegra_i2c_wait_for_config_load()
536 err = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_init()
538 dev_err(i2c_dev->dev, "runtime resume failed %d\n", err); in tegra_i2c_init()
542 reset_control_assert(i2c_dev->rst); in tegra_i2c_init()
544 reset_control_deassert(i2c_dev->rst); in tegra_i2c_init()
546 if (i2c_dev->is_dvc) in tegra_i2c_init()
552 if (i2c_dev->hw->has_multi_master_mode) in tegra_i2c_init()
559 clk_divisor = i2c_dev->hw->clk_divisor_hs_mode; in tegra_i2c_init()
560 clk_divisor |= i2c_dev->clk_divisor_non_hs_mode << in tegra_i2c_init()
564 if (!i2c_dev->is_dvc) { in tegra_i2c_init()
573 if (i2c_dev->hw->has_mst_fifo) { in tegra_i2c_init()
587 if (i2c_dev->is_multimaster_mode && i2c_dev->hw->has_slcg_override_reg) in tegra_i2c_init()
594 if (i2c_dev->irq_disabled) { in tegra_i2c_init()
595 i2c_dev->irq_disabled = false; in tegra_i2c_init()
596 enable_irq(i2c_dev->irq); in tegra_i2c_init()
600 pm_runtime_put(i2c_dev->dev); in tegra_i2c_init()
609 * NACK interrupt is generated before the I2C controller generates in tegra_i2c_disable_packet_mode()
614 udelay(DIV_ROUND_UP(2 * 1000000, i2c_dev->bus_clk_rate)); in tegra_i2c_disable_packet_mode()
632 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); in tegra_i2c_isr()
634 dev_warn(i2c_dev->dev, "irq status 0 %08x %08x %08x\n", in tegra_i2c_isr()
638 i2c_dev->msg_err |= I2C_ERR_UNKNOWN_INTERRUPT; in tegra_i2c_isr()
640 if (!i2c_dev->irq_disabled) { in tegra_i2c_isr()
641 disable_irq_nosync(i2c_dev->irq); in tegra_i2c_isr()
642 i2c_dev->irq_disabled = true; in tegra_i2c_isr()
650 i2c_dev->msg_err |= I2C_ERR_NO_ACK; in tegra_i2c_isr()
652 i2c_dev->msg_err |= I2C_ERR_ARBITRATION_LOST; in tegra_i2c_isr()
656 if (i2c_dev->msg_read && (status & I2C_INT_RX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
657 if (i2c_dev->msg_buf_remaining) in tegra_i2c_isr()
663 if (!i2c_dev->msg_read && (status & I2C_INT_TX_FIFO_DATA_REQ)) { in tegra_i2c_isr()
664 if (i2c_dev->msg_buf_remaining) in tegra_i2c_isr()
671 if (i2c_dev->is_dvc) in tegra_i2c_isr()
675 BUG_ON(i2c_dev->msg_buf_remaining); in tegra_i2c_isr()
676 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
685 if (i2c_dev->is_dvc) in tegra_i2c_isr()
688 complete(&i2c_dev->msg_complete); in tegra_i2c_isr()
690 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); in tegra_i2c_isr()
704 i2c_dev->msg_buf = msg->buf; in tegra_i2c_xfer_msg()
705 i2c_dev->msg_buf_remaining = msg->len; in tegra_i2c_xfer_msg()
706 i2c_dev->msg_err = I2C_ERR_NONE; in tegra_i2c_xfer_msg()
707 i2c_dev->msg_read = (msg->flags & I2C_M_RD); in tegra_i2c_xfer_msg()
708 reinit_completion(&i2c_dev->msg_complete); in tegra_i2c_xfer_msg()
710 spin_lock_irqsave(&i2c_dev->xfer_lock, flags); in tegra_i2c_xfer_msg()
717 (i2c_dev->cont_id << PACKET_HEADER0_CONT_ID_SHIFT) | in tegra_i2c_xfer_msg()
721 packet_header = msg->len - 1; in tegra_i2c_xfer_msg()
729 if (msg->flags & I2C_M_TEN) { in tegra_i2c_xfer_msg()
730 packet_header |= msg->addr; in tegra_i2c_xfer_msg()
733 packet_header |= msg->addr << I2C_HEADER_SLAVE_ADDR_SHIFT; in tegra_i2c_xfer_msg()
735 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_xfer_msg()
737 if (msg->flags & I2C_M_RD) in tegra_i2c_xfer_msg()
741 if (!(msg->flags & I2C_M_RD)) in tegra_i2c_xfer_msg()
744 if (i2c_dev->hw->has_per_pkt_xfer_complete_irq) in tegra_i2c_xfer_msg()
746 if (msg->flags & I2C_M_RD) in tegra_i2c_xfer_msg()
748 else if (i2c_dev->msg_buf_remaining) in tegra_i2c_xfer_msg()
752 spin_unlock_irqrestore(&i2c_dev->xfer_lock, flags); in tegra_i2c_xfer_msg()
753 dev_dbg(i2c_dev->dev, "unmasked irq: %02x\n", in tegra_i2c_xfer_msg()
756 time_left = wait_for_completion_timeout(&i2c_dev->msg_complete, in tegra_i2c_xfer_msg()
761 dev_err(i2c_dev->dev, "i2c transfer timed out\n"); in tegra_i2c_xfer_msg()
764 return -ETIMEDOUT; in tegra_i2c_xfer_msg()
767 dev_dbg(i2c_dev->dev, "transfer complete: %lu %d %d\n", in tegra_i2c_xfer_msg()
768 time_left, completion_done(&i2c_dev->msg_complete), in tegra_i2c_xfer_msg()
769 i2c_dev->msg_err); in tegra_i2c_xfer_msg()
771 if (likely(i2c_dev->msg_err == I2C_ERR_NONE)) in tegra_i2c_xfer_msg()
775 if (i2c_dev->msg_err == I2C_ERR_NO_ACK) { in tegra_i2c_xfer_msg()
776 if (msg->flags & I2C_M_IGNORE_NAK) in tegra_i2c_xfer_msg()
778 return -EREMOTEIO; in tegra_i2c_xfer_msg()
781 return -EIO; in tegra_i2c_xfer_msg()
791 ret = pm_runtime_get_sync(i2c_dev->dev); in tegra_i2c_xfer()
793 dev_err(i2c_dev->dev, "runtime resume failed %d\n", ret); in tegra_i2c_xfer()
800 if (i < (num - 1)) { in tegra_i2c_xfer()
811 pm_runtime_put(i2c_dev->dev); in tegra_i2c_xfer()
822 if (i2c_dev->hw->has_continue_xfer_support) in tegra_i2c_func()
829 struct device_node *np = i2c_dev->dev->of_node; in tegra_i2c_parse_dt()
832 ret = of_property_read_u32(np, "clock-frequency", in tegra_i2c_parse_dt()
833 &i2c_dev->bus_clk_rate); in tegra_i2c_parse_dt()
835 i2c_dev->bus_clk_rate = 100000; /* default clock rate */ in tegra_i2c_parse_dt()
837 i2c_dev->is_multimaster_mode = of_property_read_bool(np, in tegra_i2c_parse_dt()
838 "multi-master"); in tegra_i2c_parse_dt()
850 .max_write_len = 4096 - 12,
943 { .compatible = "nvidia,tegra194-i2c", .data = &tegra194_i2c_hw, },
944 { .compatible = "nvidia,tegra210-i2c", .data = &tegra210_i2c_hw, },
945 { .compatible = "nvidia,tegra124-i2c", .data = &tegra124_i2c_hw, },
946 { .compatible = "nvidia,tegra114-i2c", .data = &tegra114_i2c_hw, },
947 { .compatible = "nvidia,tegra30-i2c", .data = &tegra30_i2c_hw, },
948 { .compatible = "nvidia,tegra20-i2c", .data = &tegra20_i2c_hw, },
949 { .compatible = "nvidia,tegra20-i2c-dvc", .data = &tegra20_i2c_hw, },
966 base = devm_ioremap_resource(&pdev->dev, res); in tegra_i2c_probe()
972 dev_err(&pdev->dev, "no irq resource\n"); in tegra_i2c_probe()
973 return -EINVAL; in tegra_i2c_probe()
975 irq = res->start; in tegra_i2c_probe()
977 div_clk = devm_clk_get(&pdev->dev, "div-clk"); in tegra_i2c_probe()
979 dev_err(&pdev->dev, "missing controller clock\n"); in tegra_i2c_probe()
983 i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL); in tegra_i2c_probe()
985 return -ENOMEM; in tegra_i2c_probe()
987 i2c_dev->base = base; in tegra_i2c_probe()
988 i2c_dev->div_clk = div_clk; in tegra_i2c_probe()
989 i2c_dev->adapter.algo = &tegra_i2c_algo; in tegra_i2c_probe()
990 i2c_dev->irq = irq; in tegra_i2c_probe()
991 i2c_dev->cont_id = pdev->id; in tegra_i2c_probe()
992 i2c_dev->dev = &pdev->dev; in tegra_i2c_probe()
994 i2c_dev->rst = devm_reset_control_get_exclusive(&pdev->dev, "i2c"); in tegra_i2c_probe()
995 if (IS_ERR(i2c_dev->rst)) { in tegra_i2c_probe()
996 dev_err(&pdev->dev, "missing controller reset\n"); in tegra_i2c_probe()
997 return PTR_ERR(i2c_dev->rst); in tegra_i2c_probe()
1002 i2c_dev->hw = of_device_get_match_data(&pdev->dev); in tegra_i2c_probe()
1003 i2c_dev->is_dvc = of_device_is_compatible(pdev->dev.of_node, in tegra_i2c_probe()
1004 "nvidia,tegra20-i2c-dvc"); in tegra_i2c_probe()
1005 i2c_dev->adapter.quirks = i2c_dev->hw->quirks; in tegra_i2c_probe()
1006 init_completion(&i2c_dev->msg_complete); in tegra_i2c_probe()
1007 spin_lock_init(&i2c_dev->xfer_lock); in tegra_i2c_probe()
1009 if (!i2c_dev->hw->has_single_clk_source) { in tegra_i2c_probe()
1010 fast_clk = devm_clk_get(&pdev->dev, "fast-clk"); in tegra_i2c_probe()
1012 dev_err(&pdev->dev, "missing fast clock\n"); in tegra_i2c_probe()
1015 i2c_dev->fast_clk = fast_clk; in tegra_i2c_probe()
1020 if (!i2c_dev->hw->has_single_clk_source) { in tegra_i2c_probe()
1021 ret = clk_prepare(i2c_dev->fast_clk); in tegra_i2c_probe()
1023 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); in tegra_i2c_probe()
1028 i2c_dev->clk_divisor_non_hs_mode = in tegra_i2c_probe()
1029 i2c_dev->hw->clk_divisor_std_fast_mode; in tegra_i2c_probe()
1030 if (i2c_dev->hw->clk_divisor_fast_plus_mode && in tegra_i2c_probe()
1031 (i2c_dev->bus_clk_rate == 1000000)) in tegra_i2c_probe()
1032 i2c_dev->clk_divisor_non_hs_mode = in tegra_i2c_probe()
1033 i2c_dev->hw->clk_divisor_fast_plus_mode; in tegra_i2c_probe()
1035 clk_multiplier *= (i2c_dev->clk_divisor_non_hs_mode + 1); in tegra_i2c_probe()
1036 ret = clk_set_rate(i2c_dev->div_clk, in tegra_i2c_probe()
1037 i2c_dev->bus_clk_rate * clk_multiplier); in tegra_i2c_probe()
1039 dev_err(i2c_dev->dev, "Clock rate change failed %d\n", ret); in tegra_i2c_probe()
1043 ret = clk_prepare(i2c_dev->div_clk); in tegra_i2c_probe()
1045 dev_err(i2c_dev->dev, "Clock prepare failed %d\n", ret); in tegra_i2c_probe()
1049 pm_runtime_enable(&pdev->dev); in tegra_i2c_probe()
1050 if (!pm_runtime_enabled(&pdev->dev)) { in tegra_i2c_probe()
1051 ret = tegra_i2c_runtime_resume(&pdev->dev); in tegra_i2c_probe()
1053 dev_err(&pdev->dev, "runtime resume failed\n"); in tegra_i2c_probe()
1058 if (i2c_dev->is_multimaster_mode) { in tegra_i2c_probe()
1059 ret = clk_enable(i2c_dev->div_clk); in tegra_i2c_probe()
1061 dev_err(i2c_dev->dev, "div_clk enable failed %d\n", in tegra_i2c_probe()
1069 dev_err(&pdev->dev, "Failed to initialize i2c controller\n"); in tegra_i2c_probe()
1073 ret = devm_request_irq(&pdev->dev, i2c_dev->irq, in tegra_i2c_probe()
1074 tegra_i2c_isr, 0, dev_name(&pdev->dev), i2c_dev); in tegra_i2c_probe()
1076 dev_err(&pdev->dev, "Failed to request irq %i\n", i2c_dev->irq); in tegra_i2c_probe()
1080 i2c_set_adapdata(&i2c_dev->adapter, i2c_dev); in tegra_i2c_probe()
1081 i2c_dev->adapter.owner = THIS_MODULE; in tegra_i2c_probe()
1082 i2c_dev->adapter.class = I2C_CLASS_DEPRECATED; in tegra_i2c_probe()
1083 strlcpy(i2c_dev->adapter.name, dev_name(&pdev->dev), in tegra_i2c_probe()
1084 sizeof(i2c_dev->adapter.name)); in tegra_i2c_probe()
1085 i2c_dev->adapter.dev.parent = &pdev->dev; in tegra_i2c_probe()
1086 i2c_dev->adapter.nr = pdev->id; in tegra_i2c_probe()
1087 i2c_dev->adapter.dev.of_node = pdev->dev.of_node; in tegra_i2c_probe()
1089 ret = i2c_add_numbered_adapter(&i2c_dev->adapter); in tegra_i2c_probe()
1096 if (i2c_dev->is_multimaster_mode) in tegra_i2c_probe()
1097 clk_disable(i2c_dev->div_clk); in tegra_i2c_probe()
1100 pm_runtime_disable(&pdev->dev); in tegra_i2c_probe()
1101 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra_i2c_probe()
1102 tegra_i2c_runtime_suspend(&pdev->dev); in tegra_i2c_probe()
1105 clk_unprepare(i2c_dev->div_clk); in tegra_i2c_probe()
1108 if (!i2c_dev->hw->has_single_clk_source) in tegra_i2c_probe()
1109 clk_unprepare(i2c_dev->fast_clk); in tegra_i2c_probe()
1118 i2c_del_adapter(&i2c_dev->adapter); in tegra_i2c_remove()
1120 if (i2c_dev->is_multimaster_mode) in tegra_i2c_remove()
1121 clk_disable(i2c_dev->div_clk); in tegra_i2c_remove()
1123 pm_runtime_disable(&pdev->dev); in tegra_i2c_remove()
1124 if (!pm_runtime_status_suspended(&pdev->dev)) in tegra_i2c_remove()
1125 tegra_i2c_runtime_suspend(&pdev->dev); in tegra_i2c_remove()
1127 clk_unprepare(i2c_dev->div_clk); in tegra_i2c_remove()
1128 if (!i2c_dev->hw->has_single_clk_source) in tegra_i2c_remove()
1129 clk_unprepare(i2c_dev->fast_clk); in tegra_i2c_remove()
1148 .name = "tegra-i2c",
1167 MODULE_DESCRIPTION("nVidia Tegra2 I2C Bus Controller driver");