Lines Matching +full:uniphier +full:- +full:fi2c
110 * TX-FIFO stores slave address in it for the first access. in uniphier_fi2c_fill_txfifo()
114 fifo_space--; in uniphier_fi2c_fill_txfifo()
116 while (priv->len) { in uniphier_fi2c_fill_txfifo()
117 if (fifo_space-- <= 0) in uniphier_fi2c_fill_txfifo()
120 dev_dbg(&priv->adap.dev, "write data: %02x\n", *priv->buf); in uniphier_fi2c_fill_txfifo()
121 writel(*priv->buf++, priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_fill_txfifo()
122 priv->len--; in uniphier_fi2c_fill_txfifo()
128 int fifo_left = priv->flags & UNIPHIER_FI2C_BYTE_WISE ? in uniphier_fi2c_drain_rxfifo()
131 while (priv->len) { in uniphier_fi2c_drain_rxfifo()
132 if (fifo_left-- <= 0) in uniphier_fi2c_drain_rxfifo()
135 *priv->buf++ = readl(priv->membase + UNIPHIER_FI2C_DTRX); in uniphier_fi2c_drain_rxfifo()
136 dev_dbg(&priv->adap.dev, "read data: %02x\n", priv->buf[-1]); in uniphier_fi2c_drain_rxfifo()
137 priv->len--; in uniphier_fi2c_drain_rxfifo()
143 writel(priv->enabled_irqs, priv->membase + UNIPHIER_FI2C_IE); in uniphier_fi2c_set_irqs()
149 writel(mask, priv->membase + UNIPHIER_FI2C_IC); in uniphier_fi2c_clear_irqs()
154 dev_dbg(&priv->adap.dev, "stop condition\n"); in uniphier_fi2c_stop()
156 priv->enabled_irqs |= UNIPHIER_FI2C_INT_STOP; in uniphier_fi2c_stop()
159 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_stop()
167 spin_lock(&priv->lock); in uniphier_fi2c_interrupt()
169 irq_status = readl(priv->membase + UNIPHIER_FI2C_INT); in uniphier_fi2c_interrupt()
170 irq_status &= priv->enabled_irqs; in uniphier_fi2c_interrupt()
172 dev_dbg(&priv->adap.dev, in uniphier_fi2c_interrupt()
174 priv->enabled_irqs, irq_status); in uniphier_fi2c_interrupt()
180 dev_dbg(&priv->adap.dev, "arbitration lost\n"); in uniphier_fi2c_interrupt()
181 priv->error = -EAGAIN; in uniphier_fi2c_interrupt()
186 dev_dbg(&priv->adap.dev, "could not get ACK\n"); in uniphier_fi2c_interrupt()
187 priv->error = -ENXIO; in uniphier_fi2c_interrupt()
188 if (priv->flags & UNIPHIER_FI2C_RD) { in uniphier_fi2c_interrupt()
191 * The receive-completed interrupt is never set even if in uniphier_fi2c_interrupt()
194 * To avoid time-out error, we issue STOP here, in uniphier_fi2c_interrupt()
199 priv->flags |= UNIPHIER_FI2C_DEFER_STOP_COMP; in uniphier_fi2c_interrupt()
206 if (!priv->len) in uniphier_fi2c_interrupt()
217 * (msg->len == 8, 16, 24, ...), the INT_RF bit is set a little in uniphier_fi2c_interrupt()
221 if (!priv->len && (irq_status & UNIPHIER_FI2C_INT_RB)) in uniphier_fi2c_interrupt()
224 if (unlikely(priv->flags & UNIPHIER_FI2C_MANUAL_NACK)) { in uniphier_fi2c_interrupt()
225 if (priv->len <= UNIPHIER_FI2C_FIFO_SIZE && in uniphier_fi2c_interrupt()
226 !(priv->flags & UNIPHIER_FI2C_BYTE_WISE)) { in uniphier_fi2c_interrupt()
227 dev_dbg(&priv->adap.dev, in uniphier_fi2c_interrupt()
229 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RB; in uniphier_fi2c_interrupt()
231 priv->flags |= UNIPHIER_FI2C_BYTE_WISE; in uniphier_fi2c_interrupt()
233 if (priv->len <= 1) { in uniphier_fi2c_interrupt()
234 dev_dbg(&priv->adap.dev, "set NACK\n"); in uniphier_fi2c_interrupt()
237 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_interrupt()
244 spin_unlock(&priv->lock); in uniphier_fi2c_interrupt()
249 if (priv->flags & UNIPHIER_FI2C_STOP) { in uniphier_fi2c_interrupt()
254 priv->enabled_irqs = 0; in uniphier_fi2c_interrupt()
256 complete(&priv->comp); in uniphier_fi2c_interrupt()
267 spin_unlock(&priv->lock); in uniphier_fi2c_interrupt()
274 priv->enabled_irqs |= UNIPHIER_FI2C_INT_TE; in uniphier_fi2c_tx_init()
278 writel(0, priv->membase + UNIPHIER_FI2C_TBC); in uniphier_fi2c_tx_init()
281 priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_tx_init()
288 priv->flags |= UNIPHIER_FI2C_RD; in uniphier_fi2c_rx_init()
290 if (likely(priv->len < 256)) { in uniphier_fi2c_rx_init()
295 writel(priv->len, priv->membase + UNIPHIER_FI2C_RBC); in uniphier_fi2c_rx_init()
296 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF | in uniphier_fi2c_rx_init()
304 writel(0, priv->membase + UNIPHIER_FI2C_RBC); in uniphier_fi2c_rx_init()
305 priv->flags |= UNIPHIER_FI2C_MANUAL_NACK; in uniphier_fi2c_rx_init()
306 priv->enabled_irqs |= UNIPHIER_FI2C_INT_RF; in uniphier_fi2c_rx_init()
313 priv->membase + UNIPHIER_FI2C_DTTX); in uniphier_fi2c_rx_init()
318 writel(UNIPHIER_FI2C_RST_RST, priv->membase + UNIPHIER_FI2C_RST); in uniphier_fi2c_reset()
324 priv->membase + UNIPHIER_FI2C_BRST); in uniphier_fi2c_prepare_operation()
330 i2c_recover_bus(&priv->adap); in uniphier_fi2c_recover()
338 bool is_read = msg->flags & I2C_M_RD; in uniphier_fi2c_master_xfer_one()
341 dev_dbg(&adap->dev, "%s: addr=0x%02x, len=%d, repeat=%d, stop=%d\n", in uniphier_fi2c_master_xfer_one()
342 is_read ? "receive" : "transmit", msg->addr, msg->len, in uniphier_fi2c_master_xfer_one()
345 priv->len = msg->len; in uniphier_fi2c_master_xfer_one()
346 priv->buf = msg->buf; in uniphier_fi2c_master_xfer_one()
347 priv->enabled_irqs = UNIPHIER_FI2C_INT_FAULTS; in uniphier_fi2c_master_xfer_one()
348 priv->error = 0; in uniphier_fi2c_master_xfer_one()
349 priv->flags = 0; in uniphier_fi2c_master_xfer_one()
352 priv->flags |= UNIPHIER_FI2C_STOP; in uniphier_fi2c_master_xfer_one()
354 reinit_completion(&priv->comp); in uniphier_fi2c_master_xfer_one()
357 priv->membase + UNIPHIER_FI2C_RST); /* reset TX/RX FIFO */ in uniphier_fi2c_master_xfer_one()
359 spin_lock_irqsave(&priv->lock, flags); in uniphier_fi2c_master_xfer_one()
362 uniphier_fi2c_rx_init(priv, msg->addr); in uniphier_fi2c_master_xfer_one()
364 uniphier_fi2c_tx_init(priv, msg->addr); in uniphier_fi2c_master_xfer_one()
366 dev_dbg(&adap->dev, "start condition\n"); in uniphier_fi2c_master_xfer_one()
370 * written only for a non-repeated START condition. in uniphier_fi2c_master_xfer_one()
374 priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_master_xfer_one()
376 spin_unlock_irqrestore(&priv->lock, flags); in uniphier_fi2c_master_xfer_one()
378 time_left = wait_for_completion_timeout(&priv->comp, adap->timeout); in uniphier_fi2c_master_xfer_one()
380 spin_lock_irqsave(&priv->lock, flags); in uniphier_fi2c_master_xfer_one()
381 priv->enabled_irqs = 0; in uniphier_fi2c_master_xfer_one()
383 spin_unlock_irqrestore(&priv->lock, flags); in uniphier_fi2c_master_xfer_one()
386 dev_err(&adap->dev, "transaction timeout.\n"); in uniphier_fi2c_master_xfer_one()
388 return -ETIMEDOUT; in uniphier_fi2c_master_xfer_one()
390 dev_dbg(&adap->dev, "complete\n"); in uniphier_fi2c_master_xfer_one()
392 if (unlikely(priv->flags & UNIPHIER_FI2C_DEFER_STOP_COMP)) { in uniphier_fi2c_master_xfer_one()
396 ret = readl_poll_timeout(priv->membase + UNIPHIER_FI2C_SR, in uniphier_fi2c_master_xfer_one()
402 dev_err(&adap->dev, in uniphier_fi2c_master_xfer_one()
409 return priv->error; in uniphier_fi2c_master_xfer_one()
416 if (readl(priv->membase + UNIPHIER_FI2C_SR) & UNIPHIER_FI2C_SR_DB) { in uniphier_fi2c_check_bus_busy()
417 if (priv->busy_cnt++ > 3) { in uniphier_fi2c_check_bus_busy()
423 priv->busy_cnt = 0; in uniphier_fi2c_check_bus_busy()
426 return -EAGAIN; in uniphier_fi2c_check_bus_busy()
429 priv->busy_cnt = 0; in uniphier_fi2c_check_bus_busy()
446 bool stop = (msg + 1 == emsg) || (msg->flags & I2C_M_STOP); in uniphier_fi2c_master_xfer()
472 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & in uniphier_fi2c_get_scl()
481 priv->membase + UNIPHIER_FI2C_BRST); in uniphier_fi2c_set_scl()
488 return !!(readl(priv->membase + UNIPHIER_FI2C_BM) & in uniphier_fi2c_get_sda()
507 unsigned int cyc = priv->clk_cycle; in uniphier_fi2c_hw_init()
510 tmp = readl(priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_hw_init()
512 writel(tmp, priv->membase + UNIPHIER_FI2C_CR); in uniphier_fi2c_hw_init()
517 * Standard-mode: tLOW + tHIGH = 10 us in uniphier_fi2c_hw_init()
518 * Fast-mode: tLOW + tHIGH = 2.5 us in uniphier_fi2c_hw_init()
520 writel(cyc, priv->membase + UNIPHIER_FI2C_CYC); in uniphier_fi2c_hw_init()
522 * Standard-mode: tLOW = 4.7 us, tHIGH = 4.0 us, tBUF = 4.7 us in uniphier_fi2c_hw_init()
523 * Fast-mode: tLOW = 1.3 us, tHIGH = 0.6 us, tBUF = 1.3 us in uniphier_fi2c_hw_init()
526 writel(cyc * 5 / 9, priv->membase + UNIPHIER_FI2C_LCTL); in uniphier_fi2c_hw_init()
528 * Standard-mode: tHD;STA = 4.0 us, tSU;STA = 4.7 us, tSU;STO = 4.0 us in uniphier_fi2c_hw_init()
529 * Fast-mode: tHD;STA = 0.6 us, tSU;STA = 0.6 us, tSU;STO = 0.6 us in uniphier_fi2c_hw_init()
531 writel(cyc / 2, priv->membase + UNIPHIER_FI2C_SSUT); in uniphier_fi2c_hw_init()
533 * Standard-mode: tSU;DAT = 250 ns in uniphier_fi2c_hw_init()
534 * Fast-mode: tSU;DAT = 100 ns in uniphier_fi2c_hw_init()
536 writel(cyc / 16, priv->membase + UNIPHIER_FI2C_DSUT); in uniphier_fi2c_hw_init()
543 struct device *dev = &pdev->dev; in uniphier_fi2c_probe()
552 return -ENOMEM; in uniphier_fi2c_probe()
555 priv->membase = devm_ioremap_resource(dev, regs); in uniphier_fi2c_probe()
556 if (IS_ERR(priv->membase)) in uniphier_fi2c_probe()
557 return PTR_ERR(priv->membase); in uniphier_fi2c_probe()
565 if (of_property_read_u32(dev->of_node, "clock-frequency", &bus_speed)) in uniphier_fi2c_probe()
569 dev_err(dev, "invalid clock-frequency %d\n", bus_speed); in uniphier_fi2c_probe()
570 return -EINVAL; in uniphier_fi2c_probe()
573 priv->clk = devm_clk_get(dev, NULL); in uniphier_fi2c_probe()
574 if (IS_ERR(priv->clk)) { in uniphier_fi2c_probe()
576 return PTR_ERR(priv->clk); in uniphier_fi2c_probe()
579 ret = clk_prepare_enable(priv->clk); in uniphier_fi2c_probe()
583 clk_rate = clk_get_rate(priv->clk); in uniphier_fi2c_probe()
586 ret = -EINVAL; in uniphier_fi2c_probe()
590 priv->clk_cycle = clk_rate / bus_speed; in uniphier_fi2c_probe()
591 init_completion(&priv->comp); in uniphier_fi2c_probe()
592 spin_lock_init(&priv->lock); in uniphier_fi2c_probe()
593 priv->adap.owner = THIS_MODULE; in uniphier_fi2c_probe()
594 priv->adap.algo = &uniphier_fi2c_algo; in uniphier_fi2c_probe()
595 priv->adap.dev.parent = dev; in uniphier_fi2c_probe()
596 priv->adap.dev.of_node = dev->of_node; in uniphier_fi2c_probe()
597 strlcpy(priv->adap.name, "UniPhier FI2C", sizeof(priv->adap.name)); in uniphier_fi2c_probe()
598 priv->adap.bus_recovery_info = &uniphier_fi2c_bus_recovery_info; in uniphier_fi2c_probe()
599 i2c_set_adapdata(&priv->adap, priv); in uniphier_fi2c_probe()
605 pdev->name, priv); in uniphier_fi2c_probe()
611 ret = i2c_add_adapter(&priv->adap); in uniphier_fi2c_probe()
614 clk_disable_unprepare(priv->clk); in uniphier_fi2c_probe()
623 i2c_del_adapter(&priv->adap); in uniphier_fi2c_remove()
624 clk_disable_unprepare(priv->clk); in uniphier_fi2c_remove()
633 clk_disable_unprepare(priv->clk); in uniphier_fi2c_suspend()
643 ret = clk_prepare_enable(priv->clk); in uniphier_fi2c_resume()
657 { .compatible = "socionext,uniphier-fi2c" },
666 .name = "uniphier-fi2c",
674 MODULE_DESCRIPTION("UniPhier FIFO-builtin I2C bus driver");