Lines Matching full:i2c
2 * i2c-xiic.c
33 #include <linux/i2c.h>
36 #include <linux/platform_data/i2c-xiic.h>
43 #define DRIVER_NAME "xiic-i2c"
57 * struct xiic_i2c - Internal representation of the XIIC I2C bus
173 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) argument
174 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) argument
176 static void xiic_start_xfer(struct xiic_i2c *i2c);
177 static void __xiic_start_xfer(struct xiic_i2c *i2c);
187 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) in xiic_setreg8() argument
189 if (i2c->endianness == LITTLE) in xiic_setreg8()
190 iowrite8(value, i2c->base + reg); in xiic_setreg8()
192 iowrite8(value, i2c->base + reg + 3); in xiic_setreg8()
195 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) in xiic_getreg8() argument
199 if (i2c->endianness == LITTLE) in xiic_getreg8()
200 ret = ioread8(i2c->base + reg); in xiic_getreg8()
202 ret = ioread8(i2c->base + reg + 3); in xiic_getreg8()
206 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) in xiic_setreg16() argument
208 if (i2c->endianness == LITTLE) in xiic_setreg16()
209 iowrite16(value, i2c->base + reg); in xiic_setreg16()
211 iowrite16be(value, i2c->base + reg + 2); in xiic_setreg16()
214 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) in xiic_setreg32() argument
216 if (i2c->endianness == LITTLE) in xiic_setreg32()
217 iowrite32(value, i2c->base + reg); in xiic_setreg32()
219 iowrite32be(value, i2c->base + reg); in xiic_setreg32()
222 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) in xiic_getreg32() argument
226 if (i2c->endianness == LITTLE) in xiic_getreg32()
227 ret = ioread32(i2c->base + reg); in xiic_getreg32()
229 ret = ioread32be(i2c->base + reg); in xiic_getreg32()
233 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) in xiic_irq_dis() argument
235 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_dis()
236 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); in xiic_irq_dis()
239 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_en() argument
241 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_irq_en()
242 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); in xiic_irq_en()
245 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr() argument
247 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_irq_clr()
248 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); in xiic_irq_clr()
251 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) in xiic_irq_clr_en() argument
253 xiic_irq_clr(i2c, mask); in xiic_irq_clr_en()
254 xiic_irq_en(i2c, mask); in xiic_irq_clr_en()
257 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) in xiic_clear_rx_fifo() argument
260 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_clear_rx_fifo()
262 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) in xiic_clear_rx_fifo()
263 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_clear_rx_fifo()
266 static void xiic_reinit(struct xiic_i2c *i2c) in xiic_reinit() argument
268 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_reinit()
271 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); in xiic_reinit()
274 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_reinit()
277 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); in xiic_reinit()
280 xiic_clear_rx_fifo(i2c); in xiic_reinit()
283 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); in xiic_reinit()
285 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); in xiic_reinit()
288 static void xiic_deinit(struct xiic_i2c *i2c) in xiic_deinit() argument
292 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); in xiic_deinit()
295 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); in xiic_deinit()
296 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); in xiic_deinit()
299 static void xiic_read_rx(struct xiic_i2c *i2c) in xiic_read_rx() argument
304 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; in xiic_read_rx()
306 dev_dbg(i2c->adap.dev.parent, in xiic_read_rx()
308 __func__, bytes_in_fifo, xiic_rx_space(i2c), in xiic_read_rx()
309 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_read_rx()
310 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_read_rx()
312 if (bytes_in_fifo > xiic_rx_space(i2c)) in xiic_read_rx()
313 bytes_in_fifo = xiic_rx_space(i2c); in xiic_read_rx()
316 i2c->rx_msg->buf[i2c->rx_pos++] = in xiic_read_rx()
317 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); in xiic_read_rx()
319 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, in xiic_read_rx()
320 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? in xiic_read_rx()
321 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); in xiic_read_rx()
324 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) in xiic_tx_fifo_space() argument
327 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; in xiic_tx_fifo_space()
330 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) in xiic_fill_tx_fifo() argument
332 u8 fifo_space = xiic_tx_fifo_space(i2c); in xiic_fill_tx_fifo()
333 int len = xiic_tx_space(i2c); in xiic_fill_tx_fifo()
337 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", in xiic_fill_tx_fifo()
341 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; in xiic_fill_tx_fifo()
342 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { in xiic_fill_tx_fifo()
345 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); in xiic_fill_tx_fifo()
347 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_fill_tx_fifo()
351 static void xiic_wakeup(struct xiic_i2c *i2c, int code) in xiic_wakeup() argument
353 i2c->tx_msg = NULL; in xiic_wakeup()
354 i2c->rx_msg = NULL; in xiic_wakeup()
355 i2c->nmsgs = 0; in xiic_wakeup()
356 i2c->state = code; in xiic_wakeup()
357 wake_up(&i2c->wait); in xiic_wakeup()
362 struct xiic_i2c *i2c = dev_id; in xiic_process() local
371 mutex_lock(&i2c->lock); in xiic_process()
372 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_process()
373 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_process()
376 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", in xiic_process()
378 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", in xiic_process()
379 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), in xiic_process()
380 i2c->tx_msg, i2c->nmsgs); in xiic_process()
393 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); in xiic_process()
399 xiic_reinit(i2c); in xiic_process()
401 if (i2c->rx_msg) in xiic_process()
402 xiic_wakeup(i2c, STATE_ERROR); in xiic_process()
403 if (i2c->tx_msg) in xiic_process()
404 xiic_wakeup(i2c, STATE_ERROR); in xiic_process()
410 if (!i2c->rx_msg) { in xiic_process()
411 dev_dbg(i2c->adap.dev.parent, in xiic_process()
413 xiic_clear_rx_fifo(i2c); in xiic_process()
417 xiic_read_rx(i2c); in xiic_process()
418 if (xiic_rx_space(i2c) == 0) { in xiic_process()
420 i2c->rx_msg = NULL; in xiic_process()
425 dev_dbg(i2c->adap.dev.parent, in xiic_process()
427 __func__, i2c->nmsgs); in xiic_process()
433 if (i2c->nmsgs > 1) { in xiic_process()
434 i2c->nmsgs--; in xiic_process()
435 i2c->tx_msg++; in xiic_process()
436 dev_dbg(i2c->adap.dev.parent, in xiic_process()
439 __xiic_start_xfer(i2c); in xiic_process()
448 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); in xiic_process()
450 if (!i2c->tx_msg) in xiic_process()
453 if ((i2c->nmsgs == 1) && !i2c->rx_msg && in xiic_process()
454 xiic_tx_space(i2c) == 0) in xiic_process()
455 xiic_wakeup(i2c, STATE_DONE); in xiic_process()
457 xiic_wakeup(i2c, STATE_ERROR); in xiic_process()
465 if (!i2c->tx_msg) { in xiic_process()
466 dev_dbg(i2c->adap.dev.parent, in xiic_process()
471 xiic_fill_tx_fifo(i2c); in xiic_process()
474 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { in xiic_process()
475 dev_dbg(i2c->adap.dev.parent, in xiic_process()
477 __func__, i2c->nmsgs); in xiic_process()
478 if (i2c->nmsgs > 1) { in xiic_process()
479 i2c->nmsgs--; in xiic_process()
480 i2c->tx_msg++; in xiic_process()
481 __xiic_start_xfer(i2c); in xiic_process()
483 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_process()
485 dev_dbg(i2c->adap.dev.parent, in xiic_process()
489 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) in xiic_process()
493 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); in xiic_process()
496 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); in xiic_process()
498 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); in xiic_process()
499 mutex_unlock(&i2c->lock); in xiic_process()
503 static int xiic_bus_busy(struct xiic_i2c *i2c) in xiic_bus_busy() argument
505 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); in xiic_bus_busy()
510 static int xiic_busy(struct xiic_i2c *i2c) in xiic_busy() argument
515 if (i2c->tx_msg) in xiic_busy()
522 err = xiic_bus_busy(i2c); in xiic_busy()
525 err = xiic_bus_busy(i2c); in xiic_busy()
531 static void xiic_start_recv(struct xiic_i2c *i2c) in xiic_start_recv() argument
534 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; in xiic_start_recv()
538 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); in xiic_start_recv()
549 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); in xiic_start_recv()
554 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
557 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
559 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, in xiic_start_recv()
560 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); in xiic_start_recv()
563 if (i2c->nmsgs == 1) in xiic_start_recv()
565 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); in xiic_start_recv()
568 i2c->tx_pos = msg->len; in xiic_start_recv()
571 static void xiic_start_send(struct xiic_i2c *i2c) in xiic_start_send() argument
573 struct i2c_msg *msg = i2c->tx_msg; in xiic_start_send()
575 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); in xiic_start_send()
577 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", in xiic_start_send()
579 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", in xiic_start_send()
580 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), in xiic_start_send()
581 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); in xiic_start_send()
587 if ((i2c->nmsgs == 1) && msg->len == 0) in xiic_start_send()
591 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); in xiic_start_send()
594 xiic_fill_tx_fifo(i2c); in xiic_start_send()
597 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | in xiic_start_send()
603 struct xiic_i2c *i2c = dev_id; in xiic_isr() local
610 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); in xiic_isr()
612 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); in xiic_isr()
613 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); in xiic_isr()
621 static void __xiic_start_xfer(struct xiic_i2c *i2c) in __xiic_start_xfer() argument
624 int fifo_space = xiic_tx_fifo_space(i2c); in __xiic_start_xfer()
625 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", in __xiic_start_xfer()
626 __func__, i2c->tx_msg, fifo_space); in __xiic_start_xfer()
628 if (!i2c->tx_msg) in __xiic_start_xfer()
631 i2c->rx_pos = 0; in __xiic_start_xfer()
632 i2c->tx_pos = 0; in __xiic_start_xfer()
633 i2c->state = STATE_START; in __xiic_start_xfer()
634 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { in __xiic_start_xfer()
636 i2c->nmsgs--; in __xiic_start_xfer()
637 i2c->tx_msg++; in __xiic_start_xfer()
638 i2c->tx_pos = 0; in __xiic_start_xfer()
642 if (i2c->tx_msg->flags & I2C_M_RD) { in __xiic_start_xfer()
644 xiic_start_recv(i2c); in __xiic_start_xfer()
647 xiic_start_send(i2c); in __xiic_start_xfer()
648 if (xiic_tx_space(i2c) != 0) { in __xiic_start_xfer()
654 fifo_space = xiic_tx_fifo_space(i2c); in __xiic_start_xfer()
660 if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) in __xiic_start_xfer()
661 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); in __xiic_start_xfer()
665 static void xiic_start_xfer(struct xiic_i2c *i2c) in xiic_start_xfer() argument
667 mutex_lock(&i2c->lock); in xiic_start_xfer()
668 xiic_reinit(i2c); in xiic_start_xfer()
669 __xiic_start_xfer(i2c); in xiic_start_xfer()
670 mutex_unlock(&i2c->lock); in xiic_start_xfer()
675 struct xiic_i2c *i2c = i2c_get_adapdata(adap); in xiic_xfer() local
679 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); in xiic_xfer()
681 err = pm_runtime_get_sync(i2c->dev); in xiic_xfer()
685 err = xiic_busy(i2c); in xiic_xfer()
689 i2c->tx_msg = msgs; in xiic_xfer()
690 i2c->nmsgs = num; in xiic_xfer()
692 xiic_start_xfer(i2c); in xiic_xfer()
694 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || in xiic_xfer()
695 (i2c->state == STATE_DONE), HZ)) { in xiic_xfer()
696 err = (i2c->state == STATE_DONE) ? num : -EIO; in xiic_xfer()
699 i2c->tx_msg = NULL; in xiic_xfer()
700 i2c->rx_msg = NULL; in xiic_xfer()
701 i2c->nmsgs = 0; in xiic_xfer()
706 pm_runtime_mark_last_busy(i2c->dev); in xiic_xfer()
707 pm_runtime_put_autosuspend(i2c->dev); in xiic_xfer()
736 struct xiic_i2c *i2c; in xiic_i2c_probe() local
743 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); in xiic_i2c_probe()
744 if (!i2c) in xiic_i2c_probe()
748 i2c->base = devm_ioremap_resource(&pdev->dev, res); in xiic_i2c_probe()
749 if (IS_ERR(i2c->base)) in xiic_i2c_probe()
750 return PTR_ERR(i2c->base); in xiic_i2c_probe()
759 platform_set_drvdata(pdev, i2c); in xiic_i2c_probe()
760 i2c->adap = xiic_adapter; in xiic_i2c_probe()
761 i2c_set_adapdata(&i2c->adap, i2c); in xiic_i2c_probe()
762 i2c->adap.dev.parent = &pdev->dev; in xiic_i2c_probe()
763 i2c->adap.dev.of_node = pdev->dev.of_node; in xiic_i2c_probe()
765 mutex_init(&i2c->lock); in xiic_i2c_probe()
766 init_waitqueue_head(&i2c->wait); in xiic_i2c_probe()
768 i2c->clk = devm_clk_get(&pdev->dev, NULL); in xiic_i2c_probe()
769 if (IS_ERR(i2c->clk)) { in xiic_i2c_probe()
771 return PTR_ERR(i2c->clk); in xiic_i2c_probe()
773 ret = clk_prepare_enable(i2c->clk); in xiic_i2c_probe()
778 i2c->dev = &pdev->dev; in xiic_i2c_probe()
779 pm_runtime_enable(i2c->dev); in xiic_i2c_probe()
780 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); in xiic_i2c_probe()
781 pm_runtime_use_autosuspend(i2c->dev); in xiic_i2c_probe()
782 pm_runtime_set_active(i2c->dev); in xiic_i2c_probe()
785 pdev->name, i2c); in xiic_i2c_probe()
797 i2c->endianness = LITTLE; in xiic_i2c_probe()
798 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); in xiic_i2c_probe()
800 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); in xiic_i2c_probe()
802 i2c->endianness = BIG; in xiic_i2c_probe()
804 xiic_reinit(i2c); in xiic_i2c_probe()
806 /* add i2c adapter to i2c tree */ in xiic_i2c_probe()
807 ret = i2c_add_adapter(&i2c->adap); in xiic_i2c_probe()
809 xiic_deinit(i2c); in xiic_i2c_probe()
816 i2c_new_device(&i2c->adap, pdata->devices + i); in xiic_i2c_probe()
824 clk_disable_unprepare(i2c->clk); in xiic_i2c_probe()
830 struct xiic_i2c *i2c = platform_get_drvdata(pdev); in xiic_i2c_remove() local
834 i2c_del_adapter(&i2c->adap); in xiic_i2c_remove()
836 ret = clk_prepare_enable(i2c->clk); in xiic_i2c_remove()
841 xiic_deinit(i2c); in xiic_i2c_remove()
842 clk_disable_unprepare(i2c->clk); in xiic_i2c_remove()
858 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_suspend() local
860 clk_disable(i2c->clk); in xiic_i2c_runtime_suspend()
867 struct xiic_i2c *i2c = dev_get_drvdata(dev); in xiic_i2c_runtime_resume() local
870 ret = clk_enable(i2c->clk); in xiic_i2c_runtime_resume()
896 MODULE_DESCRIPTION("Xilinx I2C bus driver");