24 	{	XFER_UDMA_6,	0x31,	0x07	},
25 	{	XFER_UDMA_5,	0x31,	0x06	},
26 	{	XFER_UDMA_4,	0x31,	0x05	},
27 	{	XFER_UDMA_3,	0x31,	0x04	},
28 	{	XFER_UDMA_2,	0x31,	0x03	},
29 	{	XFER_UDMA_1,	0x31,	0x02	},
30 	{	XFER_UDMA_0,	0x31,	0x01	},
32 	{	XFER_MW_DMA_2,	0x31,	0x00	},
33 	{	XFER_MW_DMA_1,	0x31,	0x00	},
34 	{	XFER_MW_DMA_0,	0x0a,	0x00	},
35 	{	XFER_PIO_4,	0x31,	0x00	},
36 	{	XFER_PIO_3,	0x33,	0x00	},
37 	{	XFER_PIO_2,	0x08,	0x00	},
38 	{	XFER_PIO_1,	0x0a,	0x00	},
39 	{	XFER_PIO_0,	0x00,	0x00	},
40 	{	0,		0x00,	0x00	}
44 	{	XFER_UDMA_6,	0x41,	0x06	},
45 	{	XFER_UDMA_5,	0x41,	0x05	},
46 	{	XFER_UDMA_4,	0x41,	0x04	},
47 	{	XFER_UDMA_3,	0x41,	0x03	},
48 	{	XFER_UDMA_2,	0x41,	0x02	},
49 	{	XFER_UDMA_1,	0x41,	0x01	},
50 	{	XFER_UDMA_0,	0x41,	0x01	},
52 	{	XFER_MW_DMA_2,	0x41,	0x00	},
53 	{	XFER_MW_DMA_1,	0x42,	0x00	},
54 	{	XFER_MW_DMA_0,	0x7a,	0x00	},
55 	{	XFER_PIO_4,	0x41,	0x00	},
56 	{	XFER_PIO_3,	0x43,	0x00	},
57 	{	XFER_PIO_2,	0x78,	0x00	},
58 	{	XFER_PIO_1,	0x7a,	0x00	},
59 	{	XFER_PIO_0,	0x70,	0x00	},
60 	{	0,		0x00,	0x00	}
89 	u16 d_conf		= 0;  in aec6210_set_mode()
90 	u8 ultra = 0, ultra_conf = 0;  in aec6210_set_mode()
91 	u8 tmp0 = 0, tmp1 = 0, tmp2 = 0;  in aec6210_set_mode()
96 	/* 0x40|(2*drive->dn): Active, 0x41|(2*drive->dn): Recovery */  in aec6210_set_mode()
97 	pci_read_config_word(dev, 0x40|(2*drive->dn), &d_conf);  in aec6210_set_mode()
99 	d_conf = ((tmp0 & 0xf0) << 4) | (tmp0 & 0xf);  in aec6210_set_mode()
100 	pci_write_config_word(dev, 0x40|(2*drive->dn), d_conf);  in aec6210_set_mode()
102 	tmp1 = 0x00;  in aec6210_set_mode()
103 	tmp2 = 0x00;  in aec6210_set_mode()
104 	pci_read_config_byte(dev, 0x54, &ultra);  in aec6210_set_mode()
105 	tmp1 = ((0x00 << (2*drive->dn)) | (ultra & ~(3 << (2*drive->dn))));  in aec6210_set_mode()
108 	pci_write_config_byte(dev, 0x54, tmp2);  in aec6210_set_mode()
118 	u8 tmp1 = 0, tmp2 = 0;  in aec6260_set_mode()
119 	u8 ultra = 0, drive_conf = 0, ultra_conf = 0;  in aec6260_set_mode()
125 	pci_read_config_byte(dev, 0x40|drive->dn, &drive_conf);  in aec6260_set_mode()
127 	pci_write_config_byte(dev, 0x40|drive->dn, drive_conf);  in aec6260_set_mode()
129 	pci_read_config_byte(dev, (0x44|hwif->channel), &ultra);  in aec6260_set_mode()
130 	tmp1 = ((0x00 << (4*unit)) | (ultra & ~(7 << (4*unit))));  in aec6260_set_mode()
133 	pci_write_config_byte(dev, (0x44|hwif->channel), tmp2);  in aec6260_set_mode()
148 		u8 reg49h = 0, reg4ah = 0;  in init_chipset_aec62xx()
150 		pci_read_config_byte(dev, 0x49, &reg49h);  in init_chipset_aec62xx()
151 		pci_write_config_byte(dev, 0x49, reg49h & ~0x30);  in init_chipset_aec62xx()
153 		pci_read_config_byte(dev, 0x4a, &reg4ah);  in init_chipset_aec62xx()
154 		pci_write_config_byte(dev, 0x4a, reg4ah & ~0x01);  in init_chipset_aec62xx()
156 		pci_read_config_byte(dev, 0x4a, &reg4ah);  in init_chipset_aec62xx()
157 		pci_write_config_byte(dev, 0x4a, reg4ah | 0x80);  in init_chipset_aec62xx()
160 	return 0;  in init_chipset_aec62xx()
166 	u8 ata66 = 0, mask = hwif->channel ? 0x02 : 0x01;  in atp86x_cable_detect()
168 	pci_read_config_byte(dev, 0x49, &ata66);  in atp86x_cable_detect()
185 	{	/* 0: AEC6210 */
188 		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
211 		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
232 		.enablebits	= {{0x4a,0x02,0x02}, {0x4a,0x04,0x04}},
276 		if (inb(dma_base + 2) & 0x10) {  in aec62xx_init_one()
297 	{ PCI_VDEVICE(ARTOP, PCI_DEVICE_ID_ARTOP_ATP850UF), 0 },
302 	{ 0, },