2  * Amlogic Meson Successive Approximation Register (SAR) A/D Converter
16 #include <linux/clk-provider.h>
100 					(8 + (((_chan) - 2) * 3))
158  * and u-boot source served as reference). These only seem to be relevant on
270 	regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);  in meson_sar_adc_get_fifo_count()
281 	tmp = div_s64((s64)val * priv->calibscale, MILLION) + priv->calibbias;  in meson_sar_adc_calib_val()
283 	return clamp(tmp, 0, (1 << priv->data->param->resolution) - 1);  in meson_sar_adc_calib_val()
298 		regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);  in meson_sar_adc_wait_busy_clear()
299 	} while (FIELD_GET(MESON_SAR_ADC_REG0_BUSY_MASK, regval) && timeout--);  in meson_sar_adc_wait_busy_clear()
302 		return -ETIMEDOUT;  in meson_sar_adc_wait_busy_clear()
314 	if(!wait_for_completion_timeout(&priv->done,  in meson_sar_adc_read_raw_sample()
316 		return -ETIMEDOUT;  in meson_sar_adc_read_raw_sample()
320 		dev_err(&indio_dev->dev,  in meson_sar_adc_read_raw_sample()
322 		return -EINVAL;  in meson_sar_adc_read_raw_sample()
325 	regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &regval);  in meson_sar_adc_read_raw_sample()
327 	if (fifo_chan != chan->channel) {  in meson_sar_adc_read_raw_sample()
328 		dev_err(&indio_dev->dev,  in meson_sar_adc_read_raw_sample()
330 			fifo_chan, chan->channel);  in meson_sar_adc_read_raw_sample()
331 		return -EINVAL;  in meson_sar_adc_read_raw_sample()
335 	fifo_val &= GENMASK(priv->data->param->resolution - 1, 0);  in meson_sar_adc_read_raw_sample()
347 	int val, channel = chan->channel;  in meson_sar_adc_set_averaging()
350 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,  in meson_sar_adc_set_averaging()
355 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_AVG_CNTL,  in meson_sar_adc_set_averaging()
371 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,  in meson_sar_adc_enable_channel()
376 			    chan->channel);  in meson_sar_adc_enable_channel()
377 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_LIST,  in meson_sar_adc_enable_channel()
381 			    chan->channel);  in meson_sar_adc_enable_channel()
382 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,  in meson_sar_adc_enable_channel()
387 			    chan->channel);  in meson_sar_adc_enable_channel()
388 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DETECT_IDLE_SW,  in meson_sar_adc_enable_channel()
392 	if (chan->channel == 6)  in meson_sar_adc_enable_channel()
393 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELTA_10,  in meson_sar_adc_enable_channel()
404 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_set_chan7_mux()
414 	reinit_completion(&priv->done);  in meson_sar_adc_start_sample_engine()
416 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_start_sample_engine()
420 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_start_sample_engine()
424 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_start_sample_engine()
433 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_stop_sample_engine()
436 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_stop_sample_engine()
443 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_stop_sample_engine()
452 	mutex_lock(&indio_dev->mlock);  in meson_sar_adc_lock()
454 	if (priv->data->param->has_bl30_integration) {  in meson_sar_adc_lock()
456 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_lock()
466 			regmap_read(priv->regmap, MESON_SAR_ADC_DELAY, &val);  in meson_sar_adc_lock()
467 		} while (val & MESON_SAR_ADC_DELAY_BL30_BUSY && timeout--);  in meson_sar_adc_lock()
470 			mutex_unlock(&indio_dev->mlock);  in meson_sar_adc_lock()
471 			return -ETIMEDOUT;  in meson_sar_adc_lock()
482 	if (priv->data->param->has_bl30_integration)  in meson_sar_adc_unlock()
484 		regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_unlock()
487 	mutex_unlock(&indio_dev->mlock);  in meson_sar_adc_unlock()
499 		regmap_read(priv->regmap, MESON_SAR_ADC_FIFO_RD, &tmp);  in meson_sar_adc_clear_fifo()
529 		dev_warn(indio_dev->dev.parent,  in meson_sar_adc_get_sample()
531 			 chan->channel, ret);  in meson_sar_adc_get_sample()
558 		ret = regulator_get_voltage(priv->vref);  in meson_sar_adc_iio_info_read_raw()
560 			dev_err(indio_dev->dev.parent,  in meson_sar_adc_iio_info_read_raw()
566 		*val2 = priv->data->param->resolution;  in meson_sar_adc_iio_info_read_raw()
570 		*val = priv->calibbias;  in meson_sar_adc_iio_info_read_raw()
574 		*val = priv->calibscale / MILLION;  in meson_sar_adc_iio_info_read_raw()
575 		*val2 = priv->calibscale % MILLION;  in meson_sar_adc_iio_info_read_raw()
579 		return -EINVAL;  in meson_sar_adc_iio_info_read_raw()
590 	init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_div",  in meson_sar_adc_clk_init()
591 				   dev_name(indio_dev->dev.parent));  in meson_sar_adc_clk_init()
593 		return -ENOMEM;  in meson_sar_adc_clk_init()
597 	clk_parents[0] = __clk_get_name(priv->clkin);  in meson_sar_adc_clk_init()
601 	priv->clk_div.reg = base + MESON_SAR_ADC_REG3;  in meson_sar_adc_clk_init()
602 	priv->clk_div.shift = MESON_SAR_ADC_REG3_ADC_CLK_DIV_SHIFT;  in meson_sar_adc_clk_init()
603 	priv->clk_div.width = MESON_SAR_ADC_REG3_ADC_CLK_DIV_WIDTH;  in meson_sar_adc_clk_init()
604 	priv->clk_div.hw.init = &init;  in meson_sar_adc_clk_init()
605 	priv->clk_div.flags = 0;  in meson_sar_adc_clk_init()
607 	priv->adc_div_clk = devm_clk_register(&indio_dev->dev,  in meson_sar_adc_clk_init()
608 					      &priv->clk_div.hw);  in meson_sar_adc_clk_init()
609 	if (WARN_ON(IS_ERR(priv->adc_div_clk)))  in meson_sar_adc_clk_init()
610 		return PTR_ERR(priv->adc_div_clk);  in meson_sar_adc_clk_init()
612 	init.name = devm_kasprintf(&indio_dev->dev, GFP_KERNEL, "%s#adc_en",  in meson_sar_adc_clk_init()
613 				   dev_name(indio_dev->dev.parent));  in meson_sar_adc_clk_init()
615 		return -ENOMEM;  in meson_sar_adc_clk_init()
619 	clk_parents[0] = __clk_get_name(priv->adc_div_clk);  in meson_sar_adc_clk_init()
623 	priv->clk_gate.reg = base + MESON_SAR_ADC_REG3;  in meson_sar_adc_clk_init()
624 	priv->clk_gate.bit_idx = __ffs(MESON_SAR_ADC_REG3_CLK_EN);  in meson_sar_adc_clk_init()
625 	priv->clk_gate.hw.init = &init;  in meson_sar_adc_clk_init()
627 	priv->adc_clk = devm_clk_register(&indio_dev->dev, &priv->clk_gate.hw);  in meson_sar_adc_clk_init()
628 	if (WARN_ON(IS_ERR(priv->adc_clk)))  in meson_sar_adc_clk_init()
629 		return PTR_ERR(priv->adc_clk);  in meson_sar_adc_clk_init()
645 	if (priv->data->param->has_bl30_integration) {  in meson_sar_adc_init()
651 		regmap_read(priv->regmap, MESON_SAR_ADC_REG3, &regval);  in meson_sar_adc_init()
659 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_init()
664 	regmap_write(priv->regmap, MESON_SAR_ADC_CHAN_LIST, 0x0);  in meson_sar_adc_init()
666 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_init()
668 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_init()
673 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_init()
677 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_init()
683 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_init()
687 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_DELAY,  in meson_sar_adc_init()
697 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,  in meson_sar_adc_init()
701 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_CHAN_10_SW,  in meson_sar_adc_init()
716 	regmap_write(priv->regmap, MESON_SAR_ADC_AUX_SW, regval);  in meson_sar_adc_init()
718 	ret = clk_set_parent(priv->adc_sel_clk, priv->clkin);  in meson_sar_adc_init()
720 		dev_err(indio_dev->dev.parent,  in meson_sar_adc_init()
725 	ret = clk_set_rate(priv->adc_clk, priv->data->param->clock_rate);  in meson_sar_adc_init()
727 		dev_err(indio_dev->dev.parent,  in meson_sar_adc_init()
738 	const struct meson_sar_adc_param *param = priv->data->param;  in meson_sar_adc_set_bandgap()
741 	if (param->bandgap_reg == MESON_SAR_ADC_REG11)  in meson_sar_adc_set_bandgap()
746 	regmap_update_bits(priv->regmap, param->bandgap_reg, enable_mask,  in meson_sar_adc_set_bandgap()
760 	ret = regulator_enable(priv->vref);  in meson_sar_adc_hw_enable()
762 		dev_err(indio_dev->dev.parent,  in meson_sar_adc_hw_enable()
767 	ret = clk_prepare_enable(priv->core_clk);  in meson_sar_adc_hw_enable()
769 		dev_err(indio_dev->dev.parent, "failed to enable core clk\n");  in meson_sar_adc_hw_enable()
774 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG0,  in meson_sar_adc_hw_enable()
779 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_enable()
785 	ret = clk_prepare_enable(priv->adc_clk);  in meson_sar_adc_hw_enable()
787 		dev_err(indio_dev->dev.parent, "failed to enable adc clk\n");  in meson_sar_adc_hw_enable()
796 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_enable()
799 	clk_disable_unprepare(priv->core_clk);  in meson_sar_adc_hw_enable()
801 	regulator_disable(priv->vref);  in meson_sar_adc_hw_enable()
817 	clk_disable_unprepare(priv->adc_clk);  in meson_sar_adc_hw_disable()
819 	regmap_update_bits(priv->regmap, MESON_SAR_ADC_REG3,  in meson_sar_adc_hw_disable()
824 	clk_disable_unprepare(priv->core_clk);  in meson_sar_adc_hw_disable()
826 	regulator_disable(priv->vref);  in meson_sar_adc_hw_disable()
840 	regmap_read(priv->regmap, MESON_SAR_ADC_REG0, &regval);  in meson_sar_adc_irq()
847 	complete(&priv->done);  in meson_sar_adc_irq()
858 	nominal0 = (1 << priv->data->param->resolution) / 4;  in meson_sar_adc_calib()
859 	nominal1 = (1 << priv->data->param->resolution) * 3 / 4;  in meson_sar_adc_calib()
878 		ret = -EINVAL;  in meson_sar_adc_calib()
882 	priv->calibscale = div_s64((nominal1 - nominal0) * (s64)MILLION,  in meson_sar_adc_calib()
883 				   value1 - value0);  in meson_sar_adc_calib()
884 	priv->calibbias = nominal0 - div_s64((s64)value0 * priv->calibscale,  in meson_sar_adc_calib()
923 	.name = "meson-meson8-saradc",
928 	.name = "meson-meson8b-saradc",
933 	.name = "meson-meson8m2-saradc",
938 	.name = "meson-gxbb-saradc",
943 	.name = "meson-gxl-saradc",
948 	.name = "meson-gxm-saradc",
953 	.name = "meson-axg-saradc",
958 		.compatible = "amlogic,meson8-saradc",
962 		.compatible = "amlogic,meson8b-saradc",
966 		.compatible = "amlogic,meson8m2-saradc",
970 		.compatible = "amlogic,meson-gxbb-saradc",
973 		.compatible = "amlogic,meson-gxl-saradc",
976 		.compatible = "amlogic,meson-gxm-saradc",
979 		.compatible = "amlogic,meson-axg-saradc",
995 	indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*priv));  in meson_sar_adc_probe()
997 		dev_err(&pdev->dev, "failed allocating iio device\n");  in meson_sar_adc_probe()
998 		return -ENOMEM;  in meson_sar_adc_probe()
1002 	init_completion(&priv->done);  in meson_sar_adc_probe()
1004 	match = of_match_device(meson_sar_adc_of_match, &pdev->dev);  in meson_sar_adc_probe()
1006 		dev_err(&pdev->dev, "failed to match device\n");  in meson_sar_adc_probe()
1007 		return -ENODEV;  in meson_sar_adc_probe()
1010 	priv->data = match->data;  in meson_sar_adc_probe()
1012 	indio_dev->name = priv->data->name;  in meson_sar_adc_probe()
1013 	indio_dev->dev.parent = &pdev->dev;  in meson_sar_adc_probe()
1014 	indio_dev->dev.of_node = pdev->dev.of_node;  in meson_sar_adc_probe()
1015 	indio_dev->modes = INDIO_DIRECT_MODE;  in meson_sar_adc_probe()
1016 	indio_dev->info = &meson_sar_adc_iio_info;  in meson_sar_adc_probe()
1018 	indio_dev->channels = meson_sar_adc_iio_channels;  in meson_sar_adc_probe()
1019 	indio_dev->num_channels = ARRAY_SIZE(meson_sar_adc_iio_channels);  in meson_sar_adc_probe()
1022 	base = devm_ioremap_resource(&pdev->dev, res);  in meson_sar_adc_probe()
1026 	priv->regmap = devm_regmap_init_mmio(&pdev->dev, base,  in meson_sar_adc_probe()
1027 					     priv->data->param->regmap_config);  in meson_sar_adc_probe()
1028 	if (IS_ERR(priv->regmap))  in meson_sar_adc_probe()
1029 		return PTR_ERR(priv->regmap);  in meson_sar_adc_probe()
1031 	irq = irq_of_parse_and_map(pdev->dev.of_node, 0);  in meson_sar_adc_probe()
1033 		return -EINVAL;  in meson_sar_adc_probe()
1035 	ret = devm_request_irq(&pdev->dev, irq, meson_sar_adc_irq, IRQF_SHARED,  in meson_sar_adc_probe()
1036 			       dev_name(&pdev->dev), indio_dev);  in meson_sar_adc_probe()
1040 	priv->clkin = devm_clk_get(&pdev->dev, "clkin");  in meson_sar_adc_probe()
1041 	if (IS_ERR(priv->clkin)) {  in meson_sar_adc_probe()
1042 		dev_err(&pdev->dev, "failed to get clkin\n");  in meson_sar_adc_probe()
1043 		return PTR_ERR(priv->clkin);  in meson_sar_adc_probe()
1046 	priv->core_clk = devm_clk_get(&pdev->dev, "core");  in meson_sar_adc_probe()
1047 	if (IS_ERR(priv->core_clk)) {  in meson_sar_adc_probe()
1048 		dev_err(&pdev->dev, "failed to get core clk\n");  in meson_sar_adc_probe()
1049 		return PTR_ERR(priv->core_clk);  in meson_sar_adc_probe()
1052 	priv->adc_clk = devm_clk_get(&pdev->dev, "adc_clk");  in meson_sar_adc_probe()
1053 	if (IS_ERR(priv->adc_clk)) {  in meson_sar_adc_probe()
1054 		if (PTR_ERR(priv->adc_clk) == -ENOENT) {  in meson_sar_adc_probe()
1055 			priv->adc_clk = NULL;  in meson_sar_adc_probe()
1057 			dev_err(&pdev->dev, "failed to get adc clk\n");  in meson_sar_adc_probe()
1058 			return PTR_ERR(priv->adc_clk);  in meson_sar_adc_probe()
1062 	priv->adc_sel_clk = devm_clk_get(&pdev->dev, "adc_sel");  in meson_sar_adc_probe()
1063 	if (IS_ERR(priv->adc_sel_clk)) {  in meson_sar_adc_probe()
1064 		if (PTR_ERR(priv->adc_sel_clk) == -ENOENT) {  in meson_sar_adc_probe()
1065 			priv->adc_sel_clk = NULL;  in meson_sar_adc_probe()
1067 			dev_err(&pdev->dev, "failed to get adc_sel clk\n");  in meson_sar_adc_probe()
1068 			return PTR_ERR(priv->adc_sel_clk);  in meson_sar_adc_probe()
1072 	/* on pre-GXBB SoCs the SAR ADC itself provides the ADC clock: */  in meson_sar_adc_probe()
1073 	if (!priv->adc_clk) {  in meson_sar_adc_probe()
1079 	priv->vref = devm_regulator_get(&pdev->dev, "vref");  in meson_sar_adc_probe()
1080 	if (IS_ERR(priv->vref)) {  in meson_sar_adc_probe()
1081 		dev_err(&pdev->dev, "failed to get vref regulator\n");  in meson_sar_adc_probe()
1082 		return PTR_ERR(priv->vref);  in meson_sar_adc_probe()
1085 	priv->calibscale = MILLION;  in meson_sar_adc_probe()
1097 		dev_warn(&pdev->dev, "calibration failed\n");  in meson_sar_adc_probe()
1143 		.name	= "meson-saradc",
1152 MODULE_DESCRIPTION("Amlogic Meson SAR ADC driver");