Lines Matching +full:sc2731 +full:- +full:adc
1 // SPDX-License-Identifier: GPL-2.0
20 /* ADC controller registers definition */
53 /* Maximum ADC channel number */
56 /* ADC voltage ratio definition */
67 * subsystems which will access the unique ADC controller.
85 * According to the datasheet, we can convert one ADC value to one voltage value
87 * should use the small-scale graph, and if more than 1.2v, we should use the
88 * big-scale graph.
131 reinit_completion(&data->completion); in sc27xx_adc_read()
133 ret = hwspin_lock_timeout_raw(data->hwlock, SC27XX_ADC_HWLOCK_TIMEOUT); in sc27xx_adc_read()
135 dev_err(data->dev, "timeout to get the hwspinlock\n"); in sc27xx_adc_read()
139 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, in sc27xx_adc_read()
147 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CH_CFG, in sc27xx_adc_read()
156 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, in sc27xx_adc_read()
162 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, in sc27xx_adc_read()
167 wait_for_completion(&data->completion); in sc27xx_adc_read()
170 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_CTL, in sc27xx_adc_read()
173 hwspin_unlock_raw(data->hwlock); in sc27xx_adc_read()
176 *val = data->value; in sc27xx_adc_read()
186 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_CLR, in sc27xx_adc_isr()
191 ret = regmap_read(data->regmap, data->base + SC27XX_ADC_DATA, in sc27xx_adc_isr()
192 &data->value); in sc27xx_adc_isr()
196 data->value &= SC27XX_ADC_DATA_MASK; in sc27xx_adc_isr()
197 complete(&data->completion); in sc27xx_adc_isr()
217 tmp = (graph->volt0 - graph->volt1) * (raw_adc - graph->adc1); in sc27xx_adc_to_volt()
218 tmp /= (graph->adc0 - graph->adc1); in sc27xx_adc_to_volt()
219 tmp += graph->volt1; in sc27xx_adc_to_volt()
231 * Convert ADC values to voltage values according to the linear graph, in sc27xx_adc_convert_volt()
272 int scale = data->channel_scale[chan->channel]; in sc27xx_adc_read_raw()
277 mutex_lock(&indio_dev->mlock); in sc27xx_adc_read_raw()
278 ret = sc27xx_adc_read_processed(data, chan->channel, scale, in sc27xx_adc_read_raw()
280 mutex_unlock(&indio_dev->mlock); in sc27xx_adc_read_raw()
293 return -EINVAL; in sc27xx_adc_read_raw()
305 data->channel_scale[chan->channel] = val; in sc27xx_adc_write_raw()
309 return -EINVAL; in sc27xx_adc_write_raw()
366 ret = regmap_update_bits(data->regmap, SC27XX_MODULE_EN, in sc27xx_adc_enable()
371 /* Enable ADC work clock and controller clock */ in sc27xx_adc_enable()
372 ret = regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, in sc27xx_adc_enable()
378 ret = regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN, in sc27xx_adc_enable()
386 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, in sc27xx_adc_enable()
389 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, in sc27xx_adc_enable()
399 regmap_update_bits(data->regmap, data->base + SC27XX_ADC_INT_EN, in sc27xx_adc_disable()
402 /* Disable ADC work clock and controller clock */ in sc27xx_adc_disable()
403 regmap_update_bits(data->regmap, SC27XX_ARM_CLK_EN, in sc27xx_adc_disable()
406 regmap_update_bits(data->regmap, SC27XX_MODULE_EN, in sc27xx_adc_disable()
419 struct device_node *np = pdev->dev.of_node; in sc27xx_adc_probe()
424 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*sc27xx_data)); in sc27xx_adc_probe()
426 return -ENOMEM; in sc27xx_adc_probe()
430 sc27xx_data->regmap = dev_get_regmap(pdev->dev.parent, NULL); in sc27xx_adc_probe()
431 if (!sc27xx_data->regmap) { in sc27xx_adc_probe()
432 dev_err(&pdev->dev, "failed to get ADC regmap\n"); in sc27xx_adc_probe()
433 return -ENODEV; in sc27xx_adc_probe()
436 ret = of_property_read_u32(np, "reg", &sc27xx_data->base); in sc27xx_adc_probe()
438 dev_err(&pdev->dev, "failed to get ADC base address\n"); in sc27xx_adc_probe()
442 sc27xx_data->irq = platform_get_irq(pdev, 0); in sc27xx_adc_probe()
443 if (sc27xx_data->irq < 0) { in sc27xx_adc_probe()
444 dev_err(&pdev->dev, "failed to get ADC irq number\n"); in sc27xx_adc_probe()
445 return sc27xx_data->irq; in sc27xx_adc_probe()
450 dev_err(&pdev->dev, "failed to get hwspinlock id\n"); in sc27xx_adc_probe()
454 sc27xx_data->hwlock = hwspin_lock_request_specific(ret); in sc27xx_adc_probe()
455 if (!sc27xx_data->hwlock) { in sc27xx_adc_probe()
456 dev_err(&pdev->dev, "failed to request hwspinlock\n"); in sc27xx_adc_probe()
457 return -ENXIO; in sc27xx_adc_probe()
460 ret = devm_add_action(&pdev->dev, sc27xx_adc_free_hwlock, in sc27xx_adc_probe()
461 sc27xx_data->hwlock); in sc27xx_adc_probe()
463 sc27xx_adc_free_hwlock(sc27xx_data->hwlock); in sc27xx_adc_probe()
464 dev_err(&pdev->dev, "failed to add hwspinlock action\n"); in sc27xx_adc_probe()
468 init_completion(&sc27xx_data->completion); in sc27xx_adc_probe()
469 sc27xx_data->dev = &pdev->dev; in sc27xx_adc_probe()
473 dev_err(&pdev->dev, "failed to enable ADC module\n"); in sc27xx_adc_probe()
477 ret = devm_add_action(&pdev->dev, sc27xx_adc_disable, sc27xx_data); in sc27xx_adc_probe()
480 dev_err(&pdev->dev, "failed to add ADC disable action\n"); in sc27xx_adc_probe()
484 ret = devm_request_threaded_irq(&pdev->dev, sc27xx_data->irq, NULL, in sc27xx_adc_probe()
486 pdev->name, sc27xx_data); in sc27xx_adc_probe()
488 dev_err(&pdev->dev, "failed to request ADC irq\n"); in sc27xx_adc_probe()
492 indio_dev->dev.parent = &pdev->dev; in sc27xx_adc_probe()
493 indio_dev->name = dev_name(&pdev->dev); in sc27xx_adc_probe()
494 indio_dev->modes = INDIO_DIRECT_MODE; in sc27xx_adc_probe()
495 indio_dev->info = &sc27xx_info; in sc27xx_adc_probe()
496 indio_dev->channels = sc27xx_channels; in sc27xx_adc_probe()
497 indio_dev->num_channels = ARRAY_SIZE(sc27xx_channels); in sc27xx_adc_probe()
498 ret = devm_iio_device_register(&pdev->dev, indio_dev); in sc27xx_adc_probe()
500 dev_err(&pdev->dev, "could not register iio (ADC)"); in sc27xx_adc_probe()
506 { .compatible = "sprd,sc2731-adc", },
513 .name = "sc27xx-adc",
521 MODULE_DESCRIPTION("Spreadtrum SC27XX ADC Driver");