Lines Matching +full:diff +full:- +full:channels
1 // SPDX-License-Identifier: GPL-2.0
5 * Copyright (C) 2016, STMicroelectronics - All Rights Reserved
11 #include <linux/dma-mapping.h>
15 #include <linux/iio/timer/stm32-lptim-trigger.h>
16 #include <linux/iio/timer/stm32-timer-trigger.h>
28 #include "stm32-adc-core.h"
36 #define STM32_ADC_CH_MAX 20 /* max number of channels */
53 /* extsel - trigger mux selection value */
79 * struct stm32_adc_trig_info - ADC trigger info
89 * struct stm32_adc_calib - optional adc calibration data
90 * @calfact_s: Calibration offset for single ended channels
101 * stm32_adc_regs - stm32 ADC misc registers & bitfield desc
113 * stm32_adc_regspec - stm32 registers definition, compatible dependent data
139 * stm32_adc_cfg - stm32 compatible configuration data
141 * @adc_info: per instance input channels definitions
145 * @selfcalib: optional routine for self-calibration
146 * @prepare: optional prepare routine (power-up, enable)
149 * @unprepare: optional unprepare routine (disable, power-down)
167 * struct stm32_adc - private data of each ADC IIO instance
184 * @difsel bitmask to set single-ended/differential channel
185 * @pcsel bitmask to preselect channels on some devices
220 * struct stm32_adc_info - stm32 ADC, per instance config data
221 * @max_channels: Number of channels
236 /* stm32f4 can have up to 16 channels */
248 /* stm32h7 can have up to 20 channels */
256 * stm32f4_sq - describe regular sequence registers
257 * - L: sequence len (register & bit field)
258 * - SQ1..SQ16: sequence entries (register & bit field)
303 * stm32f4_smp_bits[] - describe sampling time register index & bit fields
394 * stm32h7_smp_bits - describe sampling time register index & bit fields
450 return readl_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readl()
461 return readw_relaxed(adc->common->base + adc->offset + reg); in stm32_adc_readw()
466 writel_relaxed(val, adc->common->base + adc->offset + reg); in stm32_adc_writel()
473 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_bits()
475 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_bits()
482 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_clr_bits()
484 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_clr_bits()
488 * stm32_adc_conv_irq_enable() - Enable end of conversion interrupt
493 stm32_adc_set_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_enable()
494 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_enable()
498 * stm32_adc_conv_irq_disable() - Disable end of conversion interrupt
503 stm32_adc_clr_bits(adc, adc->cfg->regs->ier_eoc.reg, in stm32_adc_conv_irq_disable()
504 adc->cfg->regs->ier_eoc.mask); in stm32_adc_conv_irq_disable()
509 const struct stm32_adc_regs *res = &adc->cfg->regs->res; in stm32_adc_set_res()
512 val = stm32_adc_readl(adc, res->reg); in stm32_adc_set_res()
513 val = (val & ~res->mask) | (adc->res << res->shift); in stm32_adc_set_res()
514 stm32_adc_writel(adc, res->reg, val); in stm32_adc_set_res()
518 * stm32f4_adc_start_conv() - Start conversions for regular channels.
522 * Start conversions for regular channels.
537 /* Wait for Power-up time (tSTAB from datasheet) */ in stm32f4_adc_start_conv()
566 spin_lock_irqsave(&adc->lock, flags); in stm32h7_adc_start_conv()
570 spin_unlock_irqrestore(&adc->lock, flags); in stm32h7_adc_start_conv()
587 dev_warn(&indio_dev->dev, "stop failed\n"); in stm32h7_adc_stop_conv()
602 if (adc->common->rate > STM32H7_BOOST_CLKRATE) in stm32h7_adc_exit_pwr_down()
606 if (!adc->cfg->has_vregready) { in stm32h7_adc_exit_pwr_down()
616 dev_err(&indio_dev->dev, "Failed to exit power down\n"); in stm32h7_adc_exit_pwr_down()
644 dev_err(&indio_dev->dev, "Failed to enable ADC\n"); in stm32h7_adc_enable()
665 dev_warn(&indio_dev->dev, "Failed to disable\n"); in stm32h7_adc_disable()
669 * stm32h7_adc_read_selfcalib() - read calibration shadow regs, save result
685 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { in stm32h7_adc_read_selfcalib()
694 dev_err(&indio_dev->dev, "Failed to read calfact\n"); in stm32h7_adc_read_selfcalib()
699 adc->cal.lincalfact[i] = (val & STM32H7_LINCALFACT_MASK); in stm32h7_adc_read_selfcalib()
700 adc->cal.lincalfact[i] >>= STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_read_selfcalib()
707 adc->cal.calfact_s = (val & STM32H7_CALFACT_S_MASK); in stm32h7_adc_read_selfcalib()
708 adc->cal.calfact_s >>= STM32H7_CALFACT_S_SHIFT; in stm32h7_adc_read_selfcalib()
709 adc->cal.calfact_d = (val & STM32H7_CALFACT_D_MASK); in stm32h7_adc_read_selfcalib()
710 adc->cal.calfact_d >>= STM32H7_CALFACT_D_SHIFT; in stm32h7_adc_read_selfcalib()
719 * stm32h7_adc_restore_selfcalib() - Restore saved self-calibration result
721 * Note: ADC must be enabled, with no on-going conversions.
729 val = (adc->cal.calfact_s << STM32H7_CALFACT_S_SHIFT) | in stm32h7_adc_restore_selfcalib()
730 (adc->cal.calfact_d << STM32H7_CALFACT_D_SHIFT); in stm32h7_adc_restore_selfcalib()
734 for (i = STM32H7_LINCALFACT_NUM - 1; i >= 0; i--) { in stm32h7_adc_restore_selfcalib()
740 val = adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT; in stm32h7_adc_restore_selfcalib()
747 dev_err(&indio_dev->dev, "Failed to write calfact\n"); in stm32h7_adc_restore_selfcalib()
753 * - It ensures bits LINCALRDYW[6..1] are kept cleared in stm32h7_adc_restore_selfcalib()
755 * - BTW, bit clear triggers a read, then check data has been in stm32h7_adc_restore_selfcalib()
763 dev_err(&indio_dev->dev, "Failed to read calfact\n"); in stm32h7_adc_restore_selfcalib()
767 if (val != adc->cal.lincalfact[i] << STM32H7_LINCALFACT_SHIFT) { in stm32h7_adc_restore_selfcalib()
768 dev_err(&indio_dev->dev, "calfact not consistent\n"); in stm32h7_adc_restore_selfcalib()
769 return -EIO; in stm32h7_adc_restore_selfcalib()
781 * - low clock frequency
782 * - maximum prescalers
784 * - 131,072 ADC clock cycle for the linear calibration
785 * - 20 ADC clock cycle for the offset calibration
792 * stm32h7_adc_selfcalib() - Procedure to calibrate ADC (from power down)
808 * - Offset calibration for single ended inputs in stm32h7_adc_selfcalib()
809 * - No linearity calibration (do it later, before reading it) in stm32h7_adc_selfcalib()
820 dev_err(&indio_dev->dev, "calibration failed\n"); in stm32h7_adc_selfcalib()
826 * - Offset calibration for differential input in stm32h7_adc_selfcalib()
827 * - Linearity calibration (needs to be done only once for single/diff) in stm32h7_adc_selfcalib()
837 dev_err(&indio_dev->dev, "calibration failed\n"); in stm32h7_adc_selfcalib()
854 * stm32h7_adc_prepare() - Leave power down mode to enable ADC.
857 * Configure channels as single ended or differential before enabling ADC.
860 * Pre-select channels that may be used in PCSEL (required by input MUX / IO):
861 * - Only one input is selected for single ended (e.g. 'vinp')
862 * - Two inputs are selected for differential channels (e.g. 'vinp' & 'vinn')
872 stm32_adc_writel(adc, STM32H7_ADC_DIFSEL, adc->difsel); in stm32h7_adc_prepare()
882 stm32_adc_writel(adc, STM32H7_ADC_PCSEL, adc->pcsel); in stm32h7_adc_prepare()
901 * stm32_adc_conf_scan_seq() - Build regular channels scan sequence
903 * @scan_mask: channels to be converted
906 * Apply sampling time settings for all channels.
907 * Configure ADC scan sequence based on selected channels in scan_mask.
908 * Add channels to SQR registers, from scan_mask LSB to MSB, then
915 const struct stm32_adc_regs *sqr = adc->cfg->regs->sqr; in stm32_adc_conf_scan_seq()
921 stm32_adc_writel(adc, adc->cfg->regs->smpr[0], adc->smpr_val[0]); in stm32_adc_conf_scan_seq()
922 stm32_adc_writel(adc, adc->cfg->regs->smpr[1], adc->smpr_val[1]); in stm32_adc_conf_scan_seq()
924 for_each_set_bit(bit, scan_mask, indio_dev->masklength) { in stm32_adc_conf_scan_seq()
925 chan = indio_dev->channels + bit; in stm32_adc_conf_scan_seq()
932 return -EINVAL; in stm32_adc_conf_scan_seq()
934 dev_dbg(&indio_dev->dev, "%s chan %d to SQ%d\n", in stm32_adc_conf_scan_seq()
935 __func__, chan->channel, i); in stm32_adc_conf_scan_seq()
939 val |= chan->channel << sqr[i].shift; in stm32_adc_conf_scan_seq()
944 return -EINVAL; in stm32_adc_conf_scan_seq()
949 val |= ((i - 1) << sqr[0].shift); in stm32_adc_conf_scan_seq()
956 * stm32_adc_get_trig_extsel() - Get external trigger selection
959 * Returns trigger extsel value, if trig matches, -EINVAL otherwise.
968 for (i = 0; adc->cfg->trigs[i].name; i++) { in stm32_adc_get_trig_extsel()
975 !strcmp(adc->cfg->trigs[i].name, trig->name)) { in stm32_adc_get_trig_extsel()
976 return adc->cfg->trigs[i].extsel; in stm32_adc_get_trig_extsel()
980 return -EINVAL; in stm32_adc_get_trig_extsel()
984 * stm32_adc_set_trig() - Set a regular trigger
989 * - if HW trigger disabled (e.g. trig == NULL, conversion launched by sw)
990 * - if HW trigger enabled, set source & polarity
1007 exten = adc->trigger_polarity + STM32_EXTEN_HWTRIG_RISING_EDGE; in stm32_adc_set_trig()
1010 spin_lock_irqsave(&adc->lock, flags); in stm32_adc_set_trig()
1011 val = stm32_adc_readl(adc, adc->cfg->regs->exten.reg); in stm32_adc_set_trig()
1012 val &= ~(adc->cfg->regs->exten.mask | adc->cfg->regs->extsel.mask); in stm32_adc_set_trig()
1013 val |= exten << adc->cfg->regs->exten.shift; in stm32_adc_set_trig()
1014 val |= extsel << adc->cfg->regs->extsel.shift; in stm32_adc_set_trig()
1015 stm32_adc_writel(adc, adc->cfg->regs->exten.reg, val); in stm32_adc_set_trig()
1016 spin_unlock_irqrestore(&adc->lock, flags); in stm32_adc_set_trig()
1027 adc->trigger_polarity = type; in stm32_adc_set_trig_pol()
1037 return adc->trigger_polarity; in stm32_adc_get_trig_pol()
1041 "rising-edge", "falling-edge", "both-edges",
1052 * stm32_adc_single_conv() - Performs a single conversion
1058 * - Apply sampling time settings
1059 * - Program sequencer with one channel (e.g. in SQ1 with len = 1)
1060 * - Use SW trigger
1061 * - Start conversion, then wait for interrupt completion.
1068 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_single_conv()
1073 reinit_completion(&adc->completion); in stm32_adc_single_conv()
1075 adc->bufi = 0; in stm32_adc_single_conv()
1077 if (adc->cfg->prepare) { in stm32_adc_single_conv()
1078 ret = adc->cfg->prepare(adc); in stm32_adc_single_conv()
1084 stm32_adc_writel(adc, regs->smpr[0], adc->smpr_val[0]); in stm32_adc_single_conv()
1085 stm32_adc_writel(adc, regs->smpr[1], adc->smpr_val[1]); in stm32_adc_single_conv()
1088 val = stm32_adc_readl(adc, regs->sqr[1].reg); in stm32_adc_single_conv()
1089 val &= ~regs->sqr[1].mask; in stm32_adc_single_conv()
1090 val |= chan->channel << regs->sqr[1].shift; in stm32_adc_single_conv()
1091 stm32_adc_writel(adc, regs->sqr[1].reg, val); in stm32_adc_single_conv()
1094 stm32_adc_clr_bits(adc, regs->sqr[0].reg, regs->sqr[0].mask); in stm32_adc_single_conv()
1097 stm32_adc_clr_bits(adc, regs->exten.reg, regs->exten.mask); in stm32_adc_single_conv()
1101 adc->cfg->start_conv(adc, false); in stm32_adc_single_conv()
1104 &adc->completion, STM32_ADC_TIMEOUT); in stm32_adc_single_conv()
1106 ret = -ETIMEDOUT; in stm32_adc_single_conv()
1110 *res = adc->buffer[0]; in stm32_adc_single_conv()
1114 adc->cfg->stop_conv(adc); in stm32_adc_single_conv()
1118 if (adc->cfg->unprepare) in stm32_adc_single_conv()
1119 adc->cfg->unprepare(adc); in stm32_adc_single_conv()
1136 if (chan->type == IIO_VOLTAGE) in stm32_adc_read_raw()
1139 ret = -EINVAL; in stm32_adc_read_raw()
1144 if (chan->differential) { in stm32_adc_read_raw()
1145 *val = adc->common->vref_mv * 2; in stm32_adc_read_raw()
1146 *val2 = chan->scan_type.realbits; in stm32_adc_read_raw()
1148 *val = adc->common->vref_mv; in stm32_adc_read_raw()
1149 *val2 = chan->scan_type.realbits; in stm32_adc_read_raw()
1154 if (chan->differential) in stm32_adc_read_raw()
1156 *val = -((1 << chan->scan_type.realbits) / 2); in stm32_adc_read_raw()
1162 return -EINVAL; in stm32_adc_read_raw()
1170 const struct stm32_adc_regspec *regs = adc->cfg->regs; in stm32_adc_isr()
1171 u32 status = stm32_adc_readl(adc, regs->isr_eoc.reg); in stm32_adc_isr()
1173 if (status & regs->isr_eoc.mask) { in stm32_adc_isr()
1175 adc->buffer[adc->bufi] = stm32_adc_readw(adc, regs->dr); in stm32_adc_isr()
1177 adc->bufi++; in stm32_adc_isr()
1178 if (adc->bufi >= adc->num_conv) { in stm32_adc_isr()
1180 iio_trigger_poll(indio_dev->trig); in stm32_adc_isr()
1183 complete(&adc->completion); in stm32_adc_isr()
1192 * stm32_adc_validate_trigger() - validate trigger for stm32 adc
1197 * driver, -EINVAL otherwise.
1202 return stm32_adc_get_trig_extsel(indio_dev, trig) < 0 ? -EINVAL : 0; in stm32_adc_validate_trigger()
1214 * - always one buffer (period) dma is working on in stm32_adc_set_watermark()
1215 * - one buffer (period) driver can push with iio_trigger_poll(). in stm32_adc_set_watermark()
1218 adc->rx_buf_sz = min(rx_buf_sz, watermark * 2 * adc->num_conv); in stm32_adc_set_watermark()
1229 adc->num_conv = bitmap_weight(scan_mask, indio_dev->masklength); in stm32_adc_update_scan_mode()
1243 for (i = 0; i < indio_dev->num_channels; i++) in stm32_adc_of_xlate()
1244 if (indio_dev->channels[i].channel == iiospec->args[0]) in stm32_adc_of_xlate()
1247 return -EINVAL; in stm32_adc_of_xlate()
1251 * stm32_adc_debugfs_reg_access - read or write register value
1288 status = dmaengine_tx_status(adc->dma_chan, in stm32_adc_dma_residue()
1289 adc->dma_chan->cookie, in stm32_adc_dma_residue()
1293 unsigned int i = adc->rx_buf_sz - state.residue; in stm32_adc_dma_residue()
1297 if (i >= adc->bufi) in stm32_adc_dma_residue()
1298 size = i - adc->bufi; in stm32_adc_dma_residue()
1300 size = adc->rx_buf_sz + i - adc->bufi; in stm32_adc_dma_residue()
1323 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_dma_buffer_done()
1325 while (residue >= indio_dev->scan_bytes) { in stm32_adc_dma_buffer_done()
1326 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_dma_buffer_done()
1330 residue -= indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1331 adc->bufi += indio_dev->scan_bytes; in stm32_adc_dma_buffer_done()
1332 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_dma_buffer_done()
1333 adc->bufi = 0; in stm32_adc_dma_buffer_done()
1344 if (!adc->dma_chan) in stm32_adc_dma_start()
1347 dev_dbg(&indio_dev->dev, "%s size=%d watermark=%d\n", __func__, in stm32_adc_dma_start()
1348 adc->rx_buf_sz, adc->rx_buf_sz / 2); in stm32_adc_dma_start()
1351 desc = dmaengine_prep_dma_cyclic(adc->dma_chan, in stm32_adc_dma_start()
1352 adc->rx_dma_buf, in stm32_adc_dma_start()
1353 adc->rx_buf_sz, adc->rx_buf_sz / 2, in stm32_adc_dma_start()
1357 return -EBUSY; in stm32_adc_dma_start()
1359 desc->callback = stm32_adc_dma_buffer_done; in stm32_adc_dma_start()
1360 desc->callback_param = indio_dev; in stm32_adc_dma_start()
1365 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_dma_start()
1370 dma_async_issue_pending(adc->dma_chan); in stm32_adc_dma_start()
1380 if (adc->cfg->prepare) { in stm32_adc_buffer_postenable()
1381 ret = adc->cfg->prepare(adc); in stm32_adc_buffer_postenable()
1386 ret = stm32_adc_set_trig(indio_dev, indio_dev->trig); in stm32_adc_buffer_postenable()
1388 dev_err(&indio_dev->dev, "Can't set trigger\n"); in stm32_adc_buffer_postenable()
1394 dev_err(&indio_dev->dev, "Can't start dma\n"); in stm32_adc_buffer_postenable()
1403 adc->bufi = 0; in stm32_adc_buffer_postenable()
1405 if (!adc->dma_chan) in stm32_adc_buffer_postenable()
1408 adc->cfg->start_conv(adc, !!adc->dma_chan); in stm32_adc_buffer_postenable()
1413 if (adc->dma_chan) in stm32_adc_buffer_postenable()
1414 dmaengine_terminate_all(adc->dma_chan); in stm32_adc_buffer_postenable()
1418 if (adc->cfg->unprepare) in stm32_adc_buffer_postenable()
1419 adc->cfg->unprepare(adc); in stm32_adc_buffer_postenable()
1429 adc->cfg->stop_conv(adc); in stm32_adc_buffer_predisable()
1430 if (!adc->dma_chan) in stm32_adc_buffer_predisable()
1435 dev_err(&indio_dev->dev, "predisable failed\n"); in stm32_adc_buffer_predisable()
1437 if (adc->dma_chan) in stm32_adc_buffer_predisable()
1438 dmaengine_terminate_sync(adc->dma_chan); in stm32_adc_buffer_predisable()
1441 dev_err(&indio_dev->dev, "Can't clear trigger\n"); in stm32_adc_buffer_predisable()
1443 if (adc->cfg->unprepare) in stm32_adc_buffer_predisable()
1444 adc->cfg->unprepare(adc); in stm32_adc_buffer_predisable()
1457 struct iio_dev *indio_dev = pf->indio_dev; in stm32_adc_trigger_handler()
1460 dev_dbg(&indio_dev->dev, "%s bufi=%d\n", __func__, adc->bufi); in stm32_adc_trigger_handler()
1462 if (!adc->dma_chan) { in stm32_adc_trigger_handler()
1464 adc->bufi = 0; in stm32_adc_trigger_handler()
1465 iio_push_to_buffers_with_timestamp(indio_dev, adc->buffer, in stm32_adc_trigger_handler()
1466 pf->timestamp); in stm32_adc_trigger_handler()
1470 while (residue >= indio_dev->scan_bytes) { in stm32_adc_trigger_handler()
1471 u16 *buffer = (u16 *)&adc->rx_buf[adc->bufi]; in stm32_adc_trigger_handler()
1474 pf->timestamp); in stm32_adc_trigger_handler()
1475 residue -= indio_dev->scan_bytes; in stm32_adc_trigger_handler()
1476 adc->bufi += indio_dev->scan_bytes; in stm32_adc_trigger_handler()
1477 if (adc->bufi >= adc->rx_buf_sz) in stm32_adc_trigger_handler()
1478 adc->bufi = 0; in stm32_adc_trigger_handler()
1482 iio_trigger_notify_done(indio_dev->trig); in stm32_adc_trigger_handler()
1484 /* re-enable eoc irq */ in stm32_adc_trigger_handler()
1485 if (!adc->dma_chan) in stm32_adc_trigger_handler()
1504 struct device_node *node = indio_dev->dev.of_node; in stm32_adc_of_get_resolution()
1509 if (of_property_read_u32(node, "assigned-resolution-bits", &res)) in stm32_adc_of_get_resolution()
1510 res = adc->cfg->adc_info->resolutions[0]; in stm32_adc_of_get_resolution()
1512 for (i = 0; i < adc->cfg->adc_info->num_res; i++) in stm32_adc_of_get_resolution()
1513 if (res == adc->cfg->adc_info->resolutions[i]) in stm32_adc_of_get_resolution()
1515 if (i >= adc->cfg->adc_info->num_res) { in stm32_adc_of_get_resolution()
1516 dev_err(&indio_dev->dev, "Bad resolution: %u bits\n", res); in stm32_adc_of_get_resolution()
1517 return -EINVAL; in stm32_adc_of_get_resolution()
1520 dev_dbg(&indio_dev->dev, "Using %u bits resolution\n", res); in stm32_adc_of_get_resolution()
1521 adc->res = i; in stm32_adc_of_get_resolution()
1528 const struct stm32_adc_regs *smpr = &adc->cfg->regs->smp_bits[channel]; in stm32_adc_smpr_init()
1529 u32 period_ns, shift = smpr->shift, mask = smpr->mask; in stm32_adc_smpr_init()
1530 unsigned int smp, r = smpr->reg; in stm32_adc_smpr_init()
1533 period_ns = NSEC_PER_SEC / adc->common->rate; in stm32_adc_smpr_init()
1535 if ((period_ns * adc->cfg->smp_cycles[smp]) >= smp_ns) in stm32_adc_smpr_init()
1540 /* pre-build sampling time registers (e.g. smpr1, smpr2) */ in stm32_adc_smpr_init()
1541 adc->smpr_val[r] = (adc->smpr_val[r] & ~mask) | (smp << shift); in stm32_adc_smpr_init()
1549 char *name = adc->chan_name[vinp]; in stm32_adc_chan_init_one()
1551 chan->type = IIO_VOLTAGE; in stm32_adc_chan_init_one()
1552 chan->channel = vinp; in stm32_adc_chan_init_one()
1554 chan->differential = 1; in stm32_adc_chan_init_one()
1555 chan->channel2 = vinn; in stm32_adc_chan_init_one()
1556 snprintf(name, STM32_ADC_CH_SZ, "in%d-in%d", vinp, vinn); in stm32_adc_chan_init_one()
1560 chan->datasheet_name = name; in stm32_adc_chan_init_one()
1561 chan->scan_index = scan_index; in stm32_adc_chan_init_one()
1562 chan->indexed = 1; in stm32_adc_chan_init_one()
1563 chan->info_mask_separate = BIT(IIO_CHAN_INFO_RAW); in stm32_adc_chan_init_one()
1564 chan->info_mask_shared_by_type = BIT(IIO_CHAN_INFO_SCALE) | in stm32_adc_chan_init_one()
1566 chan->scan_type.sign = 'u'; in stm32_adc_chan_init_one()
1567 chan->scan_type.realbits = adc->cfg->adc_info->resolutions[adc->res]; in stm32_adc_chan_init_one()
1568 chan->scan_type.storagebits = 16; in stm32_adc_chan_init_one()
1569 chan->ext_info = stm32_adc_ext_info; in stm32_adc_chan_init_one()
1571 /* pre-build selected channels mask */ in stm32_adc_chan_init_one()
1572 adc->pcsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1574 /* pre-build diff channels mask */ in stm32_adc_chan_init_one()
1575 adc->difsel |= BIT(chan->channel); in stm32_adc_chan_init_one()
1576 /* Also add negative input to pre-selected channels */ in stm32_adc_chan_init_one()
1577 adc->pcsel |= BIT(chan->channel2); in stm32_adc_chan_init_one()
1583 struct device_node *node = indio_dev->dev.of_node; in stm32_adc_chan_of_init()
1585 const struct stm32_adc_info *adc_info = adc->cfg->adc_info; in stm32_adc_chan_of_init()
1586 struct stm32_adc_diff_channel diff[STM32_ADC_CH_MAX]; in stm32_adc_chan_of_init() local
1589 struct iio_chan_spec *channels; in stm32_adc_chan_of_init() local
1593 ret = of_property_count_u32_elems(node, "st,adc-channels"); in stm32_adc_chan_of_init()
1594 if (ret > adc_info->max_channels) { in stm32_adc_chan_of_init()
1595 dev_err(&indio_dev->dev, "Bad st,adc-channels?\n"); in stm32_adc_chan_of_init()
1596 return -EINVAL; in stm32_adc_chan_of_init()
1601 ret = of_property_count_elems_of_size(node, "st,adc-diff-channels", in stm32_adc_chan_of_init()
1602 sizeof(*diff)); in stm32_adc_chan_of_init()
1603 if (ret > adc_info->max_channels) { in stm32_adc_chan_of_init()
1604 dev_err(&indio_dev->dev, "Bad st,adc-diff-channels?\n"); in stm32_adc_chan_of_init()
1605 return -EINVAL; in stm32_adc_chan_of_init()
1607 int size = ret * sizeof(*diff) / sizeof(u32); in stm32_adc_chan_of_init()
1611 ret = of_property_read_u32_array(node, "st,adc-diff-channels", in stm32_adc_chan_of_init()
1612 (u32 *)diff, size); in stm32_adc_chan_of_init()
1618 dev_err(&indio_dev->dev, "No channels configured\n"); in stm32_adc_chan_of_init()
1619 return -ENODATA; in stm32_adc_chan_of_init()
1622 /* Optional sample time is provided either for each, or all channels */ in stm32_adc_chan_of_init()
1623 ret = of_property_count_u32_elems(node, "st,min-sample-time-nsecs"); in stm32_adc_chan_of_init()
1625 dev_err(&indio_dev->dev, "Invalid st,min-sample-time-nsecs\n"); in stm32_adc_chan_of_init()
1626 return -EINVAL; in stm32_adc_chan_of_init()
1629 channels = devm_kcalloc(&indio_dev->dev, num_channels, in stm32_adc_chan_of_init()
1631 if (!channels) in stm32_adc_chan_of_init()
1632 return -ENOMEM; in stm32_adc_chan_of_init()
1634 of_property_for_each_u32(node, "st,adc-channels", prop, cur, val) { in stm32_adc_chan_of_init()
1635 if (val >= adc_info->max_channels) { in stm32_adc_chan_of_init()
1636 dev_err(&indio_dev->dev, "Invalid channel %d\n", val); in stm32_adc_chan_of_init()
1637 return -EINVAL; in stm32_adc_chan_of_init()
1640 /* Channel can't be configured both as single-ended & diff */ in stm32_adc_chan_of_init()
1642 if (val == diff[i].vinp) { in stm32_adc_chan_of_init()
1643 dev_err(&indio_dev->dev, in stm32_adc_chan_of_init()
1644 "channel %d miss-configured\n", val); in stm32_adc_chan_of_init()
1645 return -EINVAL; in stm32_adc_chan_of_init()
1648 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], val, in stm32_adc_chan_of_init()
1654 if (diff[i].vinp >= adc_info->max_channels || in stm32_adc_chan_of_init()
1655 diff[i].vinn >= adc_info->max_channels) { in stm32_adc_chan_of_init()
1656 dev_err(&indio_dev->dev, "Invalid channel in%d-in%d\n", in stm32_adc_chan_of_init()
1657 diff[i].vinp, diff[i].vinn); in stm32_adc_chan_of_init()
1658 return -EINVAL; in stm32_adc_chan_of_init()
1660 stm32_adc_chan_init_one(indio_dev, &channels[scan_index], in stm32_adc_chan_of_init()
1661 diff[i].vinp, diff[i].vinn, scan_index, in stm32_adc_chan_of_init()
1673 of_property_read_u32_index(node, "st,min-sample-time-nsecs", in stm32_adc_chan_of_init()
1676 stm32_adc_smpr_init(adc, channels[i].channel, smp); in stm32_adc_chan_of_init()
1679 indio_dev->num_channels = scan_index; in stm32_adc_chan_of_init()
1680 indio_dev->channels = channels; in stm32_adc_chan_of_init()
1691 adc->dma_chan = dma_request_chan(dev, "rx"); in stm32_adc_dma_request()
1692 if (IS_ERR(adc->dma_chan)) { in stm32_adc_dma_request()
1693 ret = PTR_ERR(adc->dma_chan); in stm32_adc_dma_request()
1694 if (ret != -ENODEV) { in stm32_adc_dma_request()
1695 if (ret != -EPROBE_DEFER) in stm32_adc_dma_request()
1703 adc->dma_chan = NULL; in stm32_adc_dma_request()
1707 adc->rx_buf = dma_alloc_coherent(adc->dma_chan->device->dev, in stm32_adc_dma_request()
1709 &adc->rx_dma_buf, GFP_KERNEL); in stm32_adc_dma_request()
1710 if (!adc->rx_buf) { in stm32_adc_dma_request()
1711 ret = -ENOMEM; in stm32_adc_dma_request()
1717 config.src_addr = (dma_addr_t)adc->common->phys_base; in stm32_adc_dma_request()
1718 config.src_addr += adc->offset + adc->cfg->regs->dr; in stm32_adc_dma_request()
1721 ret = dmaengine_slave_config(adc->dma_chan, &config); in stm32_adc_dma_request()
1728 dma_free_coherent(adc->dma_chan->device->dev, STM32_DMA_BUFFER_SIZE, in stm32_adc_dma_request()
1729 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_dma_request()
1731 dma_release_channel(adc->dma_chan); in stm32_adc_dma_request()
1739 struct device *dev = &pdev->dev; in stm32_adc_probe()
1744 if (!pdev->dev.of_node) in stm32_adc_probe()
1745 return -ENODEV; in stm32_adc_probe()
1747 indio_dev = devm_iio_device_alloc(&pdev->dev, sizeof(*adc)); in stm32_adc_probe()
1749 return -ENOMEM; in stm32_adc_probe()
1752 adc->common = dev_get_drvdata(pdev->dev.parent); in stm32_adc_probe()
1753 spin_lock_init(&adc->lock); in stm32_adc_probe()
1754 init_completion(&adc->completion); in stm32_adc_probe()
1755 adc->cfg = (const struct stm32_adc_cfg *) in stm32_adc_probe()
1756 of_match_device(dev->driver->of_match_table, dev)->data; in stm32_adc_probe()
1758 indio_dev->name = dev_name(&pdev->dev); in stm32_adc_probe()
1759 indio_dev->dev.parent = &pdev->dev; in stm32_adc_probe()
1760 indio_dev->dev.of_node = pdev->dev.of_node; in stm32_adc_probe()
1761 indio_dev->info = &stm32_adc_iio_info; in stm32_adc_probe()
1762 indio_dev->modes = INDIO_DIRECT_MODE | INDIO_HARDWARE_TRIGGERED; in stm32_adc_probe()
1766 ret = of_property_read_u32(pdev->dev.of_node, "reg", &adc->offset); in stm32_adc_probe()
1768 dev_err(&pdev->dev, "missing reg property\n"); in stm32_adc_probe()
1769 return -EINVAL; in stm32_adc_probe()
1772 adc->irq = platform_get_irq(pdev, 0); in stm32_adc_probe()
1773 if (adc->irq < 0) { in stm32_adc_probe()
1774 dev_err(&pdev->dev, "failed to get irq\n"); in stm32_adc_probe()
1775 return adc->irq; in stm32_adc_probe()
1778 ret = devm_request_irq(&pdev->dev, adc->irq, stm32_adc_isr, in stm32_adc_probe()
1779 0, pdev->name, adc); in stm32_adc_probe()
1781 dev_err(&pdev->dev, "failed to request IRQ\n"); in stm32_adc_probe()
1785 adc->clk = devm_clk_get(&pdev->dev, NULL); in stm32_adc_probe()
1786 if (IS_ERR(adc->clk)) { in stm32_adc_probe()
1787 ret = PTR_ERR(adc->clk); in stm32_adc_probe()
1788 if (ret == -ENOENT && !adc->cfg->clk_required) { in stm32_adc_probe()
1789 adc->clk = NULL; in stm32_adc_probe()
1791 dev_err(&pdev->dev, "Can't get clock\n"); in stm32_adc_probe()
1796 if (adc->clk) { in stm32_adc_probe()
1797 ret = clk_prepare_enable(adc->clk); in stm32_adc_probe()
1799 dev_err(&pdev->dev, "clk enable failed\n"); in stm32_adc_probe()
1809 if (adc->cfg->selfcalib) { in stm32_adc_probe()
1810 ret = adc->cfg->selfcalib(adc); in stm32_adc_probe()
1823 if (!adc->dma_chan) in stm32_adc_probe()
1830 dev_err(&pdev->dev, "buffer setup failed\n"); in stm32_adc_probe()
1836 dev_err(&pdev->dev, "iio dev register failed\n"); in stm32_adc_probe()
1846 if (adc->dma_chan) { in stm32_adc_probe()
1847 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_probe()
1849 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_probe()
1850 dma_release_channel(adc->dma_chan); in stm32_adc_probe()
1853 if (adc->clk) in stm32_adc_probe()
1854 clk_disable_unprepare(adc->clk); in stm32_adc_probe()
1866 if (adc->dma_chan) { in stm32_adc_remove()
1867 dma_free_coherent(adc->dma_chan->device->dev, in stm32_adc_remove()
1869 adc->rx_buf, adc->rx_dma_buf); in stm32_adc_remove()
1870 dma_release_channel(adc->dma_chan); in stm32_adc_remove()
1872 if (adc->clk) in stm32_adc_remove()
1873 clk_disable_unprepare(adc->clk); in stm32_adc_remove()
1914 { .compatible = "st,stm32f4-adc", .data = (void *)&stm32f4_adc_cfg },
1915 { .compatible = "st,stm32h7-adc", .data = (void *)&stm32h7_adc_cfg },
1916 { .compatible = "st,stm32mp1-adc", .data = (void *)&stm32mp1_adc_cfg },
1925 .name = "stm32-adc",
1934 MODULE_ALIAS("platform:stm32-adc");