Lines Matching +full:stm32 +full:- +full:timer +full:- +full:trigger
1 // SPDX-License-Identifier: GPL-2.0
11 #include <linux/iio/timer/stm32-timer-trigger.h>
12 #include <linux/iio/trigger.h>
13 #include <linux/mfd/stm32-timers.h>
21 /* List the triggers created by each timer */
42 /* List the triggers accepted by each timer */
49 { }, /* timer 6 */
50 { }, /* timer 7 */
53 { }, /* timer 10 */
54 { }, /* timer 11 */
64 { }, /* timer 6 */
65 { }, /* timer 7 */
67 { }, /* timer 9 */
68 { }, /* timer 10 */
69 { }, /* timer 11 */
71 { }, /* timer 13 */
72 { }, /* timer 14 */
74 { }, /* timer 16 */
75 { }, /* timer 17 */
112 div = (unsigned long long)clk_get_rate(priv->clk); in stm32_timer_start()
122 while (div > priv->max_arr) { in stm32_timer_start()
130 dev_err(priv->dev, "prescaler exceeds the maximum value\n"); in stm32_timer_start()
131 return -EINVAL; in stm32_timer_start()
134 /* Check if nobody else use the timer */ in stm32_timer_start()
135 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_timer_start()
137 return -EBUSY; in stm32_timer_start()
139 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_timer_start()
141 clk_enable(priv->clk); in stm32_timer_start()
143 regmap_write(priv->regmap, TIM_PSC, prescaler); in stm32_timer_start()
144 regmap_write(priv->regmap, TIM_ARR, prd - 1); in stm32_timer_start()
145 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, TIM_CR1_ARPE); in stm32_timer_start()
148 if (stm32_timer_is_trgo2_name(trig->name)) in stm32_timer_start()
149 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, in stm32_timer_start()
152 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, in stm32_timer_start()
156 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); in stm32_timer_start()
159 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, TIM_CR1_CEN); in stm32_timer_start()
169 regmap_read(priv->regmap, TIM_CCER, &ccer); in stm32_timer_stop()
173 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_timer_stop()
175 clk_disable(priv->clk); in stm32_timer_stop()
177 /* Stop timer */ in stm32_timer_stop()
178 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); in stm32_timer_stop()
179 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, 0); in stm32_timer_stop()
180 regmap_write(priv->regmap, TIM_PSC, 0); in stm32_timer_stop()
181 regmap_write(priv->regmap, TIM_ARR, 0); in stm32_timer_stop()
184 if (stm32_timer_is_trgo2_name(trig->name)) in stm32_timer_stop()
185 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); in stm32_timer_stop()
187 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS, 0); in stm32_timer_stop()
190 regmap_update_bits(priv->regmap, TIM_EGR, TIM_EGR_UG, TIM_EGR_UG); in stm32_timer_stop()
225 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_tt_read_frequency()
226 regmap_read(priv->regmap, TIM_PSC, &psc); in stm32_tt_read_frequency()
227 regmap_read(priv->regmap, TIM_ARR, &arr); in stm32_tt_read_frequency()
230 freq = (unsigned long long)clk_get_rate(priv->clk); in stm32_tt_read_frequency()
273 regmap_read(priv->regmap, TIM_CR2, &cr2); in stm32_tt_show_master_mode()
275 if (stm32_timer_is_trgo2_name(trig->name)) in stm32_tt_show_master_mode()
292 if (stm32_timer_is_trgo2_name(trig->name)) { in stm32_tt_store_master_mode()
305 regmap_update_bits(priv->regmap, TIM_CR2, mask, in stm32_tt_store_master_mode()
308 regmap_update_bits(priv->regmap, TIM_EGR, in stm32_tt_store_master_mode()
314 return -EINVAL; in stm32_tt_store_master_mode()
325 if (stm32_timer_is_trgo2_name(trig->name)) in stm32_tt_show_master_mode_avail()
331 len += scnprintf(buf + len, PAGE_SIZE - len, in stm32_tt_show_master_mode_avail()
335 buf[len - 1] = '\n'; in stm32_tt_show_master_mode_avail()
370 const char * const *cur = priv->triggers; in stm32_setup_iio_triggers()
377 if (cur_is_trgo2 && !priv->has_trgo2) { in stm32_setup_iio_triggers()
382 trig = devm_iio_trigger_alloc(priv->dev, "%s", *cur); in stm32_setup_iio_triggers()
384 return -ENOMEM; in stm32_setup_iio_triggers()
386 trig->dev.parent = priv->dev->parent; in stm32_setup_iio_triggers()
387 trig->ops = &timer_trigger_ops; in stm32_setup_iio_triggers()
394 trig->dev.groups = stm32_trigger_attr_groups; in stm32_setup_iio_triggers()
398 ret = devm_iio_trigger_register(priv->dev, trig); in stm32_setup_iio_triggers()
416 regmap_read(priv->regmap, TIM_CNT, &dat); in stm32_counter_read_raw()
421 regmap_read(priv->regmap, TIM_CR1, &dat); in stm32_counter_read_raw()
426 regmap_read(priv->regmap, TIM_SMCR, &dat); in stm32_counter_read_raw()
439 return -EINVAL; in stm32_counter_read_raw()
451 return regmap_write(priv->regmap, TIM_CNT, val); in stm32_counter_write_raw()
455 return -EINVAL; in stm32_counter_write_raw()
459 regmap_read(priv->regmap, TIM_CR1, &dat); in stm32_counter_write_raw()
461 clk_enable(priv->clk); in stm32_counter_write_raw()
462 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, in stm32_counter_write_raw()
465 regmap_read(priv->regmap, TIM_CR1, &dat); in stm32_counter_write_raw()
466 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_CEN, in stm32_counter_write_raw()
469 clk_disable(priv->clk); in stm32_counter_write_raw()
474 return -EINVAL; in stm32_counter_write_raw()
481 const char * const *cur = priv->valids; in stm32_counter_validate_trigger()
485 return -EINVAL; in stm32_counter_validate_trigger()
488 if (!strncmp(trig->name, *cur, strlen(trig->name))) { in stm32_counter_validate_trigger()
489 regmap_update_bits(priv->regmap, in stm32_counter_validate_trigger()
498 return -EINVAL; in stm32_counter_validate_trigger()
508 "trigger",
517 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, TIM_SMCR_SMS); in stm32_set_trigger_mode()
528 regmap_read(priv->regmap, TIM_SMCR, &smcr); in stm32_get_trigger_mode()
530 return (smcr & TIM_SMCR_SMS) == TIM_SMCR_SMS ? 0 : -EINVAL; in stm32_get_trigger_mode()
557 return -EINVAL; in stm32_enable_mode2sms()
575 regmap_read(priv->regmap, TIM_CR1, &val); in stm32_set_enable_mode()
577 clk_enable(priv->clk); in stm32_set_enable_mode()
580 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, sms); in stm32_set_enable_mode()
596 return -EINVAL; in stm32_sms2enable_mode()
605 regmap_read(priv->regmap, TIM_SMCR, &smcr); in stm32_get_enable_mode()
630 regmap_update_bits(priv->regmap, TIM_SMCR, TIM_SMCR_SMS, mode + 1); in stm32_set_quadrature_mode()
642 regmap_read(priv->regmap, TIM_SMCR, &smcr); in stm32_get_quadrature_mode()
643 mode = (smcr & TIM_SMCR_SMS) - 1; in stm32_get_quadrature_mode()
645 return -EINVAL; in stm32_get_quadrature_mode()
671 regmap_read(priv->regmap, TIM_SMCR, &val); in stm32_set_count_direction()
672 mode = (val & TIM_SMCR_SMS) - 1; in stm32_set_count_direction()
674 return -EBUSY; in stm32_set_count_direction()
676 return regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_DIR, in stm32_set_count_direction()
686 regmap_read(priv->regmap, TIM_CR1, &cr1); in stm32_get_count_direction()
706 regmap_read(priv->regmap, TIM_ARR, &arr); in stm32_count_get_preset()
725 regmap_update_bits(priv->regmap, TIM_CR1, TIM_CR1_ARPE, 0); in stm32_count_set_preset()
726 regmap_write(priv->regmap, TIM_ARR, preset); in stm32_count_set_preset()
769 indio_dev->name = dev_name(dev); in stm32_setup_counter_device()
770 indio_dev->dev.parent = dev; in stm32_setup_counter_device()
771 indio_dev->info = &stm32_trigger_info; in stm32_setup_counter_device()
772 indio_dev->modes = INDIO_HARDWARE_TRIGGERED; in stm32_setup_counter_device()
773 indio_dev->num_channels = 1; in stm32_setup_counter_device()
774 indio_dev->channels = &stm32_trigger_channel; in stm32_setup_counter_device()
775 indio_dev->dev.of_node = dev->of_node; in stm32_setup_counter_device()
786 * @trig: trigger to be checked
788 * return true if the trigger is a valid stm32 iio timer trigger
793 return (trig->ops == &timer_trigger_ops); in is_stm32_timer_trigger()
803 * timer supports it. in stm32_timer_detect_trgo2()
805 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, TIM_CR2_MMS2); in stm32_timer_detect_trgo2()
806 regmap_read(priv->regmap, TIM_CR2, &val); in stm32_timer_detect_trgo2()
807 regmap_update_bits(priv->regmap, TIM_CR2, TIM_CR2_MMS2, 0); in stm32_timer_detect_trgo2()
808 priv->has_trgo2 = !!val; in stm32_timer_detect_trgo2()
813 struct device *dev = &pdev->dev; in stm32_timer_trigger_probe()
815 struct stm32_timers *ddata = dev_get_drvdata(pdev->dev.parent); in stm32_timer_trigger_probe()
820 if (of_property_read_u32(dev->of_node, "reg", &index)) in stm32_timer_trigger_probe()
821 return -EINVAL; in stm32_timer_trigger_probe()
824 of_match_device(dev->driver->of_match_table, dev)->data; in stm32_timer_trigger_probe()
827 index >= cfg->num_valids_table) in stm32_timer_trigger_probe()
828 return -EINVAL; in stm32_timer_trigger_probe()
831 if (*cfg->valids_table[index]) in stm32_timer_trigger_probe()
837 return -ENOMEM; in stm32_timer_trigger_probe()
839 priv->dev = dev; in stm32_timer_trigger_probe()
840 priv->regmap = ddata->regmap; in stm32_timer_trigger_probe()
841 priv->clk = ddata->clk; in stm32_timer_trigger_probe()
842 priv->max_arr = ddata->max_arr; in stm32_timer_trigger_probe()
843 priv->triggers = triggers_table[index]; in stm32_timer_trigger_probe()
844 priv->valids = cfg->valids_table[index]; in stm32_timer_trigger_probe()
868 .compatible = "st,stm32-timer-trigger",
871 .compatible = "st,stm32h7-timer-trigger",
881 .name = "stm32-timer-trigger",
887 MODULE_ALIAS("platform: stm32-timer-trigger");
888 MODULE_DESCRIPTION("STMicroelectronics STM32 Timer Trigger driver");