Lines Matching +full:0 +full:x0bf8
34 #define PAMU_PGC 0x00000000 /* Allows all peripheral accesses */
35 #define PAMU_PE 0x40000000 /* enable PAMU */
38 #define PAMU_OFFSET 0x1000
40 #define PAMU_MMAP_REGS_BASE 0
58 #define PAMU_POES1 0x0040
59 #define PAMU_POES2 0x0044
60 #define PAMU_POEAH 0x0048
61 #define PAMU_POEAL 0x004C
62 #define PAMU_AVS1 0x0050
63 #define PAMU_AVS1_AV 0x1
64 #define PAMU_AVS1_OTV 0x6
65 #define PAMU_AVS1_APV 0x78
66 #define PAMU_AVS1_WAV 0x380
67 #define PAMU_AVS1_LAV 0x1c00
68 #define PAMU_AVS1_GCV 0x2000
69 #define PAMU_AVS1_PDV 0x4000
73 #define PAMU_LAV_LIODN_NOT_IN_PPAACT 0x400
75 #define PAMU_AVS2 0x0054
76 #define PAMU_AVAH 0x0058
77 #define PAMU_AVAL 0x005C
78 #define PAMU_EECTL 0x0060
79 #define PAMU_EEDIS 0x0064
80 #define PAMU_EEINTEN 0x0068
81 #define PAMU_EEDET 0x006C
82 #define PAMU_EEATTR 0x0070
83 #define PAMU_EEAHI 0x0074
84 #define PAMU_EEALO 0x0078
85 #define PAMU_EEDHI 0X007C
86 #define PAMU_EEDLO 0x0080
87 #define PAMU_EECC 0x0084
88 #define PAMU_UDAD 0x0090
91 #define PAMU_PR1 0x0BF8
92 #define PAMU_PR2 0x0BFC
95 #define PAMU_PR1_MASK 0xffff
98 #define PAMU_PC1 0x0C00
99 #define PAMU_PC2 0x0C04
100 #define PAMU_PC3 0x0C08
101 #define PAMU_PC4 0x0C0C
104 #define PAMU_PC 0x0C10
107 #define PAMU_CONTROL 0x0C10
108 #define PAMU_PC_PGC 0x80000000 /* PAMU gate closed bit */
109 #define PAMU_PC_PE 0x40000000 /* PAMU enable bit */
110 #define PAMU_PC_SPCC 0x00000010 /* sPAACE cache enable */
111 #define PAMU_PC_PPCC 0x00000001 /* pPAACE cache enable */
112 #define PAMU_PC_OCE 0x00001000 /* OMT cache enable */
114 #define PAMU_PFA1 0x0C14
115 #define PAMU_PFA2 0x0C18
118 #define PAMU_PC3_MWCE(X) (((X) >> 21) & 0xf)
121 #define PAMU_PICS 0x0C1C
122 #define PAMU_ACCESS_VIOLATION_STAT 0x8
123 #define PAMU_ACCESS_VIOLATION_ENABLE 0x4
126 #define PAMU_PD1 0x0F00
127 #define PAMU_PD2 0x0F04
128 #define PAMU_PD3 0x0F08
129 #define PAMU_PD4 0x0F0C
131 #define PAACE_AP_PERMS_DENIED 0x0
132 #define PAACE_AP_PERMS_QUERY 0x1
133 #define PAACE_AP_PERMS_UPDATE 0x2
134 #define PAACE_AP_PERMS_ALL 0x3
136 #define PAACE_DD_TO_HOST 0x0
137 #define PAACE_DD_TO_IO 0x1
138 #define PAACE_PT_PRIMARY 0x0
139 #define PAACE_PT_SECONDARY 0x1
140 #define PAACE_V_INVALID 0x0
141 #define PAACE_V_VALID 0x1
142 #define PAACE_MW_SUBWINDOWS 0x1
144 #define PAACE_WSE_4K 0xB
145 #define PAACE_WSE_8K 0xC
146 #define PAACE_WSE_16K 0xD
147 #define PAACE_WSE_32K 0xE
148 #define PAACE_WSE_64K 0xF
149 #define PAACE_WSE_128K 0x10
150 #define PAACE_WSE_256K 0x11
151 #define PAACE_WSE_512K 0x12
152 #define PAACE_WSE_1M 0x13
153 #define PAACE_WSE_2M 0x14
154 #define PAACE_WSE_4M 0x15
155 #define PAACE_WSE_8M 0x16
156 #define PAACE_WSE_16M 0x17
157 #define PAACE_WSE_32M 0x18
158 #define PAACE_WSE_64M 0x19
159 #define PAACE_WSE_128M 0x1A
160 #define PAACE_WSE_256M 0x1B
161 #define PAACE_WSE_512M 0x1C
162 #define PAACE_WSE_1G 0x1D
163 #define PAACE_WSE_2G 0x1E
164 #define PAACE_WSE_4G 0x1F
166 #define PAACE_DID_PCI_EXPRESS_1 0x00
167 #define PAACE_DID_PCI_EXPRESS_2 0x01
168 #define PAACE_DID_PCI_EXPRESS_3 0x02
169 #define PAACE_DID_PCI_EXPRESS_4 0x03
170 #define PAACE_DID_LOCAL_BUS 0x04
171 #define PAACE_DID_SRIO 0x0C
172 #define PAACE_DID_MEM_1 0x10
173 #define PAACE_DID_MEM_2 0x11
174 #define PAACE_DID_MEM_3 0x12
175 #define PAACE_DID_MEM_4 0x13
176 #define PAACE_DID_MEM_1_2 0x14
177 #define PAACE_DID_MEM_3_4 0x15
178 #define PAACE_DID_MEM_1_4 0x16
179 #define PAACE_DID_BM_SW_PORTAL 0x18
180 #define PAACE_DID_PAMU 0x1C
181 #define PAACE_DID_CAAM 0x21
182 #define PAACE_DID_QM_SW_PORTAL 0x3C
183 #define PAACE_DID_CORE0_INST 0x80
184 #define PAACE_DID_CORE0_DATA 0x81
185 #define PAACE_DID_CORE1_INST 0x82
186 #define PAACE_DID_CORE1_DATA 0x83
187 #define PAACE_DID_CORE2_INST 0x84
188 #define PAACE_DID_CORE2_DATA 0x85
189 #define PAACE_DID_CORE3_INST 0x86
190 #define PAACE_DID_CORE3_DATA 0x87
191 #define PAACE_DID_CORE4_INST 0x88
192 #define PAACE_DID_CORE4_DATA 0x89
193 #define PAACE_DID_CORE5_INST 0x8A
194 #define PAACE_DID_CORE5_DATA 0x8B
195 #define PAACE_DID_CORE6_INST 0x8C
196 #define PAACE_DID_CORE6_DATA 0x8D
197 #define PAACE_DID_CORE7_INST 0x8E
198 #define PAACE_DID_CORE7_DATA 0x8F
199 #define PAACE_DID_BROADCAST 0xFF
201 #define PAACE_ATM_NO_XLATE 0x00
202 #define PAACE_ATM_WINDOW_XLATE 0x01
203 #define PAACE_ATM_PAGE_XLATE 0x02
205 #define PAACE_OTM_NO_XLATE 0x00
206 #define PAACE_OTM_IMMEDIATE 0x01
207 #define PAACE_OTM_INDEXED 0x02
208 #define PAACE_OTM_RESERVED 0x03
210 #define PAACE_M_COHERENCE_REQ 0x01
212 #define PAACE_PID_0 0x0
213 #define PAACE_PID_1 0x1
214 #define PAACE_PID_2 0x2
215 #define PAACE_PID_3 0x3
216 #define PAACE_PID_4 0x4
217 #define PAACE_PID_5 0x5
218 #define PAACE_PID_6 0x6
219 #define PAACE_PID_7 0x7
221 #define PAACE_TCEF_FORMAT0_8B 0x00
222 #define PAACE_TCEF_FORMAT1_RSVD 0x01
227 #define PAACE_NUMBER_ENTRIES 0x500
229 #define SPAACE_NUMBER_ENTRIES 0x800
234 #define PPAACE_AF_WBAL 0xfffff000
236 #define PPAACE_AF_WSE 0x00000fc0
238 #define PPAACE_AF_MW 0x00000020
241 #define SPAACE_AF_LIODN 0xffff0000
244 #define PAACE_AF_AP 0x00000018
246 #define PAACE_AF_DD 0x00000004
248 #define PAACE_AF_PT 0x00000002
250 #define PAACE_AF_V 0x00000001
251 #define PAACE_AF_V_SHIFT 0
253 #define PAACE_DA_HOST_CR 0x80
256 #define PAACE_IA_CID 0x00FF0000
258 #define PAACE_IA_WCE 0x000000F0
260 #define PAACE_IA_ATM 0x0000000C
262 #define PAACE_IA_OTM 0x00000003
263 #define PAACE_IA_OTM_SHIFT 0
265 #define PAACE_WIN_TWBAL 0xfffff000
267 #define PAACE_WIN_SWSE 0x00000fc0
273 /* PAACE Offset 0x00 */
277 /* PAACE Offset 0x08 */
301 /* PAACE Offset 0x10 */
306 /* PAACE Offset 0x18 */
322 /* PAACE Offsets 0x20-0x38 */
346 #define IOE_READ 0x00
347 #define IOE_READ_IDX 0x00
348 #define IOE_WRITE 0x81
349 #define IOE_WRITE_IDX 0x01
350 #define IOE_EREAD0 0x82 /* Enhanced read type 0 */
351 #define IOE_EREAD0_IDX 0x02 /* Enhanced read type 0 */
352 #define IOE_EWRITE0 0x83 /* Enhanced write type 0 */
353 #define IOE_EWRITE0_IDX 0x03 /* Enhanced write type 0 */
354 #define IOE_DIRECT0 0x84 /* Directive type 0 */
355 #define IOE_DIRECT0_IDX 0x04 /* Directive type 0 */
356 #define IOE_EREAD1 0x85 /* Enhanced read type 1 */
357 #define IOE_EREAD1_IDX 0x05 /* Enhanced read type 1 */
358 #define IOE_EWRITE1 0x86 /* Enhanced write type 1 */
359 #define IOE_EWRITE1_IDX 0x06 /* Enhanced write type 1 */
360 #define IOE_DIRECT1 0x87 /* Directive type 1 */
361 #define IOE_DIRECT1_IDX 0x07 /* Directive type 1 */
362 #define IOE_RAC 0x8c /* Read with Atomic clear */
363 #define IOE_RAC_IDX 0x0c /* Read with Atomic clear */
364 #define IOE_RAS 0x8d /* Read with Atomic set */
365 #define IOE_RAS_IDX 0x0d /* Read with Atomic set */
366 #define IOE_RAD 0x8e /* Read with Atomic decrement */
367 #define IOE_RAD_IDX 0x0e /* Read with Atomic decrement */
368 #define IOE_RAI 0x8f /* Read with Atomic increment */
369 #define IOE_RAI_IDX 0x0f /* Read with Atomic increment */
371 #define EOE_READ 0x00
372 #define EOE_WRITE 0x01
373 #define EOE_RAC 0x0c /* Read with Atomic clear */
374 #define EOE_RAS 0x0d /* Read with Atomic set */
375 #define EOE_RAD 0x0e /* Read with Atomic decrement */
376 #define EOE_RAI 0x0f /* Read with Atomic increment */
377 #define EOE_LDEC 0x10 /* Load external cache */
378 #define EOE_LDECL 0x11 /* Load external cache with stash lock */
379 #define EOE_LDECPE 0x12 /* Load external cache with preferred exclusive */
380 #define EOE_LDECPEL 0x13 /* Load external cache with preferred exclusive and lock */
381 #define EOE_LDECFE 0x14 /* Load external cache with forced exclusive */
382 #define EOE_LDECFEL 0x15 /* Load external cache with forced exclusive and lock */
383 #define EOE_RSA 0x16 /* Read with stash allocate */
384 #define EOE_RSAU 0x17 /* Read with stash allocate and unlock */
385 #define EOE_READI 0x18 /* Read with invalidate */
386 #define EOE_RWNITC 0x19 /* Read with no intention to cache */
387 #define EOE_WCI 0x1a /* Write cache inhibited */
388 #define EOE_WWSA 0x1b /* Write with stash allocate */
389 #define EOE_WWSAL 0x1c /* Write with stash allocate and lock */
390 #define EOE_WWSAO 0x1d /* Write with stash allocate only */
391 #define EOE_WWSAOL 0x1e /* Write with stash allocate only and lock */
392 #define EOE_VALID 0x80