32 	struct irq_chip *chip = irq_desc_get_chip(desc);  in dw_apb_ictl_handler()  local
35 	chained_irq_enter(chip, desc);  in dw_apb_ictl_handler()
37 	for (n = 0; n < d->revmap_size; n += 32) {  in dw_apb_ictl_handler()
39 		u32 stat = readl_relaxed(gc->reg_base + APB_INT_FINALSTATUS_L);  in dw_apb_ictl_handler()
42 			u32 hwirq = ffs(stat) - 1;  in dw_apb_ictl_handler()
43 			u32 virq = irq_find_mapping(d, gc->irq_base + hwirq);  in dw_apb_ictl_handler()
50 	chained_irq_exit(chip, desc);  in dw_apb_ictl_handler()
60 	writel_relaxed(~0, gc->reg_base + ct->regs.enable);  in dw_apb_ictl_resume()
61 	writel_relaxed(*ct->mask_cache, gc->reg_base + ct->regs.mask);  in dw_apb_ictl_resume()
83 		return -EINVAL;  in dw_apb_ictl_init()
92 	if (!request_mem_region(r.start, resource_size(&r), np->full_name)) {  in dw_apb_ictl_init()
94 		return -ENOMEM;  in dw_apb_ictl_init()
100 		ret = -ENOMEM;  in dw_apb_ictl_init()
105 	 * DW IP can be configured to allow 2-64 irqs. We can determine  in dw_apb_ictl_init()
107 	 * and look for bits not set, as corresponding flip-flops will  in dw_apb_ictl_init()
127 		ret = -ENOMEM;  in dw_apb_ictl_init()
131 	ret = irq_alloc_domain_generic_chips(domain, 32, 1, np->name,  in dw_apb_ictl_init()
141 		gc->reg_base = iobase + i * APB_INT_BASE_OFFSET;  in dw_apb_ictl_init()
142 		gc->chip_types[0].regs.mask = APB_INT_MASK_L;  in dw_apb_ictl_init()
143 		gc->chip_types[0].regs.enable = APB_INT_ENABLE_L;  in dw_apb_ictl_init()
144 		gc->chip_types[0].chip.irq_mask = irq_gc_mask_set_bit;  in dw_apb_ictl_init()
145 		gc->chip_types[0].chip.irq_unmask = irq_gc_mask_clr_bit;  in dw_apb_ictl_init()
146 		gc->chip_types[0].chip.irq_resume = dw_apb_ictl_resume;  in dw_apb_ictl_init()
160 		"snps,dw-apb-ictl", dw_apb_ictl_init);