Lines Matching +full:ppi +full:- +full:partitions
2 * Copyright (C) 2013-2017 ARM Limited, All Rights Reserved.
33 #include <linux/irqchip/arm-gic-common.h>
34 #include <linux/irqchip/arm-gic-v3.h>
35 #include <linux/irqchip/irq-partition-percpu.h>
42 #include "irq-gic-common.h"
71 #define gic_data_rdist_rd_base() (gic_data_rdist()->rd_base)
79 return d->hwirq; in gic_irq()
89 if (gic_irq_in_rdist(d)) /* SGI+PPI -> SGI_base for this CPU */ in gic_dist_base()
92 if (d->hwirq <= 1023) /* SPI -> dist_base */ in gic_dist_base()
103 count--; in gic_do_wait_for_rwp()
158 while (--count) { in gic_enable_redist()
234 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ in gic_irq_set_irqchip_state()
235 return -EINVAL; in gic_irq_set_irqchip_state()
251 return -EINVAL; in gic_irq_set_irqchip_state()
261 if (d->hwirq >= gic_data.irq_nr) /* PPI/SPI only */ in gic_irq_get_irqchip_state()
262 return -EINVAL; in gic_irq_get_irqchip_state()
278 return -EINVAL; in gic_irq_get_irqchip_state()
308 return -EINVAL; in gic_set_type()
313 return -EINVAL; in gic_set_type()
406 * Configure SPIs as non-secure Group-1. This will only matter in gic_dist_init()
431 int ret = -ENODEV; in gic_iterate_rdists()
465 return ret ? -ENODEV : 0; in gic_iterate_rdists()
485 u64 offset = ptr - region->redist_base; in __gic_populate_rdist()
487 gic_data_rdist()->phys_base = region->phys_base + offset; in __gic_populate_rdist()
491 (int)(region - gic_data.redist_regions), in __gic_populate_rdist()
492 &gic_data_rdist()->phys_base); in __gic_populate_rdist()
506 WARN(true, "CPU%d: mpidr %lx has no re-distributor!\n", in gic_populate_rdist()
509 return -ENODEV; in gic_populate_rdist()
555 * setting the highest possible, non-zero priority in PMR. in gic_cpu_sys_reg_init()
559 * actual priority in the non-secure range. In the process, it in gic_cpu_sys_reg_init()
564 write_gicreg(BIT(8 - pribits), ICC_PMR_EL1); in gic_cpu_sys_reg_init()
574 * any pre-emptive interrupts from working at all). Writing a zero in gic_cpu_sys_reg_init()
639 * - The write is ignored. in gic_cpu_sys_reg_init()
640 * - The RS field is treated as 0. in gic_cpu_sys_reg_init()
671 /* Configure SGIs/PPIs as non-secure Group-1 */ in gic_cpu_init()
713 cpu--; in gic_compute_target_list()
788 return -EINVAL; in gic_set_affinity()
791 return -EINVAL; in gic_set_affinity()
896 return -EPERM; in gic_irq_domain_map()
899 return -EPERM; in gic_irq_domain_map()
902 return -EPERM; in gic_irq_domain_map()
907 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
913 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
921 return -EPERM; in gic_irq_domain_map()
922 irq_domain_set_info(d, irq, hw, chip, d->host_data, in gic_irq_domain_map()
936 if (is_of_node(fwspec->fwnode)) { in gic_irq_domain_translate()
937 if (fwspec->param_count < 3) in gic_irq_domain_translate()
938 return -EINVAL; in gic_irq_domain_translate()
940 switch (fwspec->param[0]) { in gic_irq_domain_translate()
942 *hwirq = fwspec->param[1] + 32; in gic_irq_domain_translate()
944 case 1: /* PPI */ in gic_irq_domain_translate()
946 *hwirq = fwspec->param[1] + 16; in gic_irq_domain_translate()
949 *hwirq = fwspec->param[1]; in gic_irq_domain_translate()
952 return -EINVAL; in gic_irq_domain_translate()
955 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in gic_irq_domain_translate()
962 fwspec->param[0] != GIC_IRQ_TYPE_PARTITION); in gic_irq_domain_translate()
966 if (is_fwnode_irqchip(fwspec->fwnode)) { in gic_irq_domain_translate()
967 if(fwspec->param_count != 2) in gic_irq_domain_translate()
968 return -EINVAL; in gic_irq_domain_translate()
970 *hwirq = fwspec->param[0]; in gic_irq_domain_translate()
971 *type = fwspec->param[1]; in gic_irq_domain_translate()
977 return -EINVAL; in gic_irq_domain_translate()
1018 if (fwspec->fwnode != d->fwnode) in gic_irq_domain_select()
1022 if (!is_of_node(fwspec->fwnode)) in gic_irq_domain_select()
1026 * If this is a PPI and we have a 4th (non-null) parameter, in gic_irq_domain_select()
1029 if (fwspec->param_count >= 4 && in gic_irq_domain_select()
1030 fwspec->param[0] == 1 && fwspec->param[3] != 0) in gic_irq_domain_select()
1031 return d == partition_get_domain(gic_data.ppi_descs[fwspec->param[1]]); in gic_irq_domain_select()
1051 np = of_find_node_by_phandle(fwspec->param[3]); in partition_domain_translate()
1053 return -EINVAL; in partition_domain_translate()
1055 ret = partition_translate_id(gic_data.ppi_descs[fwspec->param[1]], in partition_domain_translate()
1061 *type = fwspec->param[2] & IRQ_TYPE_SENSE_MASK; in partition_domain_translate()
1095 * The GIC only supports up to 1020 interrupt sources (SGI+PPI+SPI) in gic_init_bases()
1112 err = -ENOMEM; in gic_init_bases()
1152 return -ENODEV; in gic_validate_dist_version()
1157 /* Create all possible partitions at boot time */
1165 parts_node = of_get_child_by_name(gic_node, "ppi-partitions"); in gic_populate_ppi_partitions()
1184 part->partition_id = of_node_to_fwnode(child_part); in gic_populate_ppi_partitions()
1186 pr_info("GIC: PPI partition %s[%d] { ", in gic_populate_ppi_partitions()
1187 child_part->name, part_idx); in gic_populate_ppi_partitions()
1213 cpumask_set_cpu(cpu, &part->mask); in gic_populate_ppi_partitions()
1260 if (of_property_read_u32(node, "#redistributor-regions", in gic_of_setup_kvm_info()
1284 return -ENXIO; in gic_of_init()
1293 if (of_property_read_u32(node, "#redistributor-regions", &nr_redist_regions)) in gic_of_init()
1299 err = -ENOMEM; in gic_of_init()
1311 err = -ENODEV; in gic_of_init()
1317 if (of_property_read_u64(node, "redistributor-stride", &redist_stride)) in gic_of_init()
1321 redist_stride, &node->fwnode); in gic_of_init()
1341 IRQCHIP_DECLARE(gic_v3, "arm,gic-v3", gic_of_init);
1375 redist_base = ioremap(redist->base_address, redist->length); in gic_acpi_parse_madt_redist()
1377 pr_err("Couldn't map GICR region @%llx\n", redist->base_address); in gic_acpi_parse_madt_redist()
1378 return -ENOMEM; in gic_acpi_parse_madt_redist()
1381 gic_acpi_register_redist(redist->base_address, redist_base); in gic_acpi_parse_madt_redist()
1396 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_madt_gicc()
1399 redist_base = ioremap(gicc->gicr_base_address, size); in gic_acpi_parse_madt_gicc()
1401 return -ENOMEM; in gic_acpi_parse_madt_gicc()
1403 gic_acpi_register_redist(gicc->gicr_base_address, redist_base); in gic_acpi_parse_madt_gicc()
1425 return -ENODEV; in gic_acpi_collect_gicr_base()
1445 if ((gicc->flags & ACPI_MADT_ENABLED) && gicc->gicr_base_address) { in gic_acpi_match_gicc()
1454 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_match_gicc()
1457 return -ENODEV; in gic_acpi_match_gicc()
1493 if (dist->version != ape->driver_data) in acpi_validate_gic_table()
1514 if (!(gicc->flags & ACPI_MADT_ENABLED)) in gic_acpi_parse_virt_madt_gicc()
1517 maint_irq_mode = (gicc->flags & ACPI_MADT_VGIC_IRQ_MODE) ? in gic_acpi_parse_virt_madt_gicc()
1523 acpi_data.maint_irq = gicc->vgic_interrupt; in gic_acpi_parse_virt_madt_gicc()
1525 acpi_data.vcpu_base = gicc->gicv_base_address; in gic_acpi_parse_virt_madt_gicc()
1533 if ((acpi_data.maint_irq != gicc->vgic_interrupt) || in gic_acpi_parse_virt_madt_gicc()
1535 (acpi_data.vcpu_base != gicc->gicv_base_address)) in gic_acpi_parse_virt_madt_gicc()
1536 return -EINVAL; in gic_acpi_parse_virt_madt_gicc()
1577 vcpu->flags = IORESOURCE_MEM; in gic_acpi_setup_kvm_info()
1578 vcpu->start = acpi_data.vcpu_base; in gic_acpi_setup_kvm_info()
1579 vcpu->end = vcpu->start + ACPI_GICV2_VCPU_MEM_SIZE - 1; in gic_acpi_setup_kvm_info()
1596 acpi_data.dist_base = ioremap(dist->base_address, in gic_acpi_init()
1600 return -ENOMEM; in gic_acpi_init()
1613 err = -ENOMEM; in gic_acpi_init()
1623 err = -ENOMEM; in gic_acpi_init()