Lines Matching full:gic
8 * Interrupt architecture for the GIC:
43 #include <linux/irqchip/arm-gic.h>
51 #include "irq-gic-common.h"
117 * The GIC mapping of CPU interfaces does not necessarily match
119 * by the GIC itself.
312 /* Only interrupts on the primary GIC can be forwarded to a vcpu. */ in gic_irq_set_vcpu_affinity()
348 struct gic_chip_data *gic = &gic_data[0]; in gic_handle_irq() local
349 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_handle_irq()
359 handle_domain_irq(gic->domain, irqnr, regs); in gic_handle_irq()
370 * on the GIC. in gic_handle_irq()
429 static u8 gic_get_cpumask(struct gic_chip_data *gic) in gic_get_cpumask() argument
431 void __iomem *base = gic_data_dist_base(gic); in gic_get_cpumask()
443 pr_crit("GIC CPU mask not found - kernel will fail to boot.\n"); in gic_get_cpumask()
454 static void gic_cpu_if_up(struct gic_chip_data *gic) in gic_cpu_if_up() argument
456 void __iomem *cpu_base = gic_data_cpu_base(gic); in gic_cpu_if_up()
461 if (gic == &gic_data[0] && static_branch_likely(&supports_deactivate_key)) in gic_cpu_if_up()
478 static void gic_dist_init(struct gic_chip_data *gic) in gic_dist_init() argument
482 unsigned int gic_irqs = gic->gic_irqs; in gic_dist_init()
483 void __iomem *base = gic_data_dist_base(gic); in gic_dist_init()
490 cpumask = gic_get_cpumask(gic); in gic_dist_init()
501 static int gic_cpu_init(struct gic_chip_data *gic) in gic_cpu_init() argument
503 void __iomem *dist_base = gic_data_dist_base(gic); in gic_cpu_init()
504 void __iomem *base = gic_data_cpu_base(gic); in gic_cpu_init()
509 * Setting up the CPU map is only relevant for the primary GIC in gic_cpu_init()
513 if (gic == &gic_data[0]) { in gic_cpu_init()
515 * Get what the GIC says our CPU mask is. in gic_cpu_init()
521 cpu_mask = gic_get_cpumask(gic); in gic_cpu_init()
536 gic_cpu_if_up(gic); in gic_cpu_init()
559 * Saves the GIC distributor registers during suspend or idle. Must be called
560 * with interrupts disabled but before powering down the GIC. After calling
561 * this function, no interrupts will be delivered by the GIC, and another
564 void gic_dist_save(struct gic_chip_data *gic) in gic_dist_save() argument
570 if (WARN_ON(!gic)) in gic_dist_save()
573 gic_irqs = gic->gic_irqs; in gic_dist_save()
574 dist_base = gic_data_dist_base(gic); in gic_dist_save()
580 gic->saved_spi_conf[i] = in gic_dist_save()
584 gic->saved_spi_target[i] = in gic_dist_save()
588 gic->saved_spi_enable[i] = in gic_dist_save()
592 gic->saved_spi_active[i] = in gic_dist_save()
597 * Restores the GIC distributor registers during resume or when coming out of
599 * that occured while the GIC was suspended is still present, it will be
601 * the GIC and need to be handled by the platform-specific wakeup source.
603 void gic_dist_restore(struct gic_chip_data *gic) in gic_dist_restore() argument
609 if (WARN_ON(!gic)) in gic_dist_restore()
612 gic_irqs = gic->gic_irqs; in gic_dist_restore()
613 dist_base = gic_data_dist_base(gic); in gic_dist_restore()
621 writel_relaxed(gic->saved_spi_conf[i], in gic_dist_restore()
629 writel_relaxed(gic->saved_spi_target[i], in gic_dist_restore()
635 writel_relaxed(gic->saved_spi_enable[i], in gic_dist_restore()
642 writel_relaxed(gic->saved_spi_active[i], in gic_dist_restore()
649 void gic_cpu_save(struct gic_chip_data *gic) in gic_cpu_save() argument
656 if (WARN_ON(!gic)) in gic_cpu_save()
659 dist_base = gic_data_dist_base(gic); in gic_cpu_save()
660 cpu_base = gic_data_cpu_base(gic); in gic_cpu_save()
665 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_save()
669 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_save()
673 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_save()
679 void gic_cpu_restore(struct gic_chip_data *gic) in gic_cpu_restore() argument
686 if (WARN_ON(!gic)) in gic_cpu_restore()
689 dist_base = gic_data_dist_base(gic); in gic_cpu_restore()
690 cpu_base = gic_data_cpu_base(gic); in gic_cpu_restore()
695 ptr = raw_cpu_ptr(gic->saved_ppi_enable); in gic_cpu_restore()
702 ptr = raw_cpu_ptr(gic->saved_ppi_active); in gic_cpu_restore()
709 ptr = raw_cpu_ptr(gic->saved_ppi_conf); in gic_cpu_restore()
718 gic_cpu_if_up(gic); in gic_cpu_restore()
756 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
758 gic->saved_ppi_enable = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
760 if (WARN_ON(!gic->saved_ppi_enable)) in gic_pm_init()
763 gic->saved_ppi_active = __alloc_percpu(DIV_ROUND_UP(32, 32) * 4, in gic_pm_init()
765 if (WARN_ON(!gic->saved_ppi_active)) in gic_pm_init()
768 gic->saved_ppi_conf = __alloc_percpu(DIV_ROUND_UP(32, 16) * 4, in gic_pm_init()
770 if (WARN_ON(!gic->saved_ppi_conf)) in gic_pm_init()
773 if (gic == &gic_data[0]) in gic_pm_init()
779 free_percpu(gic->saved_ppi_active); in gic_pm_init()
781 free_percpu(gic->saved_ppi_enable); in gic_pm_init()
786 static int gic_pm_init(struct gic_chip_data *gic) in gic_pm_init() argument
842 * @cpu: the logical CPU number to get the GIC ID for.
955 pr_info("GIC physical location is %#lx\n", gic_dist_physaddr); in gic_init_physaddr()
966 struct gic_chip_data *gic = d->host_data; in gic_irq_domain_map() local
970 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, in gic_irq_domain_map()
974 irq_domain_set_info(d, irq, hw, &gic->chip, d->host_data, in gic_irq_domain_map()
999 * For SPIs, we need to add 16 more to get the GIC irq in gic_irq_domain_translate()
1064 static void gic_init_chip(struct gic_chip_data *gic, struct device *dev, in gic_init_chip() argument
1068 gic->chip = gic_chip; in gic_init_chip()
1069 gic->chip.name = name; in gic_init_chip()
1070 gic->chip.parent_device = dev; in gic_init_chip()
1073 gic->chip.irq_mask = gic_eoimode1_mask_irq; in gic_init_chip()
1074 gic->chip.irq_eoi = gic_eoimode1_eoi_irq; in gic_init_chip()
1075 gic->chip.irq_set_vcpu_affinity = gic_irq_set_vcpu_affinity; in gic_init_chip()
1079 if (gic == &gic_data[0]) in gic_init_chip()
1080 gic->chip.irq_set_affinity = gic_set_affinity; in gic_init_chip()
1084 static int gic_init_bases(struct gic_chip_data *gic, int irq_start, in gic_init_bases() argument
1090 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1091 /* Frankein-GIC without banked registers... */ in gic_init_bases()
1094 gic->dist_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1095 gic->cpu_base.percpu_base = alloc_percpu(void __iomem *); in gic_init_bases()
1096 if (WARN_ON(!gic->dist_base.percpu_base || in gic_init_bases()
1097 !gic->cpu_base.percpu_base)) { in gic_init_bases()
1105 unsigned long offset = gic->percpu_offset * core_id; in gic_init_bases()
1106 *per_cpu_ptr(gic->dist_base.percpu_base, cpu) = in gic_init_bases()
1107 gic->raw_dist_base + offset; in gic_init_bases()
1108 *per_cpu_ptr(gic->cpu_base.percpu_base, cpu) = in gic_init_bases()
1109 gic->raw_cpu_base + offset; in gic_init_bases()
1112 gic_set_base_accessor(gic, gic_get_percpu_base); in gic_init_bases()
1114 /* Normal, sane GIC... */ in gic_init_bases()
1115 WARN(gic->percpu_offset, in gic_init_bases()
1117 gic->percpu_offset); in gic_init_bases()
1118 gic->dist_base.common_base = gic->raw_dist_base; in gic_init_bases()
1119 gic->cpu_base.common_base = gic->raw_cpu_base; in gic_init_bases()
1120 gic_set_base_accessor(gic, gic_get_common_base); in gic_init_bases()
1125 * The GIC only supports up to 1020 interrupt sources. in gic_init_bases()
1127 gic_irqs = readl_relaxed(gic_data_dist_base(gic) + GIC_DIST_CTR) & 0x1f; in gic_init_bases()
1131 gic->gic_irqs = gic_irqs; in gic_init_bases()
1134 gic->domain = irq_domain_create_linear(handle, gic_irqs, in gic_init_bases()
1136 gic); in gic_init_bases()
1142 if (gic == &gic_data[0] && (irq_start & 31) > 0) { in gic_init_bases()
1160 gic->domain = irq_domain_add_legacy(NULL, gic_irqs, irq_base, in gic_init_bases()
1161 hwirq_base, &gic_irq_domain_ops, gic); in gic_init_bases()
1164 if (WARN_ON(!gic->domain)) { in gic_init_bases()
1169 gic_dist_init(gic); in gic_init_bases()
1170 ret = gic_cpu_init(gic); in gic_init_bases()
1174 ret = gic_pm_init(gic); in gic_init_bases()
1181 if (IS_ENABLED(CONFIG_GIC_NON_BANKED) && gic->percpu_offset) { in gic_init_bases()
1182 free_percpu(gic->dist_base.percpu_base); in gic_init_bases()
1183 free_percpu(gic->cpu_base.percpu_base); in gic_init_bases()
1189 static int __init __gic_init_bases(struct gic_chip_data *gic, in __gic_init_bases() argument
1196 if (WARN_ON(!gic || gic->domain)) in __gic_init_bases()
1199 if (gic == &gic_data[0]) { in __gic_init_bases()
1203 * This is only necessary for the primary GIC. in __gic_init_bases()
1211 "irqchip/arm/gic:starting", in __gic_init_bases()
1215 pr_info("GIC: Using split EOI/Deactivate mode\n"); in __gic_init_bases()
1218 if (static_branch_likely(&supports_deactivate_key) && gic == &gic_data[0]) { in __gic_init_bases()
1220 gic_init_chip(gic, NULL, name, true); in __gic_init_bases()
1222 name = kasprintf(GFP_KERNEL, "GIC-%d", (int)(gic-&gic_data[0])); in __gic_init_bases()
1223 gic_init_chip(gic, NULL, name, false); in __gic_init_bases()
1226 ret = gic_init_bases(gic, irq_start, handle); in __gic_init_bases()
1236 struct gic_chip_data *gic; in gic_init() local
1247 gic = &gic_data[gic_nr]; in gic_init()
1248 gic->raw_dist_base = dist_base; in gic_init()
1249 gic->raw_cpu_base = cpu_base; in gic_init()
1251 __gic_init_bases(gic, irq_start, NULL); in gic_init()
1254 static void gic_teardown(struct gic_chip_data *gic) in gic_teardown() argument
1256 if (WARN_ON(!gic)) in gic_teardown()
1259 if (gic->raw_dist_base) in gic_teardown()
1260 iounmap(gic->raw_dist_base); in gic_teardown()
1261 if (gic->raw_cpu_base) in gic_teardown()
1262 iounmap(gic->raw_cpu_base); in gic_teardown()
1293 pr_warn("GIC: GICv2 detected, but range too small and irqchip.gicv2_force_probe not set\n"); in gic_check_eoimode()
1306 pr_warn("GIC: GICv2 at %pa, but range is too small (broken DT?), assuming 8kB\n", in gic_check_eoimode()
1323 pr_warn("GIC: Aliased GICv2 at %pa, trying to find the canonical range over 128kB\n", in gic_check_eoimode()
1346 pr_warn("GIC: Adjusting CPU interface base to %pa\n", in gic_check_eoimode()
1353 static int gic_of_setup(struct gic_chip_data *gic, struct device_node *node) in gic_of_setup() argument
1355 if (!gic || !node) in gic_of_setup()
1358 gic->raw_dist_base = of_iomap(node, 0); in gic_of_setup()
1359 if (WARN(!gic->raw_dist_base, "unable to map gic dist registers\n")) in gic_of_setup()
1362 gic->raw_cpu_base = of_iomap(node, 1); in gic_of_setup()
1363 if (WARN(!gic->raw_cpu_base, "unable to map gic cpu registers\n")) in gic_of_setup()
1366 if (of_property_read_u32(node, "cpu-offset", &gic->percpu_offset)) in gic_of_setup()
1367 gic->percpu_offset = 0; in gic_of_setup()
1372 gic_teardown(gic); in gic_of_setup()
1377 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1381 if (!dev || !dev->of_node || !gic || !irq) in gic_of_init_child()
1384 *gic = devm_kzalloc(dev, sizeof(**gic), GFP_KERNEL); in gic_of_init_child()
1385 if (!*gic) in gic_of_init_child()
1388 gic_init_chip(*gic, dev, dev->of_node->name, false); in gic_of_init_child()
1390 ret = gic_of_setup(*gic, dev->of_node); in gic_of_init_child()
1394 ret = gic_init_bases(*gic, -1, &dev->of_node->fwnode); in gic_of_init_child()
1396 gic_teardown(*gic); in gic_of_init_child()
1400 irq_set_chained_handler_and_data(irq, gic_handle_cascade_irq, *gic); in gic_of_init_child()
1432 struct gic_chip_data *gic; in gic_of_init() local
1441 gic = &gic_data[gic_cnt]; in gic_of_init()
1443 ret = gic_of_setup(gic, node); in gic_of_init()
1451 if (gic_cnt == 0 && !gic_check_eoimode(node, &gic->raw_cpu_base)) in gic_of_init()
1454 ret = __gic_init_bases(gic, -1, &node->fwnode); in gic_of_init()
1456 gic_teardown(gic); in gic_of_init()
1476 IRQCHIP_DECLARE(gic_400, "arm,gic-400", gic_of_init);
1477 IRQCHIP_DECLARE(arm11mp_gic, "arm,arm11mp-gic", gic_of_init);
1478 IRQCHIP_DECLARE(arm1176jzf_dc_gic, "arm,arm1176jzf-devchip-gic", gic_of_init);
1479 IRQCHIP_DECLARE(cortex_a15_gic, "arm,cortex-a15-gic", gic_of_init);
1480 IRQCHIP_DECLARE(cortex_a9_gic, "arm,cortex-a9-gic", gic_of_init);
1481 IRQCHIP_DECLARE(cortex_a7_gic, "arm,cortex-a7-gic", gic_of_init);
1486 int gic_of_init_child(struct device *dev, struct gic_chip_data **gic, int irq) in gic_of_init_child() argument
1601 struct gic_chip_data *gic = &gic_data[0]; in gic_v2_acpi_init() local
1612 gic->raw_cpu_base = ioremap(acpi_data.cpu_phys_base, ACPI_GIC_CPU_IF_MEM_SIZE); in gic_v2_acpi_init()
1613 if (!gic->raw_cpu_base) { in gic_v2_acpi_init()
1619 gic->raw_dist_base = ioremap(dist->base_address, in gic_v2_acpi_init()
1621 if (!gic->raw_dist_base) { in gic_v2_acpi_init()
1623 gic_teardown(gic); in gic_v2_acpi_init()
1636 * Initialize GIC instance zero (no multi-GIC support). in gic_v2_acpi_init()
1638 domain_handle = irq_domain_alloc_fwnode(gic->raw_dist_base); in gic_v2_acpi_init()
1641 gic_teardown(gic); in gic_v2_acpi_init()
1645 ret = __gic_init_bases(gic, -1, domain_handle); in gic_v2_acpi_init()
1647 pr_err("Failed to initialise GIC\n"); in gic_v2_acpi_init()
1649 gic_teardown(gic); in gic_v2_acpi_init()