46 	struct ingenic_intc_data *intc = irq_get_handler_data(irq);  in intc_cascade()  local
50 	for (i = 0; i < intc->num_chips; i++) {  in intc_cascade()
51 		irq_reg = readl(intc->base + (i * CHIP_SIZE) +  in intc_cascade()
84 	.name = "SoC intc cascade interrupt",
90 	struct ingenic_intc_data *intc;  in ingenic_intc_of_init()  local
97 	intc = kzalloc(sizeof(*intc), GFP_KERNEL);  in ingenic_intc_of_init()
98 	if (!intc) {  in ingenic_intc_of_init()
109 	err = irq_set_handler_data(parent_irq, intc);  in ingenic_intc_of_init()
113 	intc->num_chips = num_chips;  in ingenic_intc_of_init()
114 	intc->base = of_iomap(node, 0);  in ingenic_intc_of_init()
115 	if (!intc->base) {  in ingenic_intc_of_init()
130 		writel(0xffffffff, intc->base + (i * CHIP_SIZE) +  in ingenic_intc_of_init()
133 		gc = irq_alloc_generic_chip("INTC", 1,  in ingenic_intc_of_init()
135 					    intc->base + (i * CHIP_SIZE),  in ingenic_intc_of_init()
158 	iounmap(intc->base);  in ingenic_intc_of_init()
162 	kfree(intc);  in ingenic_intc_of_init()
172 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
173 IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
180 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
181 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
182 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);