2  *  Copyright (C) 2009-2010, Lars-Peter Clausen <lars@metafoo.de>
30 #include <asm/mach-jz4740/irq.h>
46 	struct ingenic_intc_data *intc = irq_get_handler_data(irq);  in intc_cascade()  local
50 	for (i = 0; i < intc->num_chips; i++) {  in intc_cascade()
51 		irq_reg = readl(intc->base + (i * CHIP_SIZE) +  in intc_cascade()
64 	struct irq_chip_regs *regs = &gc->chip_types->regs;  in intc_irq_set_mask()
66 	writel(mask, gc->reg_base + regs->enable);  in intc_irq_set_mask()
67 	writel(~mask, gc->reg_base + regs->disable);  in intc_irq_set_mask()
73 	intc_irq_set_mask(gc, gc->wake_active);  in ingenic_intc_irq_suspend()
79 	intc_irq_set_mask(gc, gc->mask_cache);  in ingenic_intc_irq_resume()
84 	.name = "SoC intc cascade interrupt",
90 	struct ingenic_intc_data *intc;  in ingenic_intc_of_init()  local
97 	intc = kzalloc(sizeof(*intc), GFP_KERNEL);  in ingenic_intc_of_init()
98 	if (!intc) {  in ingenic_intc_of_init()
99 		err = -ENOMEM;  in ingenic_intc_of_init()
105 		err = -EINVAL;  in ingenic_intc_of_init()
109 	err = irq_set_handler_data(parent_irq, intc);  in ingenic_intc_of_init()
113 	intc->num_chips = num_chips;  in ingenic_intc_of_init()
114 	intc->base = of_iomap(node, 0);  in ingenic_intc_of_init()
115 	if (!intc->base) {  in ingenic_intc_of_init()
116 		err = -ENODEV;  in ingenic_intc_of_init()
124 		err = -ENOMEM;  in ingenic_intc_of_init()
130 		writel(0xffffffff, intc->base + (i * CHIP_SIZE) +  in ingenic_intc_of_init()
133 		gc = irq_alloc_generic_chip("INTC", 1,  in ingenic_intc_of_init()
135 					    intc->base + (i * CHIP_SIZE),  in ingenic_intc_of_init()
138 		gc->wake_enabled = IRQ_MSK(32);  in ingenic_intc_of_init()
140 		ct = gc->chip_types;  in ingenic_intc_of_init()
141 		ct->regs.enable = JZ_REG_INTC_CLEAR_MASK;  in ingenic_intc_of_init()
142 		ct->regs.disable = JZ_REG_INTC_SET_MASK;  in ingenic_intc_of_init()
143 		ct->chip.irq_unmask = irq_gc_unmask_enable_reg;  in ingenic_intc_of_init()
144 		ct->chip.irq_mask = irq_gc_mask_disable_reg;  in ingenic_intc_of_init()
145 		ct->chip.irq_mask_ack = irq_gc_mask_disable_reg;  in ingenic_intc_of_init()
146 		ct->chip.irq_set_wake = irq_gc_set_wake;  in ingenic_intc_of_init()
147 		ct->chip.irq_suspend = ingenic_intc_irq_suspend;  in ingenic_intc_of_init()
148 		ct->chip.irq_resume = ingenic_intc_irq_resume;  in ingenic_intc_of_init()
158 	iounmap(intc->base);  in ingenic_intc_of_init()
162 	kfree(intc);  in ingenic_intc_of_init()
172 IRQCHIP_DECLARE(jz4740_intc, "ingenic,jz4740-intc", intc_1chip_of_init);
173 IRQCHIP_DECLARE(jz4725b_intc, "ingenic,jz4725b-intc", intc_1chip_of_init);
180 IRQCHIP_DECLARE(jz4770_intc, "ingenic,jz4770-intc", intc_2chip_of_init);
181 IRQCHIP_DECLARE(jz4775_intc, "ingenic,jz4775-intc", intc_2chip_of_init);
182 IRQCHIP_DECLARE(jz4780_intc, "ingenic,jz4780-intc", intc_2chip_of_init);