30 #define PJ1_INT_SEL		0x10c
31 #define PJ4_INT_SEL		0x104
35 #define SEL_INT_NUM_MASK	0x3f
74 	if (data == &icu_data[0]) {  in icu_mask_ack_irq()
98 	if (data == &icu_data[0]) {  in icu_mask_irq()
117 	if (data == &icu_data[0]) {  in icu_unmask_irq()
158 		if (status == 0)  in icu_mux_irq_demux()
170 	return 0;  in mmp_irq_domain_map()
178 	*out_hwirq = intspec[0];  in mmp_irq_domain_xlate()
179 	return 0;  in mmp_irq_domain_xlate()
188 	.conf_enable	= 0x51,
189 	.conf_disable	= 0x0,
190 	.conf_mask	= 0x7f,
194 	.conf_enable	= 0x20,
195 	.conf_disable	= 0x0,
208 	handle_domain_irq(icu_data[0].domain, hwirq, regs);  in mmp_handle_irq()
219 	handle_domain_irq(icu_data[0].domain, hwirq, regs);  in mmp2_handle_irq()
228 	mmp_icu_base = ioremap(0xd4282000, 0x1000);  in icu_init_irq()
229 	icu_data[0].conf_enable = mmp_conf.conf_enable;  in icu_init_irq()
230 	icu_data[0].conf_disable = mmp_conf.conf_disable;  in icu_init_irq()
231 	icu_data[0].conf_mask = mmp_conf.conf_mask;  in icu_init_irq()
232 	icu_data[0].nr_irqs = 64;  in icu_init_irq()
233 	icu_data[0].virq_base = 0;  in icu_init_irq()
234 	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,  in icu_init_irq()
236 						   &icu_data[0]);  in icu_init_irq()
237 	for (irq = 0; irq < 64; irq++) {  in icu_init_irq()
241 	irq_set_default_host(icu_data[0].domain);  in icu_init_irq()
251 	mmp_icu_base = ioremap(0xd4282000, 0x1000);  in mmp2_init_icu()
252 	icu_data[0].conf_enable = mmp2_conf.conf_enable;  in mmp2_init_icu()
253 	icu_data[0].conf_disable = mmp2_conf.conf_disable;  in mmp2_init_icu()
254 	icu_data[0].conf_mask = mmp2_conf.conf_mask;  in mmp2_init_icu()
255 	icu_data[0].nr_irqs = 64;  in mmp2_init_icu()
256 	icu_data[0].virq_base = 0;  in mmp2_init_icu()
257 	icu_data[0].domain = irq_domain_add_legacy(NULL, 64, 0, 0,  in mmp2_init_icu()
259 						   &icu_data[0]);  in mmp2_init_icu()
260 	icu_data[1].reg_status = mmp_icu_base + 0x150;  in mmp2_init_icu()
261 	icu_data[1].reg_mask = mmp_icu_base + 0x168;  in mmp2_init_icu()
262 	icu_data[1].clr_mfp_irq_base = icu_data[0].virq_base +  in mmp2_init_icu()
263 				icu_data[0].nr_irqs;  in mmp2_init_icu()
267 	icu_data[1].virq_base = icu_data[0].virq_base + icu_data[0].nr_irqs;  in mmp2_init_icu()
269 						   icu_data[1].virq_base, 0,  in mmp2_init_icu()
272 	icu_data[2].reg_status = mmp_icu_base + 0x154;  in mmp2_init_icu()
273 	icu_data[2].reg_mask = mmp_icu_base + 0x16c;  in mmp2_init_icu()
278 						   icu_data[2].virq_base, 0,  in mmp2_init_icu()
281 	icu_data[3].reg_status = mmp_icu_base + 0x180;  in mmp2_init_icu()
282 	icu_data[3].reg_mask = mmp_icu_base + 0x17c;  in mmp2_init_icu()
287 						   icu_data[3].virq_base, 0,  in mmp2_init_icu()
290 	icu_data[4].reg_status = mmp_icu_base + 0x158;  in mmp2_init_icu()
291 	icu_data[4].reg_mask = mmp_icu_base + 0x170;  in mmp2_init_icu()
296 						   icu_data[4].virq_base, 0,  in mmp2_init_icu()
299 	icu_data[5].reg_status = mmp_icu_base + 0x15c;  in mmp2_init_icu()
300 	icu_data[5].reg_mask = mmp_icu_base + 0x174;  in mmp2_init_icu()
305 						   icu_data[5].virq_base, 0,  in mmp2_init_icu()
308 	icu_data[6].reg_status = mmp_icu_base + 0x160;  in mmp2_init_icu()
309 	icu_data[6].reg_mask = mmp_icu_base + 0x178;  in mmp2_init_icu()
314 						   icu_data[6].virq_base, 0,  in mmp2_init_icu()
317 	icu_data[7].reg_status = mmp_icu_base + 0x188;  in mmp2_init_icu()
318 	icu_data[7].reg_mask = mmp_icu_base + 0x184;  in mmp2_init_icu()
323 						   icu_data[7].virq_base, 0,  in mmp2_init_icu()
327 	for (irq = 0; irq < end; irq++) {  in mmp2_init_icu()
343 	irq_set_default_host(icu_data[0].domain);  in mmp2_init_icu()
350 	int ret, nr_irqs, irq, i = 0;  in mmp_init_bases()
358 	mmp_icu_base = of_iomap(node, 0);  in mmp_init_bases()
364 	icu_data[0].virq_base = 0;  in mmp_init_bases()
365 	icu_data[0].domain = irq_domain_add_linear(node, nr_irqs,  in mmp_init_bases()
367 						   &icu_data[0]);  in mmp_init_bases()
368 	for (irq = 0; irq < nr_irqs; irq++) {  in mmp_init_bases()
369 		ret = irq_create_mapping(icu_data[0].domain, irq);  in mmp_init_bases()
375 			icu_data[0].virq_base = ret;  in mmp_init_bases()
377 	icu_data[0].nr_irqs = nr_irqs;  in mmp_init_bases()
378 	return 0;  in mmp_init_bases()
380 	if (icu_data[0].virq_base) {  in mmp_init_bases()
381 		for (i = 0; i < irq; i++)  in mmp_init_bases()
382 			irq_dispose_mapping(icu_data[0].virq_base + i);  in mmp_init_bases()
384 	irq_domain_remove(icu_data[0].domain);  in mmp_init_bases()
395 	if (ret < 0)  in mmp_of_init()
398 	icu_data[0].conf_enable = mmp_conf.conf_enable;  in mmp_of_init()
399 	icu_data[0].conf_disable = mmp_conf.conf_disable;  in mmp_of_init()
400 	icu_data[0].conf_mask = mmp_conf.conf_mask;  in mmp_of_init()
401 	irq_set_default_host(icu_data[0].domain);  in mmp_of_init()
404 	return 0;  in mmp_of_init()
414 	if (ret < 0)  in mmp2_of_init()
417 	icu_data[0].conf_enable = mmp2_conf.conf_enable;  in mmp2_of_init()
418 	icu_data[0].conf_disable = mmp2_conf.conf_disable;  in mmp2_of_init()
419 	icu_data[0].conf_mask = mmp2_conf.conf_mask;  in mmp2_of_init()
420 	irq_set_default_host(icu_data[0].domain);  in mmp2_of_init()
423 	return 0;  in mmp2_of_init()
431 	int i, ret, irq, j = 0;  in mmp2_mux_of_init()
444 	ret = of_address_to_resource(node, 0, &res);  in mmp2_mux_of_init()
445 	if (ret < 0) {  in mmp2_mux_of_init()
451 	if (ret < 0) {  in mmp2_mux_of_init()
456 	icu_data[i].cascade_irq = irq_of_parse_and_map(node, 0);  in mmp2_mux_of_init()
460 	icu_data[i].virq_base = 0;  in mmp2_mux_of_init()
464 	for (irq = 0; irq < nr_irqs; irq++) {  in mmp2_mux_of_init()
482 	return 0;  in mmp2_mux_of_init()
485 		for (j = 0; j < irq; j++)  in mmp2_mux_of_init()