Lines Matching +full:irqs +full:- +full:reserved
2 * drivers/irq/irq-nvic.c
4 * Copyright (C) 2008 ARM Limited, All Rights Reserved.
12 * ARMv7-M CPUs (Cortex-M3/M4)
36 * Each bank handles 32 irqs. Only the 16th (= last) bank handles only
37 * 16 irqs.
39 #define NVIC_MAX_IRQ ((NVIC_MAX_BANKS - 1) * 32 + 16)
55 if (WARN_ON(fwspec->param_count < 1)) in nvic_irq_domain_translate()
56 return -EINVAL; in nvic_irq_domain_translate()
57 *hwirq = fwspec->param[0]; in nvic_irq_domain_translate()
90 unsigned int irqs, i, ret, numbanks; in nvic_of_init() local
99 return -ENOMEM; in nvic_of_init()
102 irqs = numbanks * 32; in nvic_of_init()
103 if (irqs > NVIC_MAX_IRQ) in nvic_of_init()
104 irqs = NVIC_MAX_IRQ; in nvic_of_init()
107 irq_domain_add_linear(node, irqs, &nvic_irq_domain_ops, NULL); in nvic_of_init()
111 return -ENOMEM; in nvic_of_init()
127 gc->reg_base = nvic_base + 4 * i; in nvic_of_init()
128 gc->chip_types[0].regs.enable = NVIC_ISER; in nvic_of_init()
129 gc->chip_types[0].regs.disable = NVIC_ICER; in nvic_of_init()
130 gc->chip_types[0].chip.irq_mask = irq_gc_mask_disable_reg; in nvic_of_init()
131 gc->chip_types[0].chip.irq_unmask = irq_gc_unmask_enable_reg; in nvic_of_init()
132 /* This is a no-op as end of interrupt is signaled by the in nvic_of_init()
135 gc->chip_types[0].chip.irq_eoi = irq_gc_noop; in nvic_of_init()
138 writel_relaxed(~0, gc->reg_base + NVIC_ICER); in nvic_of_init()
142 for (i = 0; i < irqs; i += 4) in nvic_of_init()
147 IRQCHIP_DECLARE(armv7m_nvic, "arm,armv7m-nvic", nvic_of_init);