17  * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
48  * SENSE is read-write 32-bit with 2-bits or 4-bits per IRQ (*)
49  * PRIO is read-write 32-bit with 4-bits per IRQ (**)
50  * SOURCE is read-only 32-bit or 8-bit with 1-bit per IRQ (***)
51  * MASK is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
52  * CLEAR is write-only 32-bit or 8-bit with 1-bit per IRQ (***)
54  * (*) May be accessed by more than one driver instance - lock needed
55  * (**) Read-modify-write access by one driver instance - lock needed
56  * (***) Accessed by one driver instance only - no locking needed
63 	int width;  member
113 	struct intc_irqpin_iomem *i = &p->iomem[reg];  in intc_irqpin_read()
115 	return i->read(i->iomem);  in intc_irqpin_read()
121 	struct intc_irqpin_iomem *i = &p->iomem[reg];  in intc_irqpin_write()
123 	i->write(i->iomem, data);  in intc_irqpin_write()
129 	return BIT((p->iomem[reg].width - 1) - hw_irq);  in intc_irqpin_hwirq_mask()
142 					  int width, int value)  in intc_irqpin_read_modify_write()  argument
150 	tmp &= ~(((1 << width) - 1) << shift);  in intc_irqpin_read_modify_write()
160 	/* The PRIO register is assumed to be 32-bit with fixed 4-bit fields. */  in intc_irqpin_mask_unmask_prio()
162 	int shift = 32 - (irq + 1) * bitfield_width;  in intc_irqpin_mask_unmask_prio()
166 				      do_mask ? 0 : (1 << bitfield_width) - 1);  in intc_irqpin_mask_unmask_prio()
171 	/* The SENSE register is assumed to be 32-bit. */  in intc_irqpin_set_sense()
172 	int bitfield_width = p->sense_bitfield_width;  in intc_irqpin_set_sense()
173 	int shift = 32 - (irq + 1) * bitfield_width;  in intc_irqpin_set_sense()
175 	dev_dbg(&p->pdev->dev, "sense irq = %d, mode = %d\n", irq, value);  in intc_irqpin_set_sense()
178 		return -EINVAL;  in intc_irqpin_set_sense()
187 	dev_dbg(&i->p->pdev->dev, "%s (%d:%d:%d)\n",  in intc_irqpin_dbg()
188 		str, i->requested_irq, i->hw_irq, i->domain_irq);  in intc_irqpin_dbg()
196 	intc_irqpin_dbg(&p->irq[hw_irq], "enable");  in intc_irqpin_irq_enable()
205 	intc_irqpin_dbg(&p->irq[hw_irq], "disable");  in intc_irqpin_irq_disable()
214 	intc_irqpin_dbg(&p->irq[hw_irq], "shared enable");  in intc_irqpin_shared_irq_enable()
217 	p->shared_irq_mask &= ~BIT(hw_irq);  in intc_irqpin_shared_irq_enable()
225 	intc_irqpin_dbg(&p->irq[hw_irq], "shared disable");  in intc_irqpin_shared_irq_disable()
228 	p->shared_irq_mask |= BIT(hw_irq);  in intc_irqpin_shared_irq_disable()
234 	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;  in intc_irqpin_irq_enable_force()
239 	 * assumes non-shared interrupt with 1:1 mapping  in intc_irqpin_irq_enable_force()
242 	irq_get_chip(irq)->irq_unmask(irq_get_irq_data(irq));  in intc_irqpin_irq_enable_force()
248 	int irq = p->irq[irqd_to_hwirq(d)].requested_irq;  in intc_irqpin_irq_disable_force()
251 	 * assumes non-shared interrupt with 1:1 mapping  in intc_irqpin_irq_disable_force()
254 	irq_get_chip(irq)->irq_mask(irq_get_irq_data(irq));  in intc_irqpin_irq_disable_force()
275 		return -EINVAL;  in intc_irqpin_irq_set_type()
286 	irq_set_irq_wake(p->irq[hw_irq].requested_irq, on);  in intc_irqpin_irq_set_wake()
288 		atomic_inc(&p->wakeup_path);  in intc_irqpin_irq_set_wake()
290 		atomic_dec(&p->wakeup_path);  in intc_irqpin_irq_set_wake()
298 	struct intc_irqpin_priv *p = i->p;  in intc_irqpin_irq_handler()
302 	bit = intc_irqpin_hwirq_mask(p, INTC_IRQPIN_REG_SOURCE, i->hw_irq);  in intc_irqpin_irq_handler()
307 		generic_handle_irq(i->domain_irq);  in intc_irqpin_irq_handler()
321 		if (reg_source & BIT(7 - k)) {  in intc_irqpin_shared_irq_handler()
322 			if (BIT(k) & p->shared_irq_mask)  in intc_irqpin_shared_irq_handler()
325 			status |= intc_irqpin_irq_handler(irq, &p->irq[k]);  in intc_irqpin_shared_irq_handler()
344 	struct intc_irqpin_priv *p = h->host_data;  in intc_irqpin_irq_domain_map()
346 	p->irq[hw].domain_irq = virq;  in intc_irqpin_irq_domain_map()
347 	p->irq[hw].hw_irq = hw;  in intc_irqpin_irq_domain_map()
349 	intc_irqpin_dbg(&p->irq[hw], "map");  in intc_irqpin_irq_domain_map()
350 	irq_set_chip_data(virq, h->host_data);  in intc_irqpin_irq_domain_map()
353 	irq_set_chip_and_handler(virq, &p->irq_chip, handle_level_irq);  in intc_irqpin_irq_domain_map()
372 	{ .compatible = "renesas,intc-irqpin", },
373 	{ .compatible = "renesas,intc-irqpin-r8a7778",
375 	{ .compatible = "renesas,intc-irqpin-r8a7779",
377 	{ .compatible = "renesas,intc-irqpin-r8a7740",
379 	{ .compatible = "renesas,intc-irqpin-sh73a0",
388 	struct device *dev = &pdev->dev;  in intc_irqpin_probe()
406 		return -ENOMEM;  in intc_irqpin_probe()
410 	of_property_read_u32(dev->of_node, "sense-bitfield-width",  in intc_irqpin_probe()
411 			     &p->sense_bitfield_width);  in intc_irqpin_probe()
412 	control_parent = of_property_read_bool(dev->of_node, "control-parent");  in intc_irqpin_probe()
413 	if (!p->sense_bitfield_width)  in intc_irqpin_probe()
414 		p->sense_bitfield_width = 4; /* default to 4 bits */  in intc_irqpin_probe()
416 	p->pdev = pdev;  in intc_irqpin_probe()
430 			ret = -EINVAL;  in intc_irqpin_probe()
441 		p->irq[k].p = p;  in intc_irqpin_probe()
442 		p->irq[k].requested_irq = irq->start;  in intc_irqpin_probe()
448 		ret = -EINVAL;  in intc_irqpin_probe()
454 		i = &p->iomem[k];  in intc_irqpin_probe()
462 			i->width = 8;  in intc_irqpin_probe()
463 			i->read = intc_irqpin_read8;  in intc_irqpin_probe()
464 			i->write = intc_irqpin_write8;  in intc_irqpin_probe()
467 			i->width = 32;  in intc_irqpin_probe()
468 			i->read = intc_irqpin_read32;  in intc_irqpin_probe()
469 			i->write = intc_irqpin_write32;  in intc_irqpin_probe()
473 			ret = -EINVAL;  in intc_irqpin_probe()
477 		i->iomem = devm_ioremap_nocache(dev, io[k]->start,  in intc_irqpin_probe()
479 		if (!i->iomem) {  in intc_irqpin_probe()
481 			ret = -ENXIO;  in intc_irqpin_probe()
487 	if (config && config->needs_irlm) {  in intc_irqpin_probe()
490 						      config->irlm_bit, 1, 1);  in intc_irqpin_probe()
503 	ref_irq = p->irq[0].requested_irq;  in intc_irqpin_probe()
504 	p->shared_irqs = 1;  in intc_irqpin_probe()
506 		if (ref_irq != p->irq[k].requested_irq) {  in intc_irqpin_probe()
507 			p->shared_irqs = 0;  in intc_irqpin_probe()
516 	} else if (!p->shared_irqs) {  in intc_irqpin_probe()
524 	irq_chip = &p->irq_chip;  in intc_irqpin_probe()
525 	irq_chip->name = name;  in intc_irqpin_probe()
526 	irq_chip->irq_mask = disable_fn;  in intc_irqpin_probe()
527 	irq_chip->irq_unmask = enable_fn;  in intc_irqpin_probe()
528 	irq_chip->irq_set_type = intc_irqpin_irq_set_type;  in intc_irqpin_probe()
529 	irq_chip->irq_set_wake = intc_irqpin_irq_set_wake;  in intc_irqpin_probe()
530 	irq_chip->flags	= IRQCHIP_MASK_ON_SUSPEND;  in intc_irqpin_probe()
532 	p->irq_domain = irq_domain_add_simple(dev->of_node, nirqs, 0,  in intc_irqpin_probe()
534 	if (!p->irq_domain) {  in intc_irqpin_probe()
535 		ret = -ENXIO;  in intc_irqpin_probe()
540 	if (p->shared_irqs) {  in intc_irqpin_probe()
542 		if (devm_request_irq(dev, p->irq[0].requested_irq,  in intc_irqpin_probe()
546 			ret = -ENOENT;  in intc_irqpin_probe()
552 			if (devm_request_irq(dev, p->irq[k].requested_irq,  in intc_irqpin_probe()
554 					     &p->irq[k])) {  in intc_irqpin_probe()
556 				ret = -ENOENT;  in intc_irqpin_probe()
571 	irq_domain_remove(p->irq_domain);  in intc_irqpin_probe()
582 	irq_domain_remove(p->irq_domain);  in intc_irqpin_remove()
583 	pm_runtime_put(&pdev->dev);  in intc_irqpin_remove()
584 	pm_runtime_disable(&pdev->dev);  in intc_irqpin_remove()
592 	if (atomic_read(&p->wakeup_path))  in intc_irqpin_suspend()