Lines Matching +full:irqs +full:- +full:reserved
4 * Copyright (c) 2003-2004 Simtec Electronics
37 #include <mach/regs-irq.h>
38 #include <mach/regs-gpio.h>
41 #include <plat/regs-irqtype.h>
62 * @reg_pending register holding pending irqs
66 * @parent parent controller for ext and sub irqs
67 * @irqs irq-data, always s3c_irq_data[32]
75 struct s3c_irq_data *irqs; member
89 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_mask()
90 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_mask()
95 mask = readl_relaxed(intc->reg_mask); in s3c_irq_mask()
96 mask |= (1UL << irq_data->offset); in s3c_irq_mask()
97 writel_relaxed(mask, intc->reg_mask); in s3c_irq_mask()
100 parent_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c_irq_mask()
106 if ((mask & parent_data->sub_bits) == parent_data->sub_bits) { in s3c_irq_mask()
107 irqno = irq_find_mapping(parent_intc->domain, in s3c_irq_mask()
108 irq_data->parent_irq); in s3c_irq_mask()
117 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_unmask()
118 struct s3c_irq_intc *parent_intc = intc->parent; in s3c_irq_unmask()
122 mask = readl_relaxed(intc->reg_mask); in s3c_irq_unmask()
123 mask &= ~(1UL << irq_data->offset); in s3c_irq_unmask()
124 writel_relaxed(mask, intc->reg_mask); in s3c_irq_unmask()
127 irqno = irq_find_mapping(parent_intc->domain, in s3c_irq_unmask()
128 irq_data->parent_irq); in s3c_irq_unmask()
136 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_ack()
137 unsigned long bitval = 1UL << irq_data->offset; in s3c_irq_ack()
139 writel_relaxed(bitval, intc->reg_pending); in s3c_irq_ack()
140 if (intc->reg_intpnd) in s3c_irq_ack()
141 writel_relaxed(bitval, intc->reg_intpnd); in s3c_irq_ack()
152 irq_set_handler(data->irq, handle_edge_irq); in s3c_irq_type()
156 irq_set_handler(data->irq, handle_level_irq); in s3c_irq_type()
160 return -EINVAL; in s3c_irq_type()
208 return -EINVAL; in s3c_irqext_type_set()
224 if ((data->hwirq >= 4) && (data->hwirq <= 7)) { in s3c_irqext_type()
227 gpcon_offset = (data->hwirq) * 2; in s3c_irqext_type()
228 extint_offset = (data->hwirq) * 4; in s3c_irqext_type()
229 } else if ((data->hwirq >= 8) && (data->hwirq <= 15)) { in s3c_irqext_type()
232 gpcon_offset = (data->hwirq - 8) * 2; in s3c_irqext_type()
233 extint_offset = (data->hwirq - 8) * 4; in s3c_irqext_type()
234 } else if ((data->hwirq >= 16) && (data->hwirq <= 23)) { in s3c_irqext_type()
237 gpcon_offset = (data->hwirq - 8) * 2; in s3c_irqext_type()
238 extint_offset = (data->hwirq - 16) * 4; in s3c_irqext_type()
240 return -EINVAL; in s3c_irqext_type()
253 if (data->hwirq <= 3) { in s3c_irqext0_type()
256 gpcon_offset = (data->hwirq) * 2; in s3c_irqext0_type()
257 extint_offset = (data->hwirq) * 4; in s3c_irqext0_type()
259 return -EINVAL; in s3c_irqext0_type()
276 .name = "s3c-level",
284 .name = "s3c-ext",
293 .name = "s3c-ext0",
305 struct s3c_irq_intc *intc = irq_data->intc; in s3c_irq_demux()
306 struct s3c_irq_intc *sub_intc = irq_data->sub_intc; in s3c_irq_demux()
310 /* we're using individual domains for the non-dt case in s3c_irq_demux()
314 offset = irq_domain_get_of_node(intc->domain) ? 32 : 0; in s3c_irq_demux()
318 src = readl_relaxed(sub_intc->reg_pending); in s3c_irq_demux()
319 msk = readl_relaxed(sub_intc->reg_mask); in s3c_irq_demux()
322 src &= irq_data->sub_bits; in s3c_irq_demux()
327 irq = irq_find_mapping(sub_intc->domain, offset + n); in s3c_irq_demux()
340 pnd = readl_relaxed(intc->reg_intpnd); in s3c24xx_handle_intc()
344 /* non-dt machines use individual domains */ in s3c24xx_handle_intc()
345 if (!irq_domain_get_of_node(intc->domain)) in s3c24xx_handle_intc()
351 * what looks like the logical-or of the two interrupt numbers. in s3c24xx_handle_intc()
355 offset = readl_relaxed(intc->reg_intpnd + 4); in s3c24xx_handle_intc()
364 handle_domain_irq(intc->domain, intc_offset + offset, regs); in s3c24xx_handle_intc()
385 * s3c24xx_set_fiq - set the FIQ routing
400 offs = irq - FIQ_START; in s3c24xx_set_fiq()
402 return -EINVAL; in s3c24xx_set_fiq()
419 struct s3c_irq_intc *intc = h->host_data; in s3c24xx_irq_map()
420 struct s3c_irq_data *irq_data = &intc->irqs[hw]; in s3c24xx_irq_map()
426 irq_data->intc = intc; in s3c24xx_irq_map()
427 irq_data->offset = hw; in s3c24xx_irq_map()
429 parent_intc = intc->parent; in s3c24xx_irq_map()
432 switch (irq_data->type) { in s3c24xx_irq_map()
447 if (parent_intc || intc->reg_pending == S3C2416_SRCPND2) in s3c24xx_irq_map()
463 pr_err("irq-s3c24xx: unsupported irqtype %d\n", irq_data->type); in s3c24xx_irq_map()
464 return -EINVAL; in s3c24xx_irq_map()
469 if (parent_intc && irq_data->type != S3C_IRQTYPE_NONE) { in s3c24xx_irq_map()
470 if (irq_data->parent_irq > 31) { in s3c24xx_irq_map()
471 pr_err("irq-s3c24xx: parent irq %lu is out of range\n", in s3c24xx_irq_map()
472 irq_data->parent_irq); in s3c24xx_irq_map()
473 return -EINVAL; in s3c24xx_irq_map()
476 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c24xx_irq_map()
477 parent_irq_data->sub_intc = intc; in s3c24xx_irq_map()
478 parent_irq_data->sub_bits |= (1UL << hw); in s3c24xx_irq_map()
481 irqno = irq_find_mapping(parent_intc->domain, in s3c24xx_irq_map()
482 irq_data->parent_irq); in s3c24xx_irq_map()
484 pr_err("irq-s3c24xx: could not find mapping for parent irq %lu\n", in s3c24xx_irq_map()
485 irq_data->parent_irq); in s3c24xx_irq_map()
486 return -EINVAL; in s3c24xx_irq_map()
507 reg_source = intc->reg_intpnd ? intc->reg_intpnd : intc->reg_pending; in s3c24xx_clear_intc()
516 writel_relaxed(pend, intc->reg_pending); in s3c24xx_clear_intc()
517 if (intc->reg_intpnd) in s3c24xx_clear_intc()
518 writel_relaxed(pend, intc->reg_intpnd); in s3c24xx_clear_intc()
538 return ERR_PTR(-ENOMEM); in s3c24xx_init_intc()
540 intc->irqs = irq_data; in s3c24xx_init_intc()
543 intc->parent = parent; in s3c24xx_init_intc()
552 intc->reg_pending = base; in s3c24xx_init_intc()
553 intc->reg_mask = base + 0x08; in s3c24xx_init_intc()
554 intc->reg_intpnd = base + 0x10; in s3c24xx_init_intc()
560 intc->reg_pending = base + 0x18; in s3c24xx_init_intc()
561 intc->reg_mask = base + 0x1c; in s3c24xx_init_intc()
567 intc->reg_pending = base + 0x40; in s3c24xx_init_intc()
568 intc->reg_mask = base + 0x48; in s3c24xx_init_intc()
569 intc->reg_intpnd = base + 0x50; in s3c24xx_init_intc()
577 intc->reg_mask = base + 0xa4; in s3c24xx_init_intc()
578 intc->reg_pending = base + 0xa8; in s3c24xx_init_intc()
584 ret = -EINVAL; in s3c24xx_init_intc()
588 /* now that all the data is complete, init the irq-domain */ in s3c24xx_init_intc()
590 intc->domain = irq_domain_add_legacy(np, irq_num, irq_start, in s3c24xx_init_intc()
593 if (!intc->domain) { in s3c24xx_init_intc()
594 pr_err("irq: could not create irq-domain\n"); in s3c24xx_init_intc()
595 ret = -EINVAL; in s3c24xx_init_intc()
609 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
610 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
611 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
612 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
643 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
661 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
672 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
673 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
674 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
675 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
676 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
677 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
678 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
679 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
680 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
712 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
730 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
768 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
769 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
770 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
771 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
772 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
773 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
774 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
775 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
776 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
814 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
827 { .type = S3C_IRQTYPE_NONE, }, /* reserved */
843 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
844 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
845 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
846 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
847 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
848 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
849 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
850 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
851 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
854 { .type = S3C_IRQTYPE_NONE }, /* reserved */
855 { .type = S3C_IRQTYPE_NONE }, /* reserved */
856 { .type = S3C_IRQTYPE_NONE }, /* reserved */
857 { .type = S3C_IRQTYPE_NONE }, /* reserved */
867 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
868 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
869 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
876 { .type = S3C_IRQTYPE_NONE }, /* reserved */
877 { .type = S3C_IRQTYPE_NONE }, /* reserved */
878 { .type = S3C_IRQTYPE_NONE }, /* reserved */
880 { .type = S3C_IRQTYPE_NONE }, /* reserved */
946 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
947 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
948 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
949 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
950 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
951 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
952 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
953 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
954 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1021 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1022 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1023 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1024 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1025 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1026 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1027 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1028 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1029 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1095 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-RX */
1096 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-TX */
1097 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 28 }, /* UART0-ERR */
1098 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-RX */
1099 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-TX */
1100 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 23 }, /* UART1-ERR */
1101 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-RX */
1102 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-TX */
1103 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 15 }, /* UART2-ERR */
1108 { .type = S3C_IRQTYPE_NONE }, /* reserved */
1119 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-RX */
1120 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-TX */
1121 { .type = S3C_IRQTYPE_LEVEL, .parent_irq = 18 }, /* UART3-ERR */
1154 struct s3c_irq_intc *parent_intc = intc->parent; in s3c24xx_irq_map_of()
1155 struct s3c_irq_data *irq_data = &intc->irqs[intc_hw]; in s3c24xx_irq_map_of()
1158 irq_data->intc = intc; in s3c24xx_irq_map_of()
1159 irq_data->offset = intc_hw; in s3c24xx_irq_map_of()
1186 return -EINVAL; in s3c24xx_irq_xlate_of()
1190 return -EINVAL; in s3c24xx_irq_xlate_of()
1197 parent_intc = intc->parent; in s3c24xx_irq_xlate_of()
1199 irq_data = &intc->irqs[intspec[2]]; in s3c24xx_irq_xlate_of()
1200 irq_data->parent_irq = intspec[1]; in s3c24xx_irq_xlate_of()
1201 parent_irq_data = &parent_intc->irqs[irq_data->parent_irq]; in s3c24xx_irq_xlate_of()
1202 parent_irq_data->sub_intc = intc; in s3c24xx_irq_xlate_of()
1203 parent_irq_data->sub_bits |= (1UL << intspec[2]); in s3c24xx_irq_xlate_of()
1206 irqno = irq_create_mapping(parent_intc->domain, intspec[1]); in s3c24xx_irq_xlate_of()
1243 pr_err("irq-s3c24xx: could not map irq registers\n"); in s3c_init_intc_of()
1244 return -EINVAL; in s3c_init_intc_of()
1250 pr_err("irq: could not create irq-domain\n"); in s3c_init_intc_of()
1251 return -EINVAL; in s3c_init_intc_of()
1257 pr_debug("irq: found controller %s\n", ctrl->name); in s3c_init_intc_of()
1261 return -ENOMEM; in s3c_init_intc_of()
1263 intc->domain = domain; in s3c_init_intc_of()
1264 intc->irqs = kcalloc(32, sizeof(struct s3c_irq_data), in s3c_init_intc_of()
1266 if (!intc->irqs) { in s3c_init_intc_of()
1268 return -ENOMEM; in s3c_init_intc_of()
1271 if (ctrl->parent) { in s3c_init_intc_of()
1272 intc->reg_pending = reg_base + ctrl->offset; in s3c_init_intc_of()
1273 intc->reg_mask = reg_base + ctrl->offset + 0x4; in s3c_init_intc_of()
1275 if (*(ctrl->parent)) { in s3c_init_intc_of()
1276 intc->parent = *(ctrl->parent); in s3c_init_intc_of()
1279 ctrl->name); in s3c_init_intc_of()
1280 kfree(intc->irqs); in s3c_init_intc_of()
1285 intc->reg_pending = reg_base + ctrl->offset; in s3c_init_intc_of()
1286 intc->reg_mask = reg_base + ctrl->offset + 0x08; in s3c_init_intc_of()
1287 intc->reg_intpnd = reg_base + ctrl->offset + 0x10; in s3c_init_intc_of()
1316 IRQCHIP_DECLARE(s3c2410_irq, "samsung,s3c2410-irq", s3c2410_init_intc_of);
1338 IRQCHIP_DECLARE(s3c2416_irq, "samsung,s3c2416-irq", s3c2416_init_intc_of);