1 // SPDX-License-Identifier: GPL-2.0
3  * Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
52 	int pin_out = d->hwirq;  in pdc_enable_intr()
54 	u32 enable;  in pdc_enable_intr()  local
60 	enable = pdc_reg_read(IRQ_ENABLE_BANK, index);  in pdc_enable_intr()
61 	enable = on ? ENABLE_INTR(enable, mask) : CLEAR_INTR(enable, mask);  in pdc_enable_intr()
62 	pdc_reg_write(IRQ_ENABLE_BANK, index, enable);  in pdc_enable_intr()
79  * GIC does not handle falling edge or active low. To allow falling edge and
80  * active low interrupts to be handled at GIC, PDC has an inverter that inverts
81  * falling edge into a rising edge and active low into an active high.
84  * Level sensitive active low    LOW
88  * Level sensitive active High   HIGH
104  * @d: the interrupt data
114 	int pin_out = d->hwirq;  in qcom_pdc_gic_set_type()
138 		return -EINVAL;  in qcom_pdc_gic_set_type()
167 		if (pin >= region->pin_base &&  in get_parent_hwirq()
168 		    pin < region->pin_base + region->cnt)  in get_parent_hwirq()
169 			return (region->parent_base + pin - region->pin_base);  in get_parent_hwirq()
179 	if (is_of_node(fwspec->fwnode)) {  in qcom_pdc_translate()
180 		if (fwspec->param_count != 2)  in qcom_pdc_translate()
181 			return -EINVAL;  in qcom_pdc_translate()
183 		*hwirq = fwspec->param[0];  in qcom_pdc_translate()
184 		*type = fwspec->param[1] & IRQ_TYPE_SENSE_MASK;  in qcom_pdc_translate()
188 	return -EINVAL;  in qcom_pdc_translate()
192 			  unsigned int nr_irqs, void *data)  in qcom_pdc_alloc()  argument
194 	struct irq_fwspec *fwspec = data;  in qcom_pdc_alloc()
202 		return -EINVAL;  in qcom_pdc_alloc()
206 		return -EINVAL;  in qcom_pdc_alloc()
219 	parent_fwspec.fwnode      = domain->parent->fwnode;  in qcom_pdc_alloc()
239 	n = of_property_count_elems_of_size(np, "qcom,pdc-ranges", sizeof(u32));  in pdc_setup_pin_mapping()
241 		return -EINVAL;  in pdc_setup_pin_mapping()
247 		return -ENOMEM;  in pdc_setup_pin_mapping()
251 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
256 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
261 		ret = of_property_read_u32_index(np, "qcom,pdc-ranges",  in pdc_setup_pin_mapping()
279 		return -ENXIO;  in qcom_pdc_init()
285 		ret = -ENXIO;  in qcom_pdc_init()
291 		pr_err("%pOF: failed to init PDC pin-hwirq mapping\n", node);  in qcom_pdc_init()
300 		ret = -ENOMEM;  in qcom_pdc_init()
312 IRQCHIP_DECLARE(pdc_sdm845, "qcom,sdm845-pdc", qcom_pdc_init);