Lines Matching +full:cs +full:- +full:3
3 * low level driver for CCD's hfc-pci based cards
56 {PCI_VENDOR_ID_BERKOM, PCI_DEVICE_ID_BERKOM_T_CONCEPT, "German telekom", "T-Concept"},
64 {PCI_VENDOR_ID_SITECOM, PCI_DEVICE_ID_SITECOM_DC105V2, "Sitecom Europe", "DC-105 ISDN PCI"},
73 release_io_hfcpci(struct IsdnCardState *cs) in release_io_hfcpci() argument
76 cs->hw.hfcpci.pci_io); in release_io_hfcpci()
77 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcpci()
78 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
79 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ in release_io_hfcpci()
81 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ in release_io_hfcpci()
83 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in release_io_hfcpci()
84 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, 0); /* disable memory mapped ports + busmast… in release_io_hfcpci()
85 del_timer(&cs->hw.hfcpci.timer); in release_io_hfcpci()
86 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, in release_io_hfcpci()
87 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); in release_io_hfcpci()
88 cs->hw.hfcpci.fifos = NULL; in release_io_hfcpci()
89 iounmap((void *)cs->hw.hfcpci.pci_io); in release_io_hfcpci()
97 reset_hfcpci(struct IsdnCardState *cs) in reset_hfcpci() argument
99 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped port… in reset_hfcpci()
100 cs->hw.hfcpci.int_m2 = 0; /* interrupt output off ! */ in reset_hfcpci()
101 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
104 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO + PCI_ENA_MASTER); /* enable m… in reset_hfcpci()
105 Write_hfc(cs, HFCPCI_CIRM, HFCPCI_RESET); /* Reset On */ in reset_hfcpci()
107 Write_hfc(cs, HFCPCI_CIRM, 0); /* Reset Off */ in reset_hfcpci()
109 if (Read_hfc(cs, HFCPCI_STATUS) & 2) in reset_hfcpci()
110 printk(KERN_WARNING "HFC-PCI init bit busy\n"); in reset_hfcpci()
112 cs->hw.hfcpci.fifo_en = 0x30; /* only D fifos enabled */ in reset_hfcpci()
113 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in reset_hfcpci()
115 cs->hw.hfcpci.trm = 0 + HFCPCI_BTRANS_THRESMASK; /* no echo connect , threshold */ in reset_hfcpci()
116 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in reset_hfcpci()
118 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_TE); /* ST-Bit delay for TE-Mode */ in reset_hfcpci()
119 cs->hw.hfcpci.sctrl_e = HFCPCI_AUTO_AWAKE; in reset_hfcpci()
120 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); /* S/T Auto awake */ in reset_hfcpci()
121 cs->hw.hfcpci.bswapped = 0; /* no exchange */ in reset_hfcpci()
122 cs->hw.hfcpci.nt_mode = 0; /* we are in TE mode */ in reset_hfcpci()
123 cs->hw.hfcpci.ctmt = HFCPCI_TIM3_125 | HFCPCI_AUTO_TIMER; in reset_hfcpci()
124 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in reset_hfcpci()
126 cs->hw.hfcpci.int_m1 = HFCPCI_INTS_DTRANS | HFCPCI_INTS_DREC | in reset_hfcpci()
128 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in reset_hfcpci()
131 if (Read_hfc(cs, HFCPCI_INT_S1)); in reset_hfcpci()
133 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcpci()
135 Write_hfc(cs, HFCPCI_STATES, 2); /* HFC ST 2 */ in reset_hfcpci()
136 cs->hw.hfcpci.mst_m = HFCPCI_MASTER; /* HFC Master Mode */ in reset_hfcpci()
138 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in reset_hfcpci()
139 cs->hw.hfcpci.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ in reset_hfcpci()
140 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in reset_hfcpci()
141 cs->hw.hfcpci.sctrl_r = 0; in reset_hfcpci()
142 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in reset_hfcpci()
145 /* Slots 0 and 1 are set for B-chan 1 and 2 */ in reset_hfcpci()
146 /* D- and monitor/CI channel are not enabled */ in reset_hfcpci()
147 /* STIO1 is used as output for data, B1+B2 from ST->IOM+HFC */ in reset_hfcpci()
148 /* STIO2 is used as data input, B1+B2 from IOM->ST */ in reset_hfcpci()
149 /* ST B-channel send disabled -> continuous 1s */ in reset_hfcpci()
151 cs->hw.hfcpci.conn = 0x36; /* set data flow directions */ in reset_hfcpci()
152 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in reset_hfcpci()
153 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ in reset_hfcpci()
154 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ in reset_hfcpci()
155 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ in reset_hfcpci()
156 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ in reset_hfcpci()
159 cs->hw.hfcpci.int_m2 = HFCPCI_IRQ_ENABLE; in reset_hfcpci()
160 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in reset_hfcpci()
161 if (Read_hfc(cs, HFCPCI_INT_S1)); in reset_hfcpci()
170 struct IsdnCardState *cs = from_timer(cs, t, hw.hfcpci.timer); in hfcpci_Timer() local
171 cs->hw.hfcpci.timer.expires = jiffies + 75; in hfcpci_Timer()
173 /* WriteReg(cs, HFCD_DATA, HFCD_CTMT, cs->hw.hfcpci.ctmt | 0x80); in hfcpci_Timer()
174 add_timer(&cs->hw.hfcpci.timer); in hfcpci_Timer()
180 /* schedule a new D-channel task */
183 sched_event_D_pci(struct IsdnCardState *cs, int event) in sched_event_D_pci() argument
185 test_and_set_bit(event, &cs->event); in sched_event_D_pci()
186 schedule_work(&cs->tqueue); in sched_event_D_pci()
195 test_and_set_bit(event, &bcs->event); in hfcpci_sched_event()
196 schedule_work(&bcs->tqueue); in hfcpci_sched_event()
200 /* select a b-channel entry matching and active */
204 Sel_BCS(struct IsdnCardState *cs, int channel) in Sel_BCS() argument
206 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) in Sel_BCS()
207 return (&cs->bcs[0]); in Sel_BCS()
208 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) in Sel_BCS()
209 return (&cs->bcs[1]); in Sel_BCS()
215 /* clear the desired B-channel rx fifo */
217 static void hfcpci_clear_fifo_rx(struct IsdnCardState *cs, int fifo) in hfcpci_clear_fifo_rx() argument
222 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in hfcpci_clear_fifo_rx()
223 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2RX; in hfcpci_clear_fifo_rx()
225 bzr = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1; in hfcpci_clear_fifo_rx()
226 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1RX; in hfcpci_clear_fifo_rx()
229 cs->hw.hfcpci.fifo_en ^= fifo_state; in hfcpci_clear_fifo_rx()
230 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
231 cs->hw.hfcpci.last_bfifo_cnt[fifo] = 0; in hfcpci_clear_fifo_rx()
232 bzr->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1; in hfcpci_clear_fifo_rx()
233 bzr->za[MAX_B_FRAMES].z2 = bzr->za[MAX_B_FRAMES].z1; in hfcpci_clear_fifo_rx()
234 bzr->f1 = MAX_B_FRAMES; in hfcpci_clear_fifo_rx()
235 bzr->f2 = bzr->f1; /* init F pointers to remain constant */ in hfcpci_clear_fifo_rx()
237 cs->hw.hfcpci.fifo_en |= fifo_state; in hfcpci_clear_fifo_rx()
238 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_rx()
242 /* clear the desired B-channel tx fifo */
244 static void hfcpci_clear_fifo_tx(struct IsdnCardState *cs, int fifo) in hfcpci_clear_fifo_tx() argument
249 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2; in hfcpci_clear_fifo_tx()
250 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B2TX; in hfcpci_clear_fifo_tx()
252 bzt = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1; in hfcpci_clear_fifo_tx()
253 fifo_state = cs->hw.hfcpci.fifo_en & HFCPCI_FIFOEN_B1TX; in hfcpci_clear_fifo_tx()
256 cs->hw.hfcpci.fifo_en ^= fifo_state; in hfcpci_clear_fifo_tx()
257 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
258 bzt->za[MAX_B_FRAMES].z1 = B_FIFO_SIZE + B_SUB_VAL - 1; in hfcpci_clear_fifo_tx()
259 bzt->za[MAX_B_FRAMES].z2 = bzt->za[MAX_B_FRAMES].z1; in hfcpci_clear_fifo_tx()
260 bzt->f1 = MAX_B_FRAMES; in hfcpci_clear_fifo_tx()
261 bzt->f2 = bzt->f1; /* init F pointers to remain constant */ in hfcpci_clear_fifo_tx()
263 cs->hw.hfcpci.fifo_en |= fifo_state; in hfcpci_clear_fifo_tx()
264 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_clear_fifo_tx()
268 /* read a complete B-frame out of the buffer */
276 struct IsdnCardState *cs = bcs->cs; in hfcpci_empty_fifo() local
280 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) in hfcpci_empty_fifo()
281 debugl1(cs, "hfcpci_empty_fifo"); in hfcpci_empty_fifo()
282 zp = &bz->za[bz->f2]; /* point to Z-Regs */ in hfcpci_empty_fifo()
283 new_z2 = zp->z2 + count; /* new position in fifo */ in hfcpci_empty_fifo()
285 new_z2 -= B_FIFO_SIZE; /* buffer wrap */ in hfcpci_empty_fifo()
286 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES; in hfcpci_empty_fifo()
287 if ((count > HSCX_BUFMAX + 3) || (count < 4) || in hfcpci_empty_fifo()
288 (*(bdata + (zp->z1 - B_SUB_VAL)))) { in hfcpci_empty_fifo()
289 if (cs->debug & L1_DEB_WARN) in hfcpci_empty_fifo()
290 debugl1(cs, "hfcpci_empty_fifo: incoming packet invalid length %d or crc", count); in hfcpci_empty_fifo()
292 bcs->err_inv++; in hfcpci_empty_fifo()
294 bz->za[new_f2].z2 = new_z2; in hfcpci_empty_fifo()
295 bz->f2 = new_f2; /* next buffer */ in hfcpci_empty_fifo()
297 } else if (!(skb = dev_alloc_skb(count - 3))) in hfcpci_empty_fifo()
301 count -= 3; in hfcpci_empty_fifo()
304 if (zp->z2 + count <= B_FIFO_SIZE + B_SUB_VAL) in hfcpci_empty_fifo()
307 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */ in hfcpci_empty_fifo()
309 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */ in hfcpci_empty_fifo()
311 count -= maxlen; in hfcpci_empty_fifo()
318 bz->za[new_f2].z2 = new_z2; in hfcpci_empty_fifo()
319 bz->f2 = new_f2; /* next buffer */ in hfcpci_empty_fifo()
326 /* D-channel receive procedure */
330 receive_dmsg(struct IsdnCardState *cs) in receive_dmsg() argument
340 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_rx; in receive_dmsg()
341 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_dmsg()
342 debugl1(cs, "rec_dmsg blocked"); in receive_dmsg()
345 while (((df->f1 & D_FREG_MASK) != (df->f2 & D_FREG_MASK)) && count--) { in receive_dmsg()
346 zp = &df->za[df->f2 & D_FREG_MASK]; in receive_dmsg()
347 rcnt = zp->z1 - zp->z2; in receive_dmsg()
351 if (cs->debug & L1_DEB_ISAC) in receive_dmsg()
352 debugl1(cs, "hfcpci recd f1(%d) f2(%d) z1(%x) z2(%x) cnt(%d)", in receive_dmsg()
353 df->f1, df->f2, zp->z1, zp->z2, rcnt); in receive_dmsg()
355 if ((rcnt > MAX_DFRAME_LEN + 3) || (rcnt < 4) || in receive_dmsg()
356 (df->data[zp->z1])) { in receive_dmsg()
357 if (cs->debug & L1_DEB_WARN) in receive_dmsg()
358 debugl1(cs, "empty_fifo hfcpci packet inv. len %d or crc %d", rcnt, df->data[zp->z1]); in receive_dmsg()
360 cs->err_rx++; in receive_dmsg()
362 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */ in receive_dmsg()
363 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + rcnt) & (D_FIFO_SIZE - 1); in receive_dmsg()
364 } else if ((skb = dev_alloc_skb(rcnt - 3))) { in receive_dmsg()
366 rcnt -= 3; in receive_dmsg()
369 if (zp->z2 + rcnt <= D_FIFO_SIZE) in receive_dmsg()
372 maxlen = D_FIFO_SIZE - zp->z2; /* maximum */ in receive_dmsg()
374 ptr1 = df->data + zp->z2; /* start of data */ in receive_dmsg()
376 rcnt -= maxlen; in receive_dmsg()
380 ptr1 = df->data; /* start of buffer */ in receive_dmsg()
383 df->f2 = ((df->f2 + 1) & MAX_D_FRAMES) | (MAX_D_FRAMES + 1); /* next buffer */ in receive_dmsg()
384 df->za[df->f2 & D_FREG_MASK].z2 = (zp->z2 + total) & (D_FIFO_SIZE - 1); in receive_dmsg()
386 skb_queue_tail(&cs->rq, skb); in receive_dmsg()
387 sched_event_D_pci(cs, D_RCVBUFREADY); in receive_dmsg()
389 printk(KERN_WARNING "HFC-PCI: D receive out of memory\n"); in receive_dmsg()
391 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_dmsg()
406 z1r = &bz->za[MAX_B_FRAMES].z1; /* pointer to z reg */ in hfcpci_empty_fifo_trans()
409 if (!(fcnt = *z1r - *z2r)) in hfcpci_empty_fifo_trans()
419 new_z2 -= B_FIFO_SIZE; /* buffer wrap */ in hfcpci_empty_fifo_trans()
428 maxlen = B_FIFO_SIZE + B_SUB_VAL - *z2r; /* maximum */ in hfcpci_empty_fifo_trans()
430 ptr1 = bdata + (*z2r - B_SUB_VAL); /* start of data */ in hfcpci_empty_fifo_trans()
432 fcnt -= maxlen; in hfcpci_empty_fifo_trans()
439 skb_queue_tail(&bcs->rqueue, skb); in hfcpci_empty_fifo_trans()
448 /* B-channel main receive routine */
453 struct IsdnCardState *cs = bcs->cs; in main_rec_hfcpci() local
462 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) { in main_rec_hfcpci()
463 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in main_rec_hfcpci()
464 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2; in main_rec_hfcpci()
467 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b1; in main_rec_hfcpci()
468 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b1; in main_rec_hfcpci()
472 count--; in main_rec_hfcpci()
473 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in main_rec_hfcpci()
474 debugl1(cs, "rec_data %d blocked", bcs->channel); in main_rec_hfcpci()
477 if (bz->f1 != bz->f2) { in main_rec_hfcpci()
478 if (cs->debug & L1_DEB_HSCX) in main_rec_hfcpci()
479 debugl1(cs, "hfcpci rec %d f1(%d) f2(%d)", in main_rec_hfcpci()
480 bcs->channel, bz->f1, bz->f2); in main_rec_hfcpci()
481 zp = &bz->za[bz->f2]; in main_rec_hfcpci()
483 rcnt = zp->z1 - zp->z2; in main_rec_hfcpci()
487 if (cs->debug & L1_DEB_HSCX) in main_rec_hfcpci()
488 debugl1(cs, "hfcpci rec %d z1(%x) z2(%x) cnt(%d)", in main_rec_hfcpci()
489 bcs->channel, zp->z1, zp->z2, rcnt); in main_rec_hfcpci()
491 skb_queue_tail(&bcs->rqueue, skb); in main_rec_hfcpci()
494 rcnt = bz->f1 - bz->f2; in main_rec_hfcpci()
497 if (cs->hw.hfcpci.last_bfifo_cnt[real_fifo] > rcnt + 1) { in main_rec_hfcpci()
499 hfcpci_clear_fifo_rx(cs, real_fifo); in main_rec_hfcpci()
501 cs->hw.hfcpci.last_bfifo_cnt[real_fifo] = rcnt; in main_rec_hfcpci()
506 } else if (bcs->mode == L1_MODE_TRANS) in main_rec_hfcpci()
510 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in main_rec_hfcpci()
516 /* D-channel send routine */
519 hfcpci_fill_dfifo(struct IsdnCardState *cs) in hfcpci_fill_dfifo() argument
526 if (!cs->tx_skb) in hfcpci_fill_dfifo()
528 if (cs->tx_skb->len <= 0) in hfcpci_fill_dfifo()
531 df = &((fifo_area *) (cs->hw.hfcpci.fifos))->d_chan.d_tx; in hfcpci_fill_dfifo()
533 if (cs->debug & L1_DEB_ISAC) in hfcpci_fill_dfifo()
534 debugl1(cs, "hfcpci_fill_Dfifo f1(%d) f2(%d) z1(f1)(%x)", in hfcpci_fill_dfifo()
535 df->f1, df->f2, in hfcpci_fill_dfifo()
536 df->za[df->f1 & D_FREG_MASK].z1); in hfcpci_fill_dfifo()
537 fcnt = df->f1 - df->f2; /* frame count actually buffered */ in hfcpci_fill_dfifo()
540 if (fcnt > (MAX_D_FRAMES - 1)) { in hfcpci_fill_dfifo()
541 if (cs->debug & L1_DEB_ISAC) in hfcpci_fill_dfifo()
542 debugl1(cs, "hfcpci_fill_Dfifo more as 14 frames"); in hfcpci_fill_dfifo()
544 cs->err_tx++; in hfcpci_fill_dfifo()
549 count = df->za[df->f2 & D_FREG_MASK].z2 - df->za[df->f1 & D_FREG_MASK].z1 - 1; in hfcpci_fill_dfifo()
553 if (cs->debug & L1_DEB_ISAC) in hfcpci_fill_dfifo()
554 debugl1(cs, "hfcpci_fill_Dfifo count(%u/%d)", in hfcpci_fill_dfifo()
555 cs->tx_skb->len, count); in hfcpci_fill_dfifo()
556 if (count < cs->tx_skb->len) { in hfcpci_fill_dfifo()
557 if (cs->debug & L1_DEB_ISAC) in hfcpci_fill_dfifo()
558 debugl1(cs, "hfcpci_fill_Dfifo no fifo mem"); in hfcpci_fill_dfifo()
561 count = cs->tx_skb->len; /* get frame len */ in hfcpci_fill_dfifo()
562 new_z1 = (df->za[df->f1 & D_FREG_MASK].z1 + count) & (D_FIFO_SIZE - 1); in hfcpci_fill_dfifo()
563 new_f1 = ((df->f1 + 1) & D_FREG_MASK) | (D_FREG_MASK + 1); in hfcpci_fill_dfifo()
564 src = cs->tx_skb->data; /* source pointer */ in hfcpci_fill_dfifo()
565 dst = df->data + df->za[df->f1 & D_FREG_MASK].z1; in hfcpci_fill_dfifo()
566 maxlen = D_FIFO_SIZE - df->za[df->f1 & D_FREG_MASK].z1; /* end fifo */ in hfcpci_fill_dfifo()
571 count -= maxlen; /* remaining bytes */ in hfcpci_fill_dfifo()
573 dst = df->data; /* start of buffer */ in hfcpci_fill_dfifo()
577 df->za[new_f1 & D_FREG_MASK].z1 = new_z1; /* for next buffer */ in hfcpci_fill_dfifo()
578 df->za[df->f1 & D_FREG_MASK].z1 = new_z1; /* new pos actual buffer */ in hfcpci_fill_dfifo()
579 df->f1 = new_f1; /* next frame */ in hfcpci_fill_dfifo()
581 dev_kfree_skb_any(cs->tx_skb); in hfcpci_fill_dfifo()
582 cs->tx_skb = NULL; in hfcpci_fill_dfifo()
586 /* B-channel send routine */
591 struct IsdnCardState *cs = bcs->cs; in hfcpci_fill_fifo() local
599 if (!bcs->tx_skb) in hfcpci_fill_fifo()
601 if (bcs->tx_skb->len <= 0) in hfcpci_fill_fifo()
604 if ((bcs->channel) && (!cs->hw.hfcpci.bswapped)) { in hfcpci_fill_fifo()
605 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b2; in hfcpci_fill_fifo()
606 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b2; in hfcpci_fill_fifo()
608 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txbz_b1; in hfcpci_fill_fifo()
609 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.txdat_b1; in hfcpci_fill_fifo()
612 if (bcs->mode == L1_MODE_TRANS) { in hfcpci_fill_fifo()
613 z1t = &bz->za[MAX_B_FRAMES].z1; in hfcpci_fill_fifo()
615 if (cs->debug & L1_DEB_HSCX) in hfcpci_fill_fifo()
616 debugl1(cs, "hfcpci_fill_fifo_trans %d z1(%x) z2(%x)", in hfcpci_fill_fifo()
617 bcs->channel, *z1t, *z2t); in hfcpci_fill_fifo()
618 fcnt = *z2t - *z1t; in hfcpci_fill_fifo()
621 fcnt = B_FIFO_SIZE - fcnt; /* remaining bytes to send */ in hfcpci_fill_fifo()
623 while ((fcnt < 2 * HFCPCI_BTRANS_THRESHOLD) && (bcs->tx_skb)) { in hfcpci_fill_fifo()
624 if (bcs->tx_skb->len < B_FIFO_SIZE - fcnt) { in hfcpci_fill_fifo()
626 count = bcs->tx_skb->len; in hfcpci_fill_fifo()
630 new_z1 -= B_FIFO_SIZE; /* buffer wrap */ in hfcpci_fill_fifo()
631 src = bcs->tx_skb->data; /* source pointer */ in hfcpci_fill_fifo()
632 dst = bdata + (*z1t - B_SUB_VAL); in hfcpci_fill_fifo()
633 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - *z1t; /* end of fifo */ in hfcpci_fill_fifo()
638 count -= maxlen; /* remaining bytes */ in hfcpci_fill_fifo()
644 bcs->tx_cnt -= bcs->tx_skb->len; in hfcpci_fill_fifo()
645 fcnt += bcs->tx_skb->len; in hfcpci_fill_fifo()
647 } else if (cs->debug & L1_DEB_HSCX) in hfcpci_fill_fifo()
648 debugl1(cs, "hfcpci_fill_fifo_trans %d frame length %d discarded", in hfcpci_fill_fifo()
649 bcs->channel, bcs->tx_skb->len); in hfcpci_fill_fifo()
651 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) && in hfcpci_fill_fifo()
652 (PACKET_NOACK != bcs->tx_skb->pkt_type)) { in hfcpci_fill_fifo()
654 spin_lock_irqsave(&bcs->aclock, flags); in hfcpci_fill_fifo()
655 bcs->ackcnt += bcs->tx_skb->len; in hfcpci_fill_fifo()
656 spin_unlock_irqrestore(&bcs->aclock, flags); in hfcpci_fill_fifo()
660 dev_kfree_skb_any(bcs->tx_skb); in hfcpci_fill_fifo()
661 bcs->tx_skb = skb_dequeue(&bcs->squeue); /* fetch next data */ in hfcpci_fill_fifo()
663 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); in hfcpci_fill_fifo()
666 if (cs->debug & L1_DEB_HSCX) in hfcpci_fill_fifo()
667 debugl1(cs, "hfcpci_fill_fifo_hdlc %d f1(%d) f2(%d) z1(f1)(%x)", in hfcpci_fill_fifo()
668 bcs->channel, bz->f1, bz->f2, in hfcpci_fill_fifo()
669 bz->za[bz->f1].z1); in hfcpci_fill_fifo()
671 fcnt = bz->f1 - bz->f2; /* frame count actually buffered */ in hfcpci_fill_fifo()
674 if (fcnt > (MAX_B_FRAMES - 1)) { in hfcpci_fill_fifo()
675 if (cs->debug & L1_DEB_HSCX) in hfcpci_fill_fifo()
676 debugl1(cs, "hfcpci_fill_Bfifo more as 14 frames"); in hfcpci_fill_fifo()
680 count = bz->za[bz->f2].z2 - bz->za[bz->f1].z1 - 1; in hfcpci_fill_fifo()
684 if (cs->debug & L1_DEB_HSCX) in hfcpci_fill_fifo()
685 debugl1(cs, "hfcpci_fill_fifo %d count(%u/%d),%lx", in hfcpci_fill_fifo()
686 bcs->channel, bcs->tx_skb->len, in hfcpci_fill_fifo()
687 count, current->state); in hfcpci_fill_fifo()
689 if (count < bcs->tx_skb->len) { in hfcpci_fill_fifo()
690 if (cs->debug & L1_DEB_HSCX) in hfcpci_fill_fifo()
691 debugl1(cs, "hfcpci_fill_fifo no fifo mem"); in hfcpci_fill_fifo()
694 count = bcs->tx_skb->len; /* get frame len */ in hfcpci_fill_fifo()
695 new_z1 = bz->za[bz->f1].z1 + count; /* new buffer Position */ in hfcpci_fill_fifo()
697 new_z1 -= B_FIFO_SIZE; /* buffer wrap */ in hfcpci_fill_fifo()
699 new_f1 = ((bz->f1 + 1) & MAX_B_FRAMES); in hfcpci_fill_fifo()
700 src = bcs->tx_skb->data; /* source pointer */ in hfcpci_fill_fifo()
701 dst = bdata + (bz->za[bz->f1].z1 - B_SUB_VAL); in hfcpci_fill_fifo()
702 maxlen = (B_FIFO_SIZE + B_SUB_VAL) - bz->za[bz->f1].z1; /* end fifo */ in hfcpci_fill_fifo()
707 count -= maxlen; /* remaining bytes */ in hfcpci_fill_fifo()
713 bcs->tx_cnt -= bcs->tx_skb->len; in hfcpci_fill_fifo()
714 if (test_bit(FLG_LLI_L1WAKEUP, &bcs->st->lli.flag) && in hfcpci_fill_fifo()
715 (PACKET_NOACK != bcs->tx_skb->pkt_type)) { in hfcpci_fill_fifo()
717 spin_lock_irqsave(&bcs->aclock, flags); in hfcpci_fill_fifo()
718 bcs->ackcnt += bcs->tx_skb->len; in hfcpci_fill_fifo()
719 spin_unlock_irqrestore(&bcs->aclock, flags); in hfcpci_fill_fifo()
723 bz->za[new_f1].z1 = new_z1; /* for next buffer */ in hfcpci_fill_fifo()
724 bz->f1 = new_f1; /* next frame */ in hfcpci_fill_fifo()
726 dev_kfree_skb_any(bcs->tx_skb); in hfcpci_fill_fifo()
727 bcs->tx_skb = NULL; in hfcpci_fill_fifo()
728 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); in hfcpci_fill_fifo()
732 /* D-channel l1 state call for leased NT-mode */
737 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in dch_nt_l2l1() local
743 st->l1.l1hw(st, pr, arg); in dch_nt_l2l1()
746 st->l1.l1l2(st, PH_ACTIVATE | CONFIRM, NULL); in dch_nt_l2l1()
750 debugl1(cs, "PH_TEST_LOOP B1"); in dch_nt_l2l1()
752 debugl1(cs, "PH_TEST_LOOP B2"); in dch_nt_l2l1()
753 if (!(3 & (long) arg)) in dch_nt_l2l1()
754 debugl1(cs, "PH_TEST_LOOP DISABLED"); in dch_nt_l2l1()
755 st->l1.l1hw(st, HW_TESTLOOP | REQUEST, arg); in dch_nt_l2l1()
758 if (cs->debug) in dch_nt_l2l1()
759 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr); in dch_nt_l2l1()
770 hfcpci_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) in hfcpci_auxcmd() argument
773 int i = *(unsigned int *) ic->parm.num; in hfcpci_auxcmd()
775 if ((ic->arg == 98) && in hfcpci_auxcmd()
776 …(!(cs->hw.hfcpci.int_m1 & (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC + HFCPCI_INTS_B1TRANS + HFCPCI_… in hfcpci_auxcmd()
777 spin_lock_irqsave(&cs->lock, flags); in hfcpci_auxcmd()
778 Write_hfc(cs, HFCPCI_CLKDEL, CLKDEL_NT); /* ST-Bit delay for NT-Mode */ in hfcpci_auxcmd()
779 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 0); /* HFC ST G0 */ in hfcpci_auxcmd()
781 cs->hw.hfcpci.sctrl |= SCTRL_MODE_NT; in hfcpci_auxcmd()
782 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); /* set NT-mode */ in hfcpci_auxcmd()
784 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 1); /* HFC ST G1 */ in hfcpci_auxcmd()
786 Write_hfc(cs, HFCPCI_STATES, 1 | HFCPCI_ACTIVATE | HFCPCI_DO_ACTION); in hfcpci_auxcmd()
787 cs->dc.hfcpci.ph_state = 1; in hfcpci_auxcmd()
788 cs->hw.hfcpci.nt_mode = 1; in hfcpci_auxcmd()
789 cs->hw.hfcpci.nt_timer = 0; in hfcpci_auxcmd()
790 cs->stlist->l2.l2l1 = dch_nt_l2l1; in hfcpci_auxcmd()
791 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_auxcmd()
792 debugl1(cs, "NT mode activated"); in hfcpci_auxcmd()
795 if ((cs->chanlimit > 1) || (cs->hw.hfcpci.bswapped) || in hfcpci_auxcmd()
796 (cs->hw.hfcpci.nt_mode) || (ic->arg != 12)) in hfcpci_auxcmd()
797 return (-EINVAL); in hfcpci_auxcmd()
799 spin_lock_irqsave(&cs->lock, flags); in hfcpci_auxcmd()
801 cs->logecho = 1; in hfcpci_auxcmd()
802 cs->hw.hfcpci.trm |= 0x20; /* enable echo chan */ in hfcpci_auxcmd()
803 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_B2REC; in hfcpci_auxcmd()
804 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2RX; in hfcpci_auxcmd()
806 cs->logecho = 0; in hfcpci_auxcmd()
807 cs->hw.hfcpci.trm &= ~0x20; /* disable echo chan */ in hfcpci_auxcmd()
808 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_B2REC; in hfcpci_auxcmd()
809 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2RX; in hfcpci_auxcmd()
811 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA; in hfcpci_auxcmd()
812 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA; in hfcpci_auxcmd()
813 cs->hw.hfcpci.conn |= 0x10; /* B2-IOM -> B2-ST */ in hfcpci_auxcmd()
814 cs->hw.hfcpci.ctmt &= ~2; in hfcpci_auxcmd()
815 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in hfcpci_auxcmd()
816 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in hfcpci_auxcmd()
817 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in hfcpci_auxcmd()
818 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in hfcpci_auxcmd()
819 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in hfcpci_auxcmd()
820 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in hfcpci_auxcmd()
821 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_auxcmd()
822 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_auxcmd()
827 /* E-channel receive routine */
830 receive_emsg(struct IsdnCardState *cs) in receive_emsg() argument
841 bz = &((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxbz_b2; in receive_emsg()
842 bdata = ((fifo_area *) (cs->hw.hfcpci.fifos))->b_chans.rxdat_b2; in receive_emsg()
844 count--; in receive_emsg()
845 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_emsg()
846 debugl1(cs, "echo_rec_data blocked"); in receive_emsg()
849 if (bz->f1 != bz->f2) { in receive_emsg()
850 if (cs->debug & L1_DEB_ISAC) in receive_emsg()
851 debugl1(cs, "hfcpci e_rec f1(%d) f2(%d)", in receive_emsg()
852 bz->f1, bz->f2); in receive_emsg()
853 zp = &bz->za[bz->f2]; in receive_emsg()
855 rcnt = zp->z1 - zp->z2; in receive_emsg()
859 if (cs->debug & L1_DEB_ISAC) in receive_emsg()
860 debugl1(cs, "hfcpci e_rec z1(%x) z2(%x) cnt(%d)", in receive_emsg()
861 zp->z1, zp->z2, rcnt); in receive_emsg()
862 new_z2 = zp->z2 + rcnt; /* new position in fifo */ in receive_emsg()
864 new_z2 -= B_FIFO_SIZE; /* buffer wrap */ in receive_emsg()
865 new_f2 = (bz->f2 + 1) & MAX_B_FRAMES; in receive_emsg()
866 if ((rcnt > 256 + 3) || (count < 4) || in receive_emsg()
867 (*(bdata + (zp->z1 - B_SUB_VAL)))) { in receive_emsg()
868 if (cs->debug & L1_DEB_WARN) in receive_emsg()
869 debugl1(cs, "hfcpci_empty_echan: incoming packet invalid length %d or crc", rcnt); in receive_emsg()
870 bz->za[new_f2].z2 = new_z2; in receive_emsg()
871 bz->f2 = new_f2; /* next buffer */ in receive_emsg()
874 rcnt -= 3; in receive_emsg()
877 if (zp->z2 <= B_FIFO_SIZE + B_SUB_VAL) in receive_emsg()
880 maxlen = B_FIFO_SIZE + B_SUB_VAL - zp->z2; /* maximum */ in receive_emsg()
882 ptr1 = bdata + (zp->z2 - B_SUB_VAL); /* start of data */ in receive_emsg()
884 rcnt -= maxlen; in receive_emsg()
891 bz->za[new_f2].z2 = new_z2; in receive_emsg()
892 bz->f2 = new_f2; /* next buffer */ in receive_emsg()
893 if (cs->debug & DEB_DLOG_HEX) { in receive_emsg()
894 ptr = cs->dlog; in receive_emsg()
895 if ((total - 3) < MAX_DLOG_SPACE / 3 - 10) { in receive_emsg()
901 ptr += QuickHex(ptr, e_buffer, total - 3); in receive_emsg()
902 ptr--; in receive_emsg()
905 HiSax_putstatus(cs, NULL, cs->dlog); in receive_emsg()
907 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", total - 3); in receive_emsg()
911 rcnt = bz->f1 - bz->f2; in receive_emsg()
920 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_emsg()
932 struct IsdnCardState *cs = dev_id; in hfcpci_interrupt() local
938 if (!(cs->hw.hfcpci.int_m2 & 0x08)) { in hfcpci_interrupt()
939 debugl1(cs, "HFC-PCI: int_m2 %x not initialised", cs->hw.hfcpci.int_m2); in hfcpci_interrupt()
942 spin_lock_irqsave(&cs->lock, flags); in hfcpci_interrupt()
943 if (HFCPCI_ANYINT & (stat = Read_hfc(cs, HFCPCI_STATUS))) { in hfcpci_interrupt()
944 val = Read_hfc(cs, HFCPCI_INT_S1); in hfcpci_interrupt()
945 if (cs->debug & L1_DEB_ISAC) in hfcpci_interrupt()
946 debugl1(cs, "HFC-PCI: stat(%02x) s1(%02x)", stat, val); in hfcpci_interrupt()
948 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_interrupt()
951 if (cs->debug & L1_DEB_ISAC) in hfcpci_interrupt()
952 debugl1(cs, "HFC-PCI irq %x %s", val, in hfcpci_interrupt()
953 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? in hfcpci_interrupt()
955 val &= cs->hw.hfcpci.int_m1; in hfcpci_interrupt()
957 exval = Read_hfc(cs, HFCPCI_STATES) & 0xf; in hfcpci_interrupt()
958 if (cs->debug & L1_DEB_ISAC) in hfcpci_interrupt()
959 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcpci.ph_state, in hfcpci_interrupt()
961 cs->dc.hfcpci.ph_state = exval; in hfcpci_interrupt()
962 sched_event_D_pci(cs, D_L1STATECHANGE); in hfcpci_interrupt()
966 if (cs->hw.hfcpci.nt_mode) { in hfcpci_interrupt()
967 if ((--cs->hw.hfcpci.nt_timer) < 0) in hfcpci_interrupt()
968 sched_event_D_pci(cs, D_L1STATECHANGE); in hfcpci_interrupt()
971 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_interrupt()
974 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcpci_interrupt()
975 cs->hw.hfcpci.int_s1 |= val; in hfcpci_interrupt()
976 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_interrupt()
979 if (cs->hw.hfcpci.int_s1 & 0x18) { in hfcpci_interrupt()
981 val = cs->hw.hfcpci.int_s1; in hfcpci_interrupt()
982 cs->hw.hfcpci.int_s1 = exval; in hfcpci_interrupt()
985 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) { in hfcpci_interrupt()
986 if (cs->debug) in hfcpci_interrupt()
987 debugl1(cs, "hfcpci spurious 0x08 IRQ"); in hfcpci_interrupt()
992 if (cs->logecho) in hfcpci_interrupt()
993 receive_emsg(cs); in hfcpci_interrupt()
994 else if (!(bcs = Sel_BCS(cs, 1))) { in hfcpci_interrupt()
995 if (cs->debug) in hfcpci_interrupt()
996 debugl1(cs, "hfcpci spurious 0x10 IRQ"); in hfcpci_interrupt()
1001 if (!(bcs = Sel_BCS(cs, cs->hw.hfcpci.bswapped ? 1 : 0))) { in hfcpci_interrupt()
1002 if (cs->debug) in hfcpci_interrupt()
1003 debugl1(cs, "hfcpci spurious 0x01 IRQ"); in hfcpci_interrupt()
1005 if (bcs->tx_skb) { in hfcpci_interrupt()
1006 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcpci_interrupt()
1008 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcpci_interrupt()
1010 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcpci_interrupt()
1012 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) { in hfcpci_interrupt()
1013 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcpci_interrupt()
1015 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcpci_interrupt()
1017 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcpci_interrupt()
1025 if (!(bcs = Sel_BCS(cs, 1))) { in hfcpci_interrupt()
1026 if (cs->debug) in hfcpci_interrupt()
1027 debugl1(cs, "hfcpci spurious 0x02 IRQ"); in hfcpci_interrupt()
1029 if (bcs->tx_skb) { in hfcpci_interrupt()
1030 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcpci_interrupt()
1032 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcpci_interrupt()
1034 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcpci_interrupt()
1036 if ((bcs->tx_skb = skb_dequeue(&bcs->squeue))) { in hfcpci_interrupt()
1037 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcpci_interrupt()
1039 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcpci_interrupt()
1041 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcpci_interrupt()
1049 receive_dmsg(cs); in hfcpci_interrupt()
1052 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in hfcpci_interrupt()
1053 del_timer(&cs->dbusytimer); in hfcpci_interrupt()
1054 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in hfcpci_interrupt()
1055 sched_event_D_pci(cs, D_CLEARBUSY); in hfcpci_interrupt()
1056 if (cs->tx_skb) { in hfcpci_interrupt()
1057 if (cs->tx_skb->len) { in hfcpci_interrupt()
1058 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcpci_interrupt()
1059 hfcpci_fill_dfifo(cs); in hfcpci_interrupt()
1060 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcpci_interrupt()
1062 debugl1(cs, "hfcpci_fill_dfifo irq blocked"); in hfcpci_interrupt()
1066 dev_kfree_skb_irq(cs->tx_skb); in hfcpci_interrupt()
1067 cs->tx_cnt = 0; in hfcpci_interrupt()
1068 cs->tx_skb = NULL; in hfcpci_interrupt()
1071 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { in hfcpci_interrupt()
1072 cs->tx_cnt = 0; in hfcpci_interrupt()
1073 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcpci_interrupt()
1074 hfcpci_fill_dfifo(cs); in hfcpci_interrupt()
1075 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcpci_interrupt()
1077 debugl1(cs, "hfcpci_fill_dfifo irq blocked"); in hfcpci_interrupt()
1080 sched_event_D_pci(cs, D_XMTBUFREADY); in hfcpci_interrupt()
1083 if (cs->hw.hfcpci.int_s1 && count--) { in hfcpci_interrupt()
1084 val = cs->hw.hfcpci.int_s1; in hfcpci_interrupt()
1085 cs->hw.hfcpci.int_s1 = 0; in hfcpci_interrupt()
1086 if (cs->debug & L1_DEB_ISAC) in hfcpci_interrupt()
1087 debugl1(cs, "HFC-PCI irq %x loop %d", val, 15 - count); in hfcpci_interrupt()
1091 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_interrupt()
1096 /* timer callback for D-chan busy resolution. Currently no function */
1104 /* Layer 1 D-channel hardware access */
1110 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in HFCPCI_l1hw() local
1115 if (cs->debug & DEB_DLOG_HEX) in HFCPCI_l1hw()
1116 LogFrame(cs, skb->data, skb->len); in HFCPCI_l1hw()
1117 if (cs->debug & DEB_DLOG_VERBOSE) in HFCPCI_l1hw()
1118 dlogframe(cs, skb, 0); in HFCPCI_l1hw()
1119 spin_lock_irqsave(&cs->lock, flags); in HFCPCI_l1hw()
1120 if (cs->tx_skb) { in HFCPCI_l1hw()
1121 skb_queue_tail(&cs->sq, skb); in HFCPCI_l1hw()
1123 if (cs->debug & L1_DEB_LAPD) in HFCPCI_l1hw()
1124 Logl2Frame(cs, skb, "PH_DATA Queued", 0); in HFCPCI_l1hw()
1127 cs->tx_skb = skb; in HFCPCI_l1hw()
1128 cs->tx_cnt = 0; in HFCPCI_l1hw()
1130 if (cs->debug & L1_DEB_LAPD) in HFCPCI_l1hw()
1131 Logl2Frame(cs, skb, "PH_DATA", 0); in HFCPCI_l1hw()
1133 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCPCI_l1hw()
1134 hfcpci_fill_dfifo(cs); in HFCPCI_l1hw()
1135 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCPCI_l1hw()
1137 debugl1(cs, "hfcpci_fill_dfifo blocked"); in HFCPCI_l1hw()
1140 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1143 spin_lock_irqsave(&cs->lock, flags); in HFCPCI_l1hw()
1144 if (cs->tx_skb) { in HFCPCI_l1hw()
1145 if (cs->debug & L1_DEB_WARN) in HFCPCI_l1hw()
1146 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); in HFCPCI_l1hw()
1147 skb_queue_tail(&cs->sq, skb); in HFCPCI_l1hw()
1148 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1151 if (cs->debug & DEB_DLOG_HEX) in HFCPCI_l1hw()
1152 LogFrame(cs, skb->data, skb->len); in HFCPCI_l1hw()
1153 if (cs->debug & DEB_DLOG_VERBOSE) in HFCPCI_l1hw()
1154 dlogframe(cs, skb, 0); in HFCPCI_l1hw()
1155 cs->tx_skb = skb; in HFCPCI_l1hw()
1156 cs->tx_cnt = 0; in HFCPCI_l1hw()
1158 if (cs->debug & L1_DEB_LAPD) in HFCPCI_l1hw()
1159 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); in HFCPCI_l1hw()
1161 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCPCI_l1hw()
1162 hfcpci_fill_dfifo(cs); in HFCPCI_l1hw()
1163 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCPCI_l1hw()
1165 debugl1(cs, "hfcpci_fill_dfifo blocked"); in HFCPCI_l1hw()
1166 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1170 if (cs->debug & L1_DEB_LAPD) in HFCPCI_l1hw()
1171 debugl1(cs, "-> PH_REQUEST_PULL"); in HFCPCI_l1hw()
1173 spin_lock_irqsave(&cs->lock, flags); in HFCPCI_l1hw()
1174 if (!cs->tx_skb) { in HFCPCI_l1hw()
1175 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); in HFCPCI_l1hw()
1176 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); in HFCPCI_l1hw()
1178 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); in HFCPCI_l1hw()
1179 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1182 spin_lock_irqsave(&cs->lock, flags); in HFCPCI_l1hw()
1183 Write_hfc(cs, HFCPCI_STATES, HFCPCI_LOAD_STATE | 3); /* HFC ST 3 */ in HFCPCI_l1hw()
1185 Write_hfc(cs, HFCPCI_STATES, 3); /* HFC ST 2 */ in HFCPCI_l1hw()
1186 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER; in HFCPCI_l1hw()
1187 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1188 Write_hfc(cs, HFCPCI_STATES, HFCPCI_ACTIVATE | HFCPCI_DO_ACTION); in HFCPCI_l1hw()
1189 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1190 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); in HFCPCI_l1hw()
1193 spin_lock_irqsave(&cs->lock, flags); in HFCPCI_l1hw()
1194 Write_hfc(cs, HFCPCI_STATES, HFCPCI_DO_ACTION); in HFCPCI_l1hw()
1195 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1198 spin_lock_irqsave(&cs->lock, flags); in HFCPCI_l1hw()
1199 cs->hw.hfcpci.mst_m &= ~HFCPCI_MASTER; in HFCPCI_l1hw()
1200 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1201 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1204 spin_lock_irqsave(&cs->lock, flags); in HFCPCI_l1hw()
1205 cs->hw.hfcpci.mst_m |= HFCPCI_MASTER; in HFCPCI_l1hw()
1206 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in HFCPCI_l1hw()
1207 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1210 spin_lock_irqsave(&cs->lock, flags); in HFCPCI_l1hw()
1213 Write_hfc(cs, HFCPCI_B1_SSL, 0x80); /* tx slot */ in HFCPCI_l1hw()
1214 Write_hfc(cs, HFCPCI_B1_RSL, 0x80); /* rx slot */ in HFCPCI_l1hw()
1215 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~7) | 1; in HFCPCI_l1hw()
1216 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1220 Write_hfc(cs, HFCPCI_B2_SSL, 0x81); /* tx slot */ in HFCPCI_l1hw()
1221 Write_hfc(cs, HFCPCI_B2_RSL, 0x81); /* rx slot */ in HFCPCI_l1hw()
1222 cs->hw.hfcpci.conn = (cs->hw.hfcpci.conn & ~0x38) | 0x08; in HFCPCI_l1hw()
1223 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in HFCPCI_l1hw()
1227 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1228 if (cs->debug & L1_DEB_WARN) in HFCPCI_l1hw()
1229 debugl1(cs, "hfcpci_l1hw loop invalid %4lx", (long) arg); in HFCPCI_l1hw()
1232 cs->hw.hfcpci.trm |= 0x80; /* enable IOM-loop */ in HFCPCI_l1hw()
1233 Write_hfc(cs, HFCPCI_TRM, cs->hw.hfcpci.trm); in HFCPCI_l1hw()
1234 spin_unlock_irqrestore(&cs->lock, flags); in HFCPCI_l1hw()
1237 if (cs->debug & L1_DEB_WARN) in HFCPCI_l1hw()
1238 debugl1(cs, "hfcpci_l1hw unknown pr %4x", pr); in HFCPCI_l1hw()
1247 setstack_hfcpci(struct PStack *st, struct IsdnCardState *cs) in setstack_hfcpci() argument
1249 st->l1.l1hw = HFCPCI_l1hw; in setstack_hfcpci()
1253 /* send B-channel data if not blocked */
1258 struct IsdnCardState *cs = bcs->cs; in hfcpci_send_data() local
1260 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcpci_send_data()
1262 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcpci_send_data()
1264 debugl1(cs, "send_data %d blocked", bcs->channel); in hfcpci_send_data()
1273 struct IsdnCardState *cs = bcs->cs; in mode_hfcpci() local
1276 if (cs->debug & L1_DEB_HSCX) in mode_hfcpci()
1277 debugl1(cs, "HFCPCI bchannel mode %d bchan %d/%d", in mode_hfcpci()
1278 mode, bc, bcs->channel); in mode_hfcpci()
1279 bcs->mode = mode; in mode_hfcpci()
1280 bcs->channel = bc; in mode_hfcpci()
1282 if (cs->chanlimit > 1) { in mode_hfcpci()
1283 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1284 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1288 cs->hw.hfcpci.bswapped = 1; /* B1 and B2 exchanged */ in mode_hfcpci()
1289 cs->hw.hfcpci.sctrl_e |= 0x80; in mode_hfcpci()
1291 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1292 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1296 cs->hw.hfcpci.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcpci()
1297 cs->hw.hfcpci.sctrl_e &= ~0x80; in mode_hfcpci()
1303 cs->hw.hfcpci.sctrl &= ~SCTRL_B2_ENA; in mode_hfcpci()
1304 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B2_ENA; in mode_hfcpci()
1306 cs->hw.hfcpci.sctrl &= ~SCTRL_B1_ENA; in mode_hfcpci()
1307 cs->hw.hfcpci.sctrl_r &= ~SCTRL_B1_ENA; in mode_hfcpci()
1310 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2; in mode_hfcpci()
1311 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1313 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1; in mode_hfcpci()
1314 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1318 hfcpci_clear_fifo_rx(cs, fifo2); in mode_hfcpci()
1319 hfcpci_clear_fifo_tx(cs, fifo2); in mode_hfcpci()
1321 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1322 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1324 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1325 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1328 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2; in mode_hfcpci()
1329 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1330 cs->hw.hfcpci.ctmt |= 2; in mode_hfcpci()
1331 cs->hw.hfcpci.conn &= ~0x18; in mode_hfcpci()
1333 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1; in mode_hfcpci()
1334 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1335 cs->hw.hfcpci.ctmt |= 1; in mode_hfcpci()
1336 cs->hw.hfcpci.conn &= ~0x03; in mode_hfcpci()
1340 hfcpci_clear_fifo_rx(cs, fifo2); in mode_hfcpci()
1341 hfcpci_clear_fifo_tx(cs, fifo2); in mode_hfcpci()
1343 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1344 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1346 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1347 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1350 cs->hw.hfcpci.last_bfifo_cnt[1] = 0; in mode_hfcpci()
1351 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B2; in mode_hfcpci()
1352 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1353 cs->hw.hfcpci.ctmt &= ~2; in mode_hfcpci()
1354 cs->hw.hfcpci.conn &= ~0x18; in mode_hfcpci()
1356 cs->hw.hfcpci.last_bfifo_cnt[0] = 0; in mode_hfcpci()
1357 cs->hw.hfcpci.fifo_en |= HFCPCI_FIFOEN_B1; in mode_hfcpci()
1358 cs->hw.hfcpci.int_m1 |= (HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1359 cs->hw.hfcpci.ctmt &= ~1; in mode_hfcpci()
1360 cs->hw.hfcpci.conn &= ~0x03; in mode_hfcpci()
1365 cs->hw.hfcpci.conn |= 0x10; in mode_hfcpci()
1366 cs->hw.hfcpci.sctrl |= SCTRL_B2_ENA; in mode_hfcpci()
1367 cs->hw.hfcpci.sctrl_r |= SCTRL_B2_ENA; in mode_hfcpci()
1368 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B2; in mode_hfcpci()
1369 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B2TRANS + HFCPCI_INTS_B2REC); in mode_hfcpci()
1371 cs->hw.hfcpci.conn |= 0x02; in mode_hfcpci()
1372 cs->hw.hfcpci.sctrl |= SCTRL_B1_ENA; in mode_hfcpci()
1373 cs->hw.hfcpci.sctrl_r |= SCTRL_B1_ENA; in mode_hfcpci()
1374 cs->hw.hfcpci.fifo_en &= ~HFCPCI_FIFOEN_B1; in mode_hfcpci()
1375 cs->hw.hfcpci.int_m1 &= ~(HFCPCI_INTS_B1TRANS + HFCPCI_INTS_B1REC); in mode_hfcpci()
1379 Write_hfc(cs, HFCPCI_SCTRL_E, cs->hw.hfcpci.sctrl_e); in mode_hfcpci()
1380 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in mode_hfcpci()
1381 Write_hfc(cs, HFCPCI_FIFO_EN, cs->hw.hfcpci.fifo_en); in mode_hfcpci()
1382 Write_hfc(cs, HFCPCI_SCTRL, cs->hw.hfcpci.sctrl); in mode_hfcpci()
1383 Write_hfc(cs, HFCPCI_SCTRL_R, cs->hw.hfcpci.sctrl_r); in mode_hfcpci()
1384 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt); in mode_hfcpci()
1385 Write_hfc(cs, HFCPCI_CONNECT, cs->hw.hfcpci.conn); in mode_hfcpci()
1389 /* Layer2 -> Layer 1 Transfer */
1394 struct BCState *bcs = st->l1.bcs; in hfcpci_l2l1()
1400 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcpci_l2l1()
1401 if (bcs->tx_skb) { in hfcpci_l2l1()
1402 skb_queue_tail(&bcs->squeue, skb); in hfcpci_l2l1()
1404 bcs->tx_skb = skb; in hfcpci_l2l1()
1405 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); in hfcpci_l2l1()
1406 bcs->cs->BC_Send_Data(bcs); in hfcpci_l2l1()
1408 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcpci_l2l1()
1411 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcpci_l2l1()
1412 if (bcs->tx_skb) { in hfcpci_l2l1()
1413 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcpci_l2l1()
1417 // test_and_set_bit(BC_FLG_BUSY, &bcs->Flag); in hfcpci_l2l1()
1418 bcs->tx_skb = skb; in hfcpci_l2l1()
1419 bcs->cs->BC_Send_Data(bcs); in hfcpci_l2l1()
1420 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcpci_l2l1()
1423 if (!bcs->tx_skb) { in hfcpci_l2l1()
1424 test_and_clear_bit(FLG_L1_PULL_REQ, &st->l1.Flags); in hfcpci_l2l1()
1425 st->l1.l1l2(st, PH_PULL | CONFIRM, NULL); in hfcpci_l2l1()
1427 test_and_set_bit(FLG_L1_PULL_REQ, &st->l1.Flags); in hfcpci_l2l1()
1430 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcpci_l2l1()
1431 test_and_set_bit(BC_FLG_ACTIV, &bcs->Flag); in hfcpci_l2l1()
1432 mode_hfcpci(bcs, st->l1.mode, st->l1.bc); in hfcpci_l2l1()
1433 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcpci_l2l1()
1440 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcpci_l2l1()
1441 test_and_clear_bit(BC_FLG_ACTIV, &bcs->Flag); in hfcpci_l2l1()
1442 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); in hfcpci_l2l1()
1443 mode_hfcpci(bcs, 0, st->l1.bc); in hfcpci_l2l1()
1444 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcpci_l2l1()
1445 st->l1.l1l2(st, PH_DEACTIVATE | CONFIRM, NULL); in hfcpci_l2l1()
1451 /* deactivate B-channel access and queues */
1456 mode_hfcpci(bcs, 0, bcs->channel); in close_hfcpci()
1457 if (test_and_clear_bit(BC_FLG_INIT, &bcs->Flag)) { in close_hfcpci()
1458 skb_queue_purge(&bcs->rqueue); in close_hfcpci()
1459 skb_queue_purge(&bcs->squeue); in close_hfcpci()
1460 if (bcs->tx_skb) { in close_hfcpci()
1461 dev_kfree_skb_any(bcs->tx_skb); in close_hfcpci()
1462 bcs->tx_skb = NULL; in close_hfcpci()
1463 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); in close_hfcpci()
1469 /* init B-channel queues and control */
1472 open_hfcpcistate(struct IsdnCardState *cs, struct BCState *bcs) in open_hfcpcistate() argument
1474 if (!test_and_set_bit(BC_FLG_INIT, &bcs->Flag)) { in open_hfcpcistate()
1475 skb_queue_head_init(&bcs->rqueue); in open_hfcpcistate()
1476 skb_queue_head_init(&bcs->squeue); in open_hfcpcistate()
1478 bcs->tx_skb = NULL; in open_hfcpcistate()
1479 test_and_clear_bit(BC_FLG_BUSY, &bcs->Flag); in open_hfcpcistate()
1480 bcs->event = 0; in open_hfcpcistate()
1481 bcs->tx_cnt = 0; in open_hfcpcistate()
1486 /* inits the stack for B-channel */
1491 bcs->channel = st->l1.bc; in setstack_2b()
1492 if (open_hfcpcistate(st->l1.hardware, bcs)) in setstack_2b()
1493 return (-1); in setstack_2b()
1494 st->l1.bcs = bcs; in setstack_2b()
1495 st->l2.l2l1 = hfcpci_l2l1; in setstack_2b()
1497 bcs->st = st; in setstack_2b()
1508 struct IsdnCardState *cs = in hfcpci_bh() local
1513 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { in hfcpci_bh()
1514 if (!cs->hw.hfcpci.nt_mode) in hfcpci_bh()
1515 switch (cs->dc.hfcpci.ph_state) { in hfcpci_bh()
1517 l1_msg(cs, HW_RESET | INDICATION, NULL); in hfcpci_bh()
1519 case (3): in hfcpci_bh()
1520 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); in hfcpci_bh()
1523 l1_msg(cs, HW_RSYNC | INDICATION, NULL); in hfcpci_bh()
1526 l1_msg(cs, HW_INFO2 | INDICATION, NULL); in hfcpci_bh()
1529 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); in hfcpci_bh()
1534 spin_lock_irqsave(&cs->lock, flags); in hfcpci_bh()
1535 switch (cs->dc.hfcpci.ph_state) { in hfcpci_bh()
1537 if (cs->hw.hfcpci.nt_timer < 0) { in hfcpci_bh()
1538 cs->hw.hfcpci.nt_timer = 0; in hfcpci_bh()
1539 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_bh()
1540 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1542 if (Read_hfc(cs, HFCPCI_INT_S1)); in hfcpci_bh()
1543 Write_hfc(cs, HFCPCI_STATES, 4 | HFCPCI_LOAD_STATE); in hfcpci_bh()
1545 Write_hfc(cs, HFCPCI_STATES, 4); in hfcpci_bh()
1546 cs->dc.hfcpci.ph_state = 4; in hfcpci_bh()
1548 cs->hw.hfcpci.int_m1 |= HFCPCI_INTS_TIMER; in hfcpci_bh()
1549 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1550 cs->hw.hfcpci.ctmt &= ~HFCPCI_AUTO_TIMER; in hfcpci_bh()
1551 cs->hw.hfcpci.ctmt |= HFCPCI_TIM3_125; in hfcpci_bh()
1552 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1553 Write_hfc(cs, HFCPCI_CTMT, cs->hw.hfcpci.ctmt | HFCPCI_CLTIMER); in hfcpci_bh()
1554 cs->hw.hfcpci.nt_timer = NT_T1_COUNT; in hfcpci_bh()
1555 Write_hfc(cs, HFCPCI_STATES, 2 | HFCPCI_NT_G2_G3); /* allow G2 -> G3 transition */ in hfcpci_bh()
1559 case (3): in hfcpci_bh()
1561 cs->hw.hfcpci.nt_timer = 0; in hfcpci_bh()
1562 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_bh()
1563 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_bh()
1568 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_bh()
1571 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) in hfcpci_bh()
1572 DChannel_proc_rcv(cs); in hfcpci_bh()
1573 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) in hfcpci_bh()
1574 DChannel_proc_xmt(cs); in hfcpci_bh()
1582 inithfcpci(struct IsdnCardState *cs) in inithfcpci() argument
1584 cs->bcs[0].BC_SetStack = setstack_2b; in inithfcpci()
1585 cs->bcs[1].BC_SetStack = setstack_2b; in inithfcpci()
1586 cs->bcs[0].BC_Close = close_hfcpci; in inithfcpci()
1587 cs->bcs[1].BC_Close = close_hfcpci; in inithfcpci()
1588 timer_setup(&cs->dbusytimer, hfcpci_dbusy_timer, 0); in inithfcpci()
1589 mode_hfcpci(cs->bcs, 0, 0); in inithfcpci()
1590 mode_hfcpci(cs->bcs + 1, 0, 1); in inithfcpci()
1599 hfcpci_card_msg(struct IsdnCardState *cs, int mt, void *arg) in hfcpci_card_msg() argument
1603 if (cs->debug & L1_DEB_ISAC) in hfcpci_card_msg()
1604 debugl1(cs, "HFCPCI: card_msg %x", mt); in hfcpci_card_msg()
1607 spin_lock_irqsave(&cs->lock, flags); in hfcpci_card_msg()
1608 reset_hfcpci(cs); in hfcpci_card_msg()
1609 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_card_msg()
1612 release_io_hfcpci(cs); in hfcpci_card_msg()
1615 spin_lock_irqsave(&cs->lock, flags); in hfcpci_card_msg()
1616 inithfcpci(cs); in hfcpci_card_msg()
1617 reset_hfcpci(cs); in hfcpci_card_msg()
1618 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_card_msg()
1621 spin_lock_irqsave(&cs->lock, flags); in hfcpci_card_msg()
1622 cs->hw.hfcpci.int_m1 &= ~HFCPCI_INTS_TIMER; in hfcpci_card_msg()
1623 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in hfcpci_card_msg()
1625 Write_hfc(cs, HFCPCI_MST_MODE, cs->hw.hfcpci.mst_m); in hfcpci_card_msg()
1626 spin_unlock_irqrestore(&cs->lock, flags); in hfcpci_card_msg()
1642 struct IsdnCardState *cs = card->cs; in setup_hfcpci() local
1648 printk(KERN_INFO "HiSax: HFC-PCI driver Rev. %s\n", HiSax_getrev(tmp)); in setup_hfcpci()
1650 cs->hw.hfcpci.int_s1 = 0; in setup_hfcpci()
1651 cs->dc.hfcpci.ph_state = 0; in setup_hfcpci()
1652 cs->hw.hfcpci.fifo = 255; in setup_hfcpci()
1653 if (cs->typ != ISDN_CTYPE_HFC_PCI) in setup_hfcpci()
1677 …if ((card->para[0]) && (card->para[0] != (tmp_hfcpci->resource[0].start & PCI_BASE_ADDRESS_IO_MASK… in setup_hfcpci()
1685 printk(KERN_WARNING "HFC-PCI: No PCI card found\n"); in setup_hfcpci()
1689 i--; in setup_hfcpci()
1691 cs->hw.hfcpci.dev = dev_hfcpci; in setup_hfcpci()
1692 cs->irq = dev_hfcpci->irq; in setup_hfcpci()
1693 if (!cs->irq) { in setup_hfcpci()
1694 printk(KERN_WARNING "HFC-PCI: No IRQ for PCI card found\n"); in setup_hfcpci()
1697 cs->hw.hfcpci.pci_io = (char *)(unsigned long)dev_hfcpci->resource[1].start; in setup_hfcpci()
1698 …printk(KERN_INFO "HiSax: HFC-PCI card manufacturer: %s card name: %s\n", id_list[i].vendor_name, i… in setup_hfcpci()
1700 if (!cs->hw.hfcpci.pci_io) { in setup_hfcpci()
1701 printk(KERN_WARNING "HFC-PCI: No IO-Mem for PCI card found\n"); in setup_hfcpci()
1706 cs->hw.hfcpci.fifos = pci_alloc_consistent(cs->hw.hfcpci.dev, in setup_hfcpci()
1707 0x8000, &cs->hw.hfcpci.dma); in setup_hfcpci()
1708 if (!cs->hw.hfcpci.fifos) { in setup_hfcpci()
1709 printk(KERN_WARNING "HFC-PCI: Error allocating FIFO memory!\n"); in setup_hfcpci()
1712 if (cs->hw.hfcpci.dma & 0x7fff) { in setup_hfcpci()
1714 "HFC-PCI: Error DMA memory not on 32K boundary (%lx)\n", in setup_hfcpci()
1715 (u_long)cs->hw.hfcpci.dma); in setup_hfcpci()
1716 pci_free_consistent(cs->hw.hfcpci.dev, 0x8000, in setup_hfcpci()
1717 cs->hw.hfcpci.fifos, cs->hw.hfcpci.dma); in setup_hfcpci()
1720 pci_write_config_dword(cs->hw.hfcpci.dev, 0x80, (u32)cs->hw.hfcpci.dma); in setup_hfcpci()
1721 cs->hw.hfcpci.pci_io = ioremap((ulong) cs->hw.hfcpci.pci_io, 256); in setup_hfcpci()
1723 "HFC-PCI: defined at mem %p fifo %p(%lx) IRQ %d HZ %d\n", in setup_hfcpci()
1724 cs->hw.hfcpci.pci_io, in setup_hfcpci()
1725 cs->hw.hfcpci.fifos, in setup_hfcpci()
1726 (u_long)cs->hw.hfcpci.dma, in setup_hfcpci()
1727 cs->irq, HZ); in setup_hfcpci()
1729 spin_lock_irqsave(&cs->lock, flags); in setup_hfcpci()
1731 …pci_write_config_word(cs->hw.hfcpci.dev, PCI_COMMAND, PCI_ENA_MEMIO); /* enable memory mapped port… in setup_hfcpci()
1732 cs->hw.hfcpci.int_m2 = 0; /* disable alle interrupts */ in setup_hfcpci()
1733 cs->hw.hfcpci.int_m1 = 0; in setup_hfcpci()
1734 Write_hfc(cs, HFCPCI_INT_M1, cs->hw.hfcpci.int_m1); in setup_hfcpci()
1735 Write_hfc(cs, HFCPCI_INT_M2, cs->hw.hfcpci.int_m2); in setup_hfcpci()
1739 INIT_WORK(&cs->tqueue, hfcpci_bh); in setup_hfcpci()
1740 cs->setstack_d = setstack_hfcpci; in setup_hfcpci()
1741 cs->BC_Send_Data = &hfcpci_send_data; in setup_hfcpci()
1742 cs->readisac = NULL; in setup_hfcpci()
1743 cs->writeisac = NULL; in setup_hfcpci()
1744 cs->readisacfifo = NULL; in setup_hfcpci()
1745 cs->writeisacfifo = NULL; in setup_hfcpci()
1746 cs->BC_Read_Reg = NULL; in setup_hfcpci()
1747 cs->BC_Write_Reg = NULL; in setup_hfcpci()
1748 cs->irq_func = &hfcpci_interrupt; in setup_hfcpci()
1749 cs->irq_flags |= IRQF_SHARED; in setup_hfcpci()
1750 timer_setup(&cs->hw.hfcpci.timer, hfcpci_Timer, 0); in setup_hfcpci()
1751 cs->cardmsg = &hfcpci_card_msg; in setup_hfcpci()
1752 cs->auxcmd = &hfcpci_auxcmd; in setup_hfcpci()
1754 spin_unlock_irqrestore(&cs->lock, flags); in setup_hfcpci()