Lines Matching refs:cs
62 Write_hfc(struct IsdnCardState *cs, u_char regnum, u_char val) in Write_hfc() argument
64 byteout(cs->hw.hfcsx.base + 1, regnum); in Write_hfc()
65 byteout(cs->hw.hfcsx.base, val); in Write_hfc()
69 Read_hfc(struct IsdnCardState *cs, u_char regnum) in Read_hfc() argument
73 byteout(cs->hw.hfcsx.base + 1, regnum); in Read_hfc()
74 ret = bytein(cs->hw.hfcsx.base); in Read_hfc()
83 fifo_select(struct IsdnCardState *cs, u_char fifo) in fifo_select() argument
85 if (fifo == cs->hw.hfcsx.last_fifo) in fifo_select()
88 byteout(cs->hw.hfcsx.base + 1, HFCSX_FIF_SEL); in fifo_select()
89 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
90 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in fifo_select()
92 byteout(cs->hw.hfcsx.base, fifo); in fifo_select()
93 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in fifo_select()
101 reset_fifo(struct IsdnCardState *cs, u_char fifo) in reset_fifo() argument
103 fifo_select(cs, fifo); /* first select the fifo */ in reset_fifo()
104 byteout(cs->hw.hfcsx.base + 1, HFCSX_CIRM); in reset_fifo()
105 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.cirm | 0x80); /* reset cmd */ in reset_fifo()
107 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in reset_fifo()
117 write_fifo(struct IsdnCardState *cs, struct sk_buff *skb, u_char fifo, int trans_max) in write_fifo() argument
126 fifo_select(cs, fifo); in write_fifo()
133 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ in write_fifo()
137 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in write_fifo()
138 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in write_fifo()
142 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in write_fifo()
143 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in write_fifo()
153 Write_hfc(cs, HFCSX_FIF_DWR, *src++); in write_fifo()
157 msp = ((struct hfcsx_extra *)(cs->hw.hfcsx.extra))->marker; in write_fifo()
159 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; in write_fifo()
160 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; in write_fifo()
166 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
167 debugl1(cs, "hfcsx_write_fifo %d more as %d frames", fifo, f_msk - 1); in write_fifo()
173 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
174 debugl1(cs, "hfcsx_write_fifo %d f1(%x) f2(%x) z1(f1)(%x)", in write_fifo()
181 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
182 debugl1(cs, "hfcsx_write_fifo %d count(%u/%d)", in write_fifo()
185 if (cs->debug & L1_DEB_ISAC_FIFO) in write_fifo()
186 debugl1(cs, "hfcsx_write_fifo %d no fifo mem", fifo); in write_fifo()
193 Write_hfc(cs, HFCSX_FIF_DWR, *src++); in write_fifo()
195 Read_hfc(cs, HFCSX_FIF_INCF1); /* increment F1 */ in write_fifo()
197 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in write_fifo()
207 read_fifo(struct IsdnCardState *cs, u_char fifo, int trans_max) in read_fifo() argument
213 fifo_select(cs, fifo); in read_fifo()
220 fifo_size = cs->hw.hfcsx.b_fifo_size; /* B-channel */ in read_fifo()
226 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in read_fifo()
227 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in read_fifo()
228 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in read_fifo()
229 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in read_fifo()
241 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
248 f1 = Read_hfc(cs, HFCSX_FIF_F1) & f_msk; in read_fifo()
249 f2 = Read_hfc(cs, HFCSX_FIF_F2) & f_msk; in read_fifo()
253 z1 = Read_hfc(cs, HFCSX_FIF_Z1H); in read_fifo()
254 z1 = ((z1 << 8) | Read_hfc(cs, HFCSX_FIF_Z1L)); in read_fifo()
255 z2 = Read_hfc(cs, HFCSX_FIF_Z2H); in read_fifo()
256 z2 = ((z2 << 8) | Read_hfc(cs, HFCSX_FIF_Z2L)); in read_fifo()
258 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
259 debugl1(cs, "hfcsx_read_fifo %d f1(%x) f2(%x) z1(f2)(%x) z2(f2)(%x)", in read_fifo()
267 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
268 debugl1(cs, "hfcsx_read_fifo %d count %u)", in read_fifo()
272 if (cs->debug & L1_DEB_WARN) in read_fifo()
273 debugl1(cs, "hfcsx_read_fifo %d packet inv. len %d ", fifo , count); in read_fifo()
276 Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
285 *dst++ = Read_hfc(cs, HFCSX_FIF_DRD); in read_fifo()
287 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 1 */ in read_fifo()
288 Read_hfc(cs, HFCSX_FIF_DRD); /* CRC 2 */ in read_fifo()
289 if (Read_hfc(cs, HFCSX_FIF_DRD)) { in read_fifo()
291 if (cs->debug & L1_DEB_ISAC_FIFO) in read_fifo()
292 debugl1(cs, "hfcsx_read_fifo %d crc error", fifo); in read_fifo()
300 Read_hfc(cs, HFCSX_FIF_INCF2); /* increment F2 */ in read_fifo()
302 while (bytein(cs->hw.hfcsx.base + 1) & 1); /* wait for busy */ in read_fifo()
312 release_io_hfcsx(struct IsdnCardState *cs) in release_io_hfcsx() argument
314 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ in release_io_hfcsx()
315 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in release_io_hfcsx()
316 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET); /* Reset On */ in release_io_hfcsx()
318 Write_hfc(cs, HFCSX_CIRM, 0); /* Reset Off */ in release_io_hfcsx()
319 del_timer(&cs->hw.hfcsx.timer); in release_io_hfcsx()
320 release_region(cs->hw.hfcsx.base, 2); /* release IO-Block */ in release_io_hfcsx()
321 kfree(cs->hw.hfcsx.extra); in release_io_hfcsx()
322 cs->hw.hfcsx.extra = NULL; in release_io_hfcsx()
329 static int set_fifo_size(struct IsdnCardState *cs) in set_fifo_size() argument
332 if (cs->hw.hfcsx.b_fifo_size) return (1); /* already determined */ in set_fifo_size()
334 if ((cs->hw.hfcsx.chip >> 4) == 9) { in set_fifo_size()
335 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_32K; in set_fifo_size()
339 cs->hw.hfcsx.b_fifo_size = B_FIFO_SIZE_8K; in set_fifo_size()
340 cs->hw.hfcsx.cirm |= 0x10; /* only 8K of ram */ in set_fifo_size()
350 reset_hfcsx(struct IsdnCardState *cs) in reset_hfcsx() argument
352 cs->hw.hfcsx.int_m2 = 0; /* interrupt output off ! */ in reset_hfcsx()
353 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
357 Write_hfc(cs, HFCSX_CIRM, HFCSX_RESET | cs->hw.hfcsx.cirm); /* Reset */ in reset_hfcsx()
359 Write_hfc(cs, HFCSX_CIRM, cs->hw.hfcsx.cirm); /* Reset Off */ in reset_hfcsx()
361 if (Read_hfc(cs, HFCSX_STATUS) & 2) in reset_hfcsx()
363 cs->hw.hfcsx.last_fifo = 0xff; /* invalidate */ in reset_hfcsx()
364 if (!set_fifo_size(cs)) continue; in reset_hfcsx()
368 cs->hw.hfcsx.trm = 0 + HFCSX_BTRANS_THRESMASK; /* no echo connect , threshold */ in reset_hfcsx()
369 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in reset_hfcsx()
371 Write_hfc(cs, HFCSX_CLKDEL, 0x0e); /* ST-Bit delay for TE-Mode */ in reset_hfcsx()
372 cs->hw.hfcsx.sctrl_e = HFCSX_AUTO_AWAKE; in reset_hfcsx()
373 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); /* S/T Auto awake */ in reset_hfcsx()
374 cs->hw.hfcsx.bswapped = 0; /* no exchange */ in reset_hfcsx()
375 cs->hw.hfcsx.nt_mode = 0; /* we are in TE mode */ in reset_hfcsx()
376 cs->hw.hfcsx.ctmt = HFCSX_TIM3_125 | HFCSX_AUTO_TIMER; in reset_hfcsx()
377 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in reset_hfcsx()
379 cs->hw.hfcsx.int_m1 = HFCSX_INTS_DTRANS | HFCSX_INTS_DREC | in reset_hfcsx()
381 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in reset_hfcsx()
384 if (Read_hfc(cs, HFCSX_INT_S1)); in reset_hfcsx()
386 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 2); /* HFC ST 2 */ in reset_hfcsx()
388 Write_hfc(cs, HFCSX_STATES, 2); /* HFC ST 2 */ in reset_hfcsx()
389 cs->hw.hfcsx.mst_m = HFCSX_MASTER; /* HFC Master Mode */ in reset_hfcsx()
391 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in reset_hfcsx()
392 cs->hw.hfcsx.sctrl = 0x40; /* set tx_lo mode, error in datasheet ! */ in reset_hfcsx()
393 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in reset_hfcsx()
394 cs->hw.hfcsx.sctrl_r = 0; in reset_hfcsx()
395 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in reset_hfcsx()
404 cs->hw.hfcsx.conn = 0x36; /* set data flow directions */ in reset_hfcsx()
405 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in reset_hfcsx()
406 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* B1-Slot 0 STIO1 out enabled */ in reset_hfcsx()
407 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* B2-Slot 1 STIO1 out enabled */ in reset_hfcsx()
408 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* B1-Slot 0 STIO2 in enabled */ in reset_hfcsx()
409 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* B2-Slot 1 STIO2 in enabled */ in reset_hfcsx()
412 cs->hw.hfcsx.int_m2 = HFCSX_IRQ_ENABLE; in reset_hfcsx()
413 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in reset_hfcsx()
414 if (Read_hfc(cs, HFCSX_INT_S2)); in reset_hfcsx()
423 struct IsdnCardState *cs = from_timer(cs, t, hw.hfcsx.timer); in hfcsx_Timer() local
424 cs->hw.hfcsx.timer.expires = jiffies + 75; in hfcsx_Timer()
436 Sel_BCS(struct IsdnCardState *cs, int channel) in Sel_BCS() argument
438 if (cs->bcs[0].mode && (cs->bcs[0].channel == channel)) in Sel_BCS()
439 return (&cs->bcs[0]); in Sel_BCS()
440 else if (cs->bcs[1].mode && (cs->bcs[1].channel == channel)) in Sel_BCS()
441 return (&cs->bcs[1]); in Sel_BCS()
451 receive_dmsg(struct IsdnCardState *cs) in receive_dmsg() argument
456 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_dmsg()
457 debugl1(cs, "rec_dmsg blocked"); in receive_dmsg()
462 skb = read_fifo(cs, HFCSX_SEL_D_RX, 0); in receive_dmsg()
464 skb_queue_tail(&cs->rq, skb); in receive_dmsg()
465 schedule_event(cs, D_RCVBUFREADY); in receive_dmsg()
469 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_dmsg()
479 struct IsdnCardState *cs = bcs->cs; in main_rec_hfcsx() local
485 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in main_rec_hfcsx()
486 debugl1(cs, "rec_data %d blocked", bcs->channel); in main_rec_hfcsx()
489 skb = read_fifo(cs, ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? in main_rec_hfcsx()
499 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in main_rec_hfcsx()
509 hfcsx_fill_dfifo(struct IsdnCardState *cs) in hfcsx_fill_dfifo() argument
511 if (!cs->tx_skb) in hfcsx_fill_dfifo()
513 if (cs->tx_skb->len <= 0) in hfcsx_fill_dfifo()
516 if (write_fifo(cs, cs->tx_skb, HFCSX_SEL_D_TX, 0)) { in hfcsx_fill_dfifo()
517 dev_kfree_skb_any(cs->tx_skb); in hfcsx_fill_dfifo()
518 cs->tx_skb = NULL; in hfcsx_fill_dfifo()
529 struct IsdnCardState *cs = bcs->cs; in hfcsx_fill_fifo() local
536 if (write_fifo(cs, bcs->tx_skb, in hfcsx_fill_fifo()
537 ((bcs->channel) && (!cs->hw.hfcsx.bswapped)) ? in hfcsx_fill_fifo()
563 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in dch_nt_l2l1() local
576 debugl1(cs, "PH_TEST_LOOP B1"); in dch_nt_l2l1()
578 debugl1(cs, "PH_TEST_LOOP B2"); in dch_nt_l2l1()
580 debugl1(cs, "PH_TEST_LOOP DISABLED"); in dch_nt_l2l1()
584 if (cs->debug) in dch_nt_l2l1()
585 debugl1(cs, "dch_nt_l2l1 msg %04X unhandled", pr); in dch_nt_l2l1()
596 hfcsx_auxcmd(struct IsdnCardState *cs, isdn_ctrl *ic) in hfcsx_auxcmd() argument
602 …(!(cs->hw.hfcsx.int_m1 & (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC + HFCSX_INTS_B1TRANS + HFCSX_INTS_… in hfcsx_auxcmd()
603 spin_lock_irqsave(&cs->lock, flags); in hfcsx_auxcmd()
604 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 0); /* HFC ST G0 */ in hfcsx_auxcmd()
606 cs->hw.hfcsx.sctrl |= SCTRL_MODE_NT; in hfcsx_auxcmd()
607 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); /* set NT-mode */ in hfcsx_auxcmd()
609 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 1); /* HFC ST G1 */ in hfcsx_auxcmd()
611 Write_hfc(cs, HFCSX_STATES, 1 | HFCSX_ACTIVATE | HFCSX_DO_ACTION); in hfcsx_auxcmd()
612 cs->dc.hfcsx.ph_state = 1; in hfcsx_auxcmd()
613 cs->hw.hfcsx.nt_mode = 1; in hfcsx_auxcmd()
614 cs->hw.hfcsx.nt_timer = 0; in hfcsx_auxcmd()
615 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_auxcmd()
616 cs->stlist->l2.l2l1 = dch_nt_l2l1; in hfcsx_auxcmd()
617 debugl1(cs, "NT mode activated"); in hfcsx_auxcmd()
620 if ((cs->chanlimit > 1) || (cs->hw.hfcsx.bswapped) || in hfcsx_auxcmd()
621 (cs->hw.hfcsx.nt_mode) || (ic->arg != 12)) in hfcsx_auxcmd()
625 cs->logecho = 1; in hfcsx_auxcmd()
626 cs->hw.hfcsx.trm |= 0x20; /* enable echo chan */ in hfcsx_auxcmd()
627 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_B2REC; in hfcsx_auxcmd()
630 cs->logecho = 0; in hfcsx_auxcmd()
631 cs->hw.hfcsx.trm &= ~0x20; /* disable echo chan */ in hfcsx_auxcmd()
632 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_B2REC; in hfcsx_auxcmd()
634 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; in hfcsx_auxcmd()
635 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; in hfcsx_auxcmd()
636 cs->hw.hfcsx.conn |= 0x10; /* B2-IOM -> B2-ST */ in hfcsx_auxcmd()
637 cs->hw.hfcsx.ctmt &= ~2; in hfcsx_auxcmd()
638 spin_lock_irqsave(&cs->lock, flags); in hfcsx_auxcmd()
639 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in hfcsx_auxcmd()
640 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in hfcsx_auxcmd()
641 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in hfcsx_auxcmd()
642 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in hfcsx_auxcmd()
643 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in hfcsx_auxcmd()
644 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_auxcmd()
645 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_auxcmd()
653 receive_emsg(struct IsdnCardState *cs) in receive_emsg() argument
659 if (test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in receive_emsg()
660 debugl1(cs, "echo_rec_data blocked"); in receive_emsg()
664 skb = read_fifo(cs, HFCSX_SEL_B2_RX, 0); in receive_emsg()
666 if (cs->debug & DEB_DLOG_HEX) { in receive_emsg()
667 ptr = cs->dlog; in receive_emsg()
678 HiSax_putstatus(cs, NULL, cs->dlog); in receive_emsg()
680 HiSax_putstatus(cs, "LogEcho: ", "warning Frame too big (%d)", skb->len); in receive_emsg()
686 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in receive_emsg()
697 struct IsdnCardState *cs = dev_id; in hfcsx_interrupt() local
704 if (!(cs->hw.hfcsx.int_m2 & 0x08)) in hfcsx_interrupt()
707 spin_lock_irqsave(&cs->lock, flags); in hfcsx_interrupt()
708 if (HFCSX_ANYINT & (stat = Read_hfc(cs, HFCSX_STATUS))) { in hfcsx_interrupt()
709 val = Read_hfc(cs, HFCSX_INT_S1); in hfcsx_interrupt()
710 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
711 debugl1(cs, "HFC-SX: stat(%02x) s1(%02x)", stat, val); in hfcsx_interrupt()
713 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_interrupt()
716 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
717 debugl1(cs, "HFC-SX irq %x %s", val, in hfcsx_interrupt()
718 test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags) ? in hfcsx_interrupt()
720 val &= cs->hw.hfcsx.int_m1; in hfcsx_interrupt()
722 exval = Read_hfc(cs, HFCSX_STATES) & 0xf; in hfcsx_interrupt()
723 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
724 debugl1(cs, "ph_state chg %d->%d", cs->dc.hfcsx.ph_state, in hfcsx_interrupt()
726 cs->dc.hfcsx.ph_state = exval; in hfcsx_interrupt()
727 schedule_event(cs, D_L1STATECHANGE); in hfcsx_interrupt()
731 if (cs->hw.hfcsx.nt_mode) { in hfcsx_interrupt()
732 if ((--cs->hw.hfcsx.nt_timer) < 0) in hfcsx_interrupt()
733 schedule_event(cs, D_L1STATECHANGE); in hfcsx_interrupt()
736 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_interrupt()
739 if (test_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
740 cs->hw.hfcsx.int_s1 |= val; in hfcsx_interrupt()
741 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_interrupt()
744 if (cs->hw.hfcsx.int_s1 & 0x18) { in hfcsx_interrupt()
746 val = cs->hw.hfcsx.int_s1; in hfcsx_interrupt()
747 cs->hw.hfcsx.int_s1 = exval; in hfcsx_interrupt()
750 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { in hfcsx_interrupt()
751 if (cs->debug) in hfcsx_interrupt()
752 debugl1(cs, "hfcsx spurious 0x08 IRQ"); in hfcsx_interrupt()
757 if (cs->logecho) in hfcsx_interrupt()
758 receive_emsg(cs); in hfcsx_interrupt()
759 else if (!(bcs = Sel_BCS(cs, 1))) { in hfcsx_interrupt()
760 if (cs->debug) in hfcsx_interrupt()
761 debugl1(cs, "hfcsx spurious 0x10 IRQ"); in hfcsx_interrupt()
766 if (!(bcs = Sel_BCS(cs, cs->hw.hfcsx.bswapped ? 1 : 0))) { in hfcsx_interrupt()
767 if (cs->debug) in hfcsx_interrupt()
768 debugl1(cs, "hfcsx spurious 0x01 IRQ"); in hfcsx_interrupt()
771 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
773 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
775 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
778 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
780 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
782 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
790 if (!(bcs = Sel_BCS(cs, 1))) { in hfcsx_interrupt()
791 if (cs->debug) in hfcsx_interrupt()
792 debugl1(cs, "hfcsx spurious 0x02 IRQ"); in hfcsx_interrupt()
795 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
797 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
799 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
802 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
804 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
806 debugl1(cs, "fill_data %d blocked", bcs->channel); in hfcsx_interrupt()
814 receive_dmsg(cs); in hfcsx_interrupt()
817 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in hfcsx_interrupt()
818 del_timer(&cs->dbusytimer); in hfcsx_interrupt()
819 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in hfcsx_interrupt()
820 schedule_event(cs, D_CLEARBUSY); in hfcsx_interrupt()
821 if (cs->tx_skb) { in hfcsx_interrupt()
822 if (cs->tx_skb->len) { in hfcsx_interrupt()
823 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
824 hfcsx_fill_dfifo(cs); in hfcsx_interrupt()
825 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
827 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); in hfcsx_interrupt()
831 dev_kfree_skb_irq(cs->tx_skb); in hfcsx_interrupt()
832 cs->tx_cnt = 0; in hfcsx_interrupt()
833 cs->tx_skb = NULL; in hfcsx_interrupt()
836 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { in hfcsx_interrupt()
837 cs->tx_cnt = 0; in hfcsx_interrupt()
838 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_interrupt()
839 hfcsx_fill_dfifo(cs); in hfcsx_interrupt()
840 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_interrupt()
842 debugl1(cs, "hfcsx_fill_dfifo irq blocked"); in hfcsx_interrupt()
845 schedule_event(cs, D_XMTBUFREADY); in hfcsx_interrupt()
848 if (cs->hw.hfcsx.int_s1 && count--) { in hfcsx_interrupt()
849 val = cs->hw.hfcsx.int_s1; in hfcsx_interrupt()
850 cs->hw.hfcsx.int_s1 = 0; in hfcsx_interrupt()
851 if (cs->debug & L1_DEB_ISAC) in hfcsx_interrupt()
852 debugl1(cs, "HFC-SX irq %x loop %d", val, 15 - count); in hfcsx_interrupt()
856 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_interrupt()
874 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in HFCSX_l1hw() local
880 if (cs->debug & DEB_DLOG_HEX) in HFCSX_l1hw()
881 LogFrame(cs, skb->data, skb->len); in HFCSX_l1hw()
882 if (cs->debug & DEB_DLOG_VERBOSE) in HFCSX_l1hw()
883 dlogframe(cs, skb, 0); in HFCSX_l1hw()
884 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
885 if (cs->tx_skb) { in HFCSX_l1hw()
886 skb_queue_tail(&cs->sq, skb); in HFCSX_l1hw()
888 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
889 Logl2Frame(cs, skb, "PH_DATA Queued", 0); in HFCSX_l1hw()
892 cs->tx_skb = skb; in HFCSX_l1hw()
893 cs->tx_cnt = 0; in HFCSX_l1hw()
895 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
896 Logl2Frame(cs, skb, "PH_DATA", 0); in HFCSX_l1hw()
898 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCSX_l1hw()
899 hfcsx_fill_dfifo(cs); in HFCSX_l1hw()
900 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCSX_l1hw()
902 debugl1(cs, "hfcsx_fill_dfifo blocked"); in HFCSX_l1hw()
905 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
908 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
909 if (cs->tx_skb) { in HFCSX_l1hw()
910 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
911 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); in HFCSX_l1hw()
912 skb_queue_tail(&cs->sq, skb); in HFCSX_l1hw()
913 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
916 if (cs->debug & DEB_DLOG_HEX) in HFCSX_l1hw()
917 LogFrame(cs, skb->data, skb->len); in HFCSX_l1hw()
918 if (cs->debug & DEB_DLOG_VERBOSE) in HFCSX_l1hw()
919 dlogframe(cs, skb, 0); in HFCSX_l1hw()
920 cs->tx_skb = skb; in HFCSX_l1hw()
921 cs->tx_cnt = 0; in HFCSX_l1hw()
923 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
924 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); in HFCSX_l1hw()
926 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in HFCSX_l1hw()
927 hfcsx_fill_dfifo(cs); in HFCSX_l1hw()
928 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in HFCSX_l1hw()
930 debugl1(cs, "hfcsx_fill_dfifo blocked"); in HFCSX_l1hw()
931 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
935 if (cs->debug & L1_DEB_LAPD) in HFCSX_l1hw()
936 debugl1(cs, "-> PH_REQUEST_PULL"); in HFCSX_l1hw()
938 if (!cs->tx_skb) { in HFCSX_l1hw()
945 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
946 Write_hfc(cs, HFCSX_STATES, HFCSX_LOAD_STATE | 3); /* HFC ST 3 */ in HFCSX_l1hw()
948 Write_hfc(cs, HFCSX_STATES, 3); /* HFC ST 2 */ in HFCSX_l1hw()
949 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; in HFCSX_l1hw()
950 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
951 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); in HFCSX_l1hw()
952 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
953 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); in HFCSX_l1hw()
956 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
957 Write_hfc(cs, HFCSX_STATES, HFCSX_ACTIVATE | HFCSX_DO_ACTION); in HFCSX_l1hw()
958 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
961 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
962 cs->hw.hfcsx.mst_m &= ~HFCSX_MASTER; in HFCSX_l1hw()
963 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
964 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
967 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
968 cs->hw.hfcsx.mst_m |= HFCSX_MASTER; in HFCSX_l1hw()
969 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in HFCSX_l1hw()
970 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
973 spin_lock_irqsave(&cs->lock, flags); in HFCSX_l1hw()
976 Write_hfc(cs, HFCSX_B1_SSL, 0x80); /* tx slot */ in HFCSX_l1hw()
977 Write_hfc(cs, HFCSX_B1_RSL, 0x80); /* rx slot */ in HFCSX_l1hw()
978 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~7) | 1; in HFCSX_l1hw()
979 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
982 Write_hfc(cs, HFCSX_B2_SSL, 0x81); /* tx slot */ in HFCSX_l1hw()
983 Write_hfc(cs, HFCSX_B2_RSL, 0x81); /* rx slot */ in HFCSX_l1hw()
984 cs->hw.hfcsx.conn = (cs->hw.hfcsx.conn & ~0x38) | 0x08; in HFCSX_l1hw()
985 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in HFCSX_l1hw()
988 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
989 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
990 debugl1(cs, "hfcsx_l1hw loop invalid %4lx", (unsigned long)arg); in HFCSX_l1hw()
993 cs->hw.hfcsx.trm |= 0x80; /* enable IOM-loop */ in HFCSX_l1hw()
994 Write_hfc(cs, HFCSX_TRM, cs->hw.hfcsx.trm); in HFCSX_l1hw()
995 spin_unlock_irqrestore(&cs->lock, flags); in HFCSX_l1hw()
998 if (cs->debug & L1_DEB_WARN) in HFCSX_l1hw()
999 debugl1(cs, "hfcsx_l1hw unknown pr %4x", pr); in HFCSX_l1hw()
1008 setstack_hfcsx(struct PStack *st, struct IsdnCardState *cs) in setstack_hfcsx() argument
1019 struct IsdnCardState *cs = bcs->cs; in hfcsx_send_data() local
1021 if (!test_and_set_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags)) { in hfcsx_send_data()
1023 test_and_clear_bit(FLG_LOCK_ATOMIC, &cs->HW_Flags); in hfcsx_send_data()
1025 debugl1(cs, "send_data %d blocked", bcs->channel); in hfcsx_send_data()
1034 struct IsdnCardState *cs = bcs->cs; in mode_hfcsx() local
1037 if (cs->debug & L1_DEB_HSCX) in mode_hfcsx()
1038 debugl1(cs, "HFCSX bchannel mode %d bchan %d/%d", in mode_hfcsx()
1043 if (cs->chanlimit > 1) { in mode_hfcsx()
1044 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1045 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1049 cs->hw.hfcsx.bswapped = 1; /* B1 and B2 exchanged */ in mode_hfcsx()
1050 cs->hw.hfcsx.sctrl_e |= 0x80; in mode_hfcsx()
1052 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1053 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1057 cs->hw.hfcsx.bswapped = 0; /* B1 and B2 normal mode */ in mode_hfcsx()
1058 cs->hw.hfcsx.sctrl_e &= ~0x80; in mode_hfcsx()
1064 cs->hw.hfcsx.sctrl &= ~SCTRL_B2_ENA; in mode_hfcsx()
1065 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B2_ENA; in mode_hfcsx()
1067 cs->hw.hfcsx.sctrl &= ~SCTRL_B1_ENA; in mode_hfcsx()
1068 cs->hw.hfcsx.sctrl_r &= ~SCTRL_B1_ENA; in mode_hfcsx()
1071 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1073 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1078 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1079 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1081 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1082 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1085 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1086 cs->hw.hfcsx.ctmt |= 2; in mode_hfcsx()
1087 cs->hw.hfcsx.conn &= ~0x18; in mode_hfcsx()
1089 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1090 cs->hw.hfcsx.ctmt |= 1; in mode_hfcsx()
1091 cs->hw.hfcsx.conn &= ~0x03; in mode_hfcsx()
1096 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1097 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1099 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1100 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1103 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1104 cs->hw.hfcsx.ctmt &= ~2; in mode_hfcsx()
1105 cs->hw.hfcsx.conn &= ~0x18; in mode_hfcsx()
1107 cs->hw.hfcsx.int_m1 |= (HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1108 cs->hw.hfcsx.ctmt &= ~1; in mode_hfcsx()
1109 cs->hw.hfcsx.conn &= ~0x03; in mode_hfcsx()
1114 cs->hw.hfcsx.conn |= 0x10; in mode_hfcsx()
1115 cs->hw.hfcsx.sctrl |= SCTRL_B2_ENA; in mode_hfcsx()
1116 cs->hw.hfcsx.sctrl_r |= SCTRL_B2_ENA; in mode_hfcsx()
1117 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B2TRANS + HFCSX_INTS_B2REC); in mode_hfcsx()
1119 cs->hw.hfcsx.conn |= 0x02; in mode_hfcsx()
1120 cs->hw.hfcsx.sctrl |= SCTRL_B1_ENA; in mode_hfcsx()
1121 cs->hw.hfcsx.sctrl_r |= SCTRL_B1_ENA; in mode_hfcsx()
1122 cs->hw.hfcsx.int_m1 &= ~(HFCSX_INTS_B1TRANS + HFCSX_INTS_B1REC); in mode_hfcsx()
1126 Write_hfc(cs, HFCSX_SCTRL_E, cs->hw.hfcsx.sctrl_e); in mode_hfcsx()
1127 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in mode_hfcsx()
1128 Write_hfc(cs, HFCSX_SCTRL, cs->hw.hfcsx.sctrl); in mode_hfcsx()
1129 Write_hfc(cs, HFCSX_SCTRL_R, cs->hw.hfcsx.sctrl_r); in mode_hfcsx()
1130 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt); in mode_hfcsx()
1131 Write_hfc(cs, HFCSX_CONNECT, cs->hw.hfcsx.conn); in mode_hfcsx()
1133 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_RX : HFCSX_SEL_B1_RX); in mode_hfcsx()
1134 reset_fifo(cs, fifo2 ? HFCSX_SEL_B2_TX : HFCSX_SEL_B1_TX); in mode_hfcsx()
1150 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcsx_l2l1()
1156 bcs->cs->BC_Send_Data(bcs); in hfcsx_l2l1()
1158 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcsx_l2l1()
1161 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcsx_l2l1()
1168 bcs->cs->BC_Send_Data(bcs); in hfcsx_l2l1()
1170 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcsx_l2l1()
1180 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcsx_l2l1()
1183 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcsx_l2l1()
1190 spin_lock_irqsave(&bcs->cs->lock, flags); in hfcsx_l2l1()
1194 spin_unlock_irqrestore(&bcs->cs->lock, flags); in hfcsx_l2l1()
1222 open_hfcsxstate(struct IsdnCardState *cs, struct BCState *bcs) in open_hfcsxstate() argument
1258 struct IsdnCardState *cs = in hfcsx_bh() local
1262 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) { in hfcsx_bh()
1263 if (!cs->hw.hfcsx.nt_mode) in hfcsx_bh()
1264 switch (cs->dc.hfcsx.ph_state) { in hfcsx_bh()
1266 l1_msg(cs, HW_RESET | INDICATION, NULL); in hfcsx_bh()
1269 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); in hfcsx_bh()
1272 l1_msg(cs, HW_RSYNC | INDICATION, NULL); in hfcsx_bh()
1275 l1_msg(cs, HW_INFO2 | INDICATION, NULL); in hfcsx_bh()
1278 l1_msg(cs, HW_INFO4_P8 | INDICATION, NULL); in hfcsx_bh()
1283 switch (cs->dc.hfcsx.ph_state) { in hfcsx_bh()
1285 spin_lock_irqsave(&cs->lock, flags); in hfcsx_bh()
1286 if (cs->hw.hfcsx.nt_timer < 0) { in hfcsx_bh()
1287 cs->hw.hfcsx.nt_timer = 0; in hfcsx_bh()
1288 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_bh()
1289 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1291 if (Read_hfc(cs, HFCSX_INT_S1)); in hfcsx_bh()
1293 Write_hfc(cs, HFCSX_STATES, 4 | HFCSX_LOAD_STATE); in hfcsx_bh()
1295 Write_hfc(cs, HFCSX_STATES, 4); in hfcsx_bh()
1296 cs->dc.hfcsx.ph_state = 4; in hfcsx_bh()
1298 cs->hw.hfcsx.int_m1 |= HFCSX_INTS_TIMER; in hfcsx_bh()
1299 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1300 cs->hw.hfcsx.ctmt &= ~HFCSX_AUTO_TIMER; in hfcsx_bh()
1301 cs->hw.hfcsx.ctmt |= HFCSX_TIM3_125; in hfcsx_bh()
1302 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1303 Write_hfc(cs, HFCSX_CTMT, cs->hw.hfcsx.ctmt | HFCSX_CLTIMER); in hfcsx_bh()
1304 cs->hw.hfcsx.nt_timer = NT_T1_COUNT; in hfcsx_bh()
1305 Write_hfc(cs, HFCSX_STATES, 2 | HFCSX_NT_G2_G3); /* allow G2 -> G3 transition */ in hfcsx_bh()
1307 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_bh()
1312 spin_lock_irqsave(&cs->lock, flags); in hfcsx_bh()
1313 cs->hw.hfcsx.nt_timer = 0; in hfcsx_bh()
1314 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_bh()
1315 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_bh()
1316 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_bh()
1323 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) in hfcsx_bh()
1324 DChannel_proc_rcv(cs); in hfcsx_bh()
1325 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) in hfcsx_bh()
1326 DChannel_proc_xmt(cs); in hfcsx_bh()
1333 static void inithfcsx(struct IsdnCardState *cs) in inithfcsx() argument
1335 cs->setstack_d = setstack_hfcsx; in inithfcsx()
1336 cs->BC_Send_Data = &hfcsx_send_data; in inithfcsx()
1337 cs->bcs[0].BC_SetStack = setstack_2b; in inithfcsx()
1338 cs->bcs[1].BC_SetStack = setstack_2b; in inithfcsx()
1339 cs->bcs[0].BC_Close = close_hfcsx; in inithfcsx()
1340 cs->bcs[1].BC_Close = close_hfcsx; in inithfcsx()
1341 mode_hfcsx(cs->bcs, 0, 0); in inithfcsx()
1342 mode_hfcsx(cs->bcs + 1, 0, 1); in inithfcsx()
1351 hfcsx_card_msg(struct IsdnCardState *cs, int mt, void *arg) in hfcsx_card_msg() argument
1355 if (cs->debug & L1_DEB_ISAC) in hfcsx_card_msg()
1356 debugl1(cs, "HFCSX: card_msg %x", mt); in hfcsx_card_msg()
1359 spin_lock_irqsave(&cs->lock, flags); in hfcsx_card_msg()
1360 reset_hfcsx(cs); in hfcsx_card_msg()
1361 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_card_msg()
1364 release_io_hfcsx(cs); in hfcsx_card_msg()
1367 spin_lock_irqsave(&cs->lock, flags); in hfcsx_card_msg()
1368 inithfcsx(cs); in hfcsx_card_msg()
1369 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_card_msg()
1372 spin_lock_irqsave(&cs->lock, flags); in hfcsx_card_msg()
1373 cs->hw.hfcsx.int_m1 &= ~HFCSX_INTS_TIMER; in hfcsx_card_msg()
1374 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in hfcsx_card_msg()
1376 Write_hfc(cs, HFCSX_MST_MODE, cs->hw.hfcsx.mst_m); in hfcsx_card_msg()
1377 spin_unlock_irqrestore(&cs->lock, flags); in hfcsx_card_msg()
1399 struct IsdnCardState *cs = card->cs; in setup_hfcsx() local
1446 cs->hw.hfcsx.base = card->para[1] & 0xfffe; in setup_hfcsx()
1447 cs->irq = card->para[0]; in setup_hfcsx()
1448 cs->hw.hfcsx.int_s1 = 0; in setup_hfcsx()
1449 cs->dc.hfcsx.ph_state = 0; in setup_hfcsx()
1450 cs->hw.hfcsx.fifo = 255; in setup_hfcsx()
1451 if ((cs->typ == ISDN_CTYPE_HFC_SX) || in setup_hfcsx()
1452 (cs->typ == ISDN_CTYPE_HFC_SP_PCMCIA)) { in setup_hfcsx()
1453 if ((!cs->hw.hfcsx.base) || !request_region(cs->hw.hfcsx.base, 2, "HFCSX isdn")) { in setup_hfcsx()
1456 cs->hw.hfcsx.base); in setup_hfcsx()
1459 byteout(cs->hw.hfcsx.base, cs->hw.hfcsx.base & 0xFF); in setup_hfcsx()
1460 byteout(cs->hw.hfcsx.base + 1, in setup_hfcsx()
1461 ((cs->hw.hfcsx.base >> 8) & 3) | 0x54); in setup_hfcsx()
1463 cs->hw.hfcsx.chip = Read_hfc(cs, HFCSX_CHIP_ID); in setup_hfcsx()
1464 switch (cs->hw.hfcsx.chip >> 4) { in setup_hfcsx()
1474 cs->hw.hfcsx.chip >> 4); in setup_hfcsx()
1475 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1478 if (!ccd_sp_irqtab[cs->irq & 0xF]) { in setup_hfcsx()
1480 "HFC_SX: invalid irq %d specified\n", cs->irq & 0xF); in setup_hfcsx()
1481 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1484 if (!(cs->hw.hfcsx.extra = in setup_hfcsx()
1486 release_region(cs->hw.hfcsx.base, 2); in setup_hfcsx()
1491 tmp[0], (u_int) cs->hw.hfcsx.base, cs->irq, HZ); in setup_hfcsx()
1492 cs->hw.hfcsx.int_m2 = 0; /* disable alle interrupts */ in setup_hfcsx()
1493 cs->hw.hfcsx.int_m1 = 0; in setup_hfcsx()
1494 Write_hfc(cs, HFCSX_INT_M1, cs->hw.hfcsx.int_m1); in setup_hfcsx()
1495 Write_hfc(cs, HFCSX_INT_M2, cs->hw.hfcsx.int_m2); in setup_hfcsx()
1499 timer_setup(&cs->dbusytimer, hfcsx_dbusy_timer, 0); in setup_hfcsx()
1500 INIT_WORK(&cs->tqueue, hfcsx_bh); in setup_hfcsx()
1501 cs->readisac = NULL; in setup_hfcsx()
1502 cs->writeisac = NULL; in setup_hfcsx()
1503 cs->readisacfifo = NULL; in setup_hfcsx()
1504 cs->writeisacfifo = NULL; in setup_hfcsx()
1505 cs->BC_Read_Reg = NULL; in setup_hfcsx()
1506 cs->BC_Write_Reg = NULL; in setup_hfcsx()
1507 cs->irq_func = &hfcsx_interrupt; in setup_hfcsx()
1509 cs->hw.hfcsx.b_fifo_size = 0; /* fifo size still unknown */ in setup_hfcsx()
1510 cs->hw.hfcsx.cirm = ccd_sp_irqtab[cs->irq & 0xF]; /* RAM not evaluated */ in setup_hfcsx()
1511 timer_setup(&cs->hw.hfcsx.timer, hfcsx_Timer, 0); in setup_hfcsx()
1513 reset_hfcsx(cs); in setup_hfcsx()
1514 cs->cardmsg = &hfcsx_card_msg; in setup_hfcsx()
1515 cs->auxcmd = &hfcsx_auxcmd; in setup_hfcsx()