Lines Matching refs:cs
32 ICCVersion(struct IsdnCardState *cs, char *s) in ICCVersion() argument
36 val = cs->readisac(cs, ICC_RBCH); in ICCVersion()
41 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
43 if (cs->debug & L1_DEB_ISAC) in ph_command()
44 debugl1(cs, "ph_command %x", command); in ph_command()
45 cs->writeisac(cs, ICC_CIX0, (command << 2) | 3); in ph_command()
50 icc_new_ph(struct IsdnCardState *cs) in icc_new_ph() argument
52 switch (cs->dc.icc.ph_state) { in icc_new_ph()
54 ph_command(cs, ICC_CMD_DI); in icc_new_ph()
55 l1_msg(cs, HW_RESET | INDICATION, NULL); in icc_new_ph()
58 l1_msg(cs, HW_DEACTIVATE | CONFIRM, NULL); in icc_new_ph()
61 l1_msg(cs, HW_DEACTIVATE | INDICATION, NULL); in icc_new_ph()
64 l1_msg(cs, HW_POWERUP | CONFIRM, NULL); in icc_new_ph()
67 l1_msg(cs, HW_RSYNC | INDICATION, NULL); in icc_new_ph()
70 l1_msg(cs, HW_INFO2 | INDICATION, NULL); in icc_new_ph()
73 l1_msg(cs, HW_INFO4 | INDICATION, NULL); in icc_new_ph()
83 struct IsdnCardState *cs = in icc_bh() local
87 if (test_and_clear_bit(D_CLEARBUSY, &cs->event)) { in icc_bh()
88 if (cs->debug) in icc_bh()
89 debugl1(cs, "D-Channel Busy cleared"); in icc_bh()
90 stptr = cs->stlist; in icc_bh()
96 if (test_and_clear_bit(D_L1STATECHANGE, &cs->event)) in icc_bh()
97 icc_new_ph(cs); in icc_bh()
98 if (test_and_clear_bit(D_RCVBUFREADY, &cs->event)) in icc_bh()
99 DChannel_proc_rcv(cs); in icc_bh()
100 if (test_and_clear_bit(D_XMTBUFREADY, &cs->event)) in icc_bh()
101 DChannel_proc_xmt(cs); in icc_bh()
103 if (!test_bit(HW_ARCOFI, &cs->HW_Flags)) in icc_bh()
105 if (test_and_clear_bit(D_RX_MON1, &cs->event)) in icc_bh()
106 arcofi_fsm(cs, ARCOFI_RX_END, NULL); in icc_bh()
107 if (test_and_clear_bit(D_TX_MON1, &cs->event)) in icc_bh()
108 arcofi_fsm(cs, ARCOFI_TX_END, NULL); in icc_bh()
113 icc_empty_fifo(struct IsdnCardState *cs, int count) in icc_empty_fifo() argument
117 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) in icc_empty_fifo()
118 debugl1(cs, "icc_empty_fifo"); in icc_empty_fifo()
120 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) { in icc_empty_fifo()
121 if (cs->debug & L1_DEB_WARN) in icc_empty_fifo()
122 debugl1(cs, "icc_empty_fifo overrun %d", in icc_empty_fifo()
123 cs->rcvidx + count); in icc_empty_fifo()
124 cs->writeisac(cs, ICC_CMDR, 0x80); in icc_empty_fifo()
125 cs->rcvidx = 0; in icc_empty_fifo()
128 ptr = cs->rcvbuf + cs->rcvidx; in icc_empty_fifo()
129 cs->rcvidx += count; in icc_empty_fifo()
130 cs->readisacfifo(cs, ptr, count); in icc_empty_fifo()
131 cs->writeisac(cs, ICC_CMDR, 0x80); in icc_empty_fifo()
132 if (cs->debug & L1_DEB_ISAC_FIFO) { in icc_empty_fifo()
133 char *t = cs->dlog; in icc_empty_fifo()
137 debugl1(cs, "%s", cs->dlog); in icc_empty_fifo()
142 icc_fill_fifo(struct IsdnCardState *cs) in icc_fill_fifo() argument
147 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) in icc_fill_fifo()
148 debugl1(cs, "icc_fill_fifo"); in icc_fill_fifo()
150 if (!cs->tx_skb) in icc_fill_fifo()
153 count = cs->tx_skb->len; in icc_fill_fifo()
162 ptr = cs->tx_skb->data; in icc_fill_fifo()
163 skb_pull(cs->tx_skb, count); in icc_fill_fifo()
164 cs->tx_cnt += count; in icc_fill_fifo()
165 cs->writeisacfifo(cs, ptr, count); in icc_fill_fifo()
166 cs->writeisac(cs, ICC_CMDR, more ? 0x8 : 0xa); in icc_fill_fifo()
167 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { in icc_fill_fifo()
168 debugl1(cs, "icc_fill_fifo dbusytimer running"); in icc_fill_fifo()
169 del_timer(&cs->dbusytimer); in icc_fill_fifo()
171 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); in icc_fill_fifo()
172 add_timer(&cs->dbusytimer); in icc_fill_fifo()
173 if (cs->debug & L1_DEB_ISAC_FIFO) { in icc_fill_fifo()
174 char *t = cs->dlog; in icc_fill_fifo()
178 debugl1(cs, "%s", cs->dlog); in icc_fill_fifo()
183 icc_interrupt(struct IsdnCardState *cs, u_char val) in icc_interrupt() argument
189 if (cs->debug & L1_DEB_ISAC) in icc_interrupt()
190 debugl1(cs, "ICC interrupt %x", val); in icc_interrupt()
192 exval = cs->readisac(cs, ICC_RSTA); in icc_interrupt()
195 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
196 debugl1(cs, "ICC RDO"); in icc_interrupt()
198 cs->err_rx++; in icc_interrupt()
202 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
203 debugl1(cs, "ICC CRC error"); in icc_interrupt()
205 cs->err_crc++; in icc_interrupt()
208 cs->writeisac(cs, ICC_CMDR, 0x80); in icc_interrupt()
210 count = cs->readisac(cs, ICC_RBCL) & 0x1f; in icc_interrupt()
213 icc_empty_fifo(cs, count); in icc_interrupt()
214 if ((count = cs->rcvidx) > 0) { in icc_interrupt()
215 cs->rcvidx = 0; in icc_interrupt()
219 skb_put_data(skb, cs->rcvbuf, count); in icc_interrupt()
220 skb_queue_tail(&cs->rq, skb); in icc_interrupt()
224 cs->rcvidx = 0; in icc_interrupt()
225 schedule_event(cs, D_RCVBUFREADY); in icc_interrupt()
228 icc_empty_fifo(cs, 32); in icc_interrupt()
232 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
233 debugl1(cs, "ICC RSC interrupt"); in icc_interrupt()
236 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in icc_interrupt()
237 del_timer(&cs->dbusytimer); in icc_interrupt()
238 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in icc_interrupt()
239 schedule_event(cs, D_CLEARBUSY); in icc_interrupt()
240 if (cs->tx_skb) { in icc_interrupt()
241 if (cs->tx_skb->len) { in icc_interrupt()
242 icc_fill_fifo(cs); in icc_interrupt()
245 dev_kfree_skb_irq(cs->tx_skb); in icc_interrupt()
246 cs->tx_cnt = 0; in icc_interrupt()
247 cs->tx_skb = NULL; in icc_interrupt()
250 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { in icc_interrupt()
251 cs->tx_cnt = 0; in icc_interrupt()
252 icc_fill_fifo(cs); in icc_interrupt()
254 schedule_event(cs, D_XMTBUFREADY); in icc_interrupt()
258 exval = cs->readisac(cs, ICC_CIR0); in icc_interrupt()
259 if (cs->debug & L1_DEB_ISAC) in icc_interrupt()
260 debugl1(cs, "ICC CIR0 %02X", exval); in icc_interrupt()
262 cs->dc.icc.ph_state = (exval >> 2) & 0xf; in icc_interrupt()
263 if (cs->debug & L1_DEB_ISAC) in icc_interrupt()
264 debugl1(cs, "ph_state change %x", cs->dc.icc.ph_state); in icc_interrupt()
265 schedule_event(cs, D_L1STATECHANGE); in icc_interrupt()
268 exval = cs->readisac(cs, ICC_CIR1); in icc_interrupt()
269 if (cs->debug & L1_DEB_ISAC) in icc_interrupt()
270 debugl1(cs, "ICC CIR1 %02X", exval); in icc_interrupt()
275 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
276 debugl1(cs, "ICC SIN interrupt"); in icc_interrupt()
279 exval = cs->readisac(cs, ICC_EXIR); in icc_interrupt()
280 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
281 debugl1(cs, "ICC EXIR %02x", exval); in icc_interrupt()
283 debugl1(cs, "ICC XMR"); in icc_interrupt()
287 debugl1(cs, "ICC XDU"); in icc_interrupt()
290 cs->err_tx++; in icc_interrupt()
292 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in icc_interrupt()
293 del_timer(&cs->dbusytimer); in icc_interrupt()
294 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in icc_interrupt()
295 schedule_event(cs, D_CLEARBUSY); in icc_interrupt()
296 if (cs->tx_skb) { /* Restart frame */ in icc_interrupt()
297 skb_push(cs->tx_skb, cs->tx_cnt); in icc_interrupt()
298 cs->tx_cnt = 0; in icc_interrupt()
299 icc_fill_fifo(cs); in icc_interrupt()
302 debugl1(cs, "ICC XDU no skb"); in icc_interrupt()
306 v1 = cs->readisac(cs, ICC_MOSR); in icc_interrupt()
307 if (cs->debug & L1_DEB_MONITOR) in icc_interrupt()
308 debugl1(cs, "ICC MOSR %02x", v1); in icc_interrupt()
311 if (!cs->dc.icc.mon_rx) { in icc_interrupt()
312 if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) { in icc_interrupt()
313 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
314 debugl1(cs, "ICC MON RX out of memory!"); in icc_interrupt()
315 cs->dc.icc.mocr &= 0xf0; in icc_interrupt()
316 cs->dc.icc.mocr |= 0x0a; in icc_interrupt()
317 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
320 cs->dc.icc.mon_rxp = 0; in icc_interrupt()
322 if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) { in icc_interrupt()
323 cs->dc.icc.mocr &= 0xf0; in icc_interrupt()
324 cs->dc.icc.mocr |= 0x0a; in icc_interrupt()
325 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
326 cs->dc.icc.mon_rxp = 0; in icc_interrupt()
327 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
328 debugl1(cs, "ICC MON RX overflow!"); in icc_interrupt()
331 cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR0); in icc_interrupt()
332 if (cs->debug & L1_DEB_MONITOR) in icc_interrupt()
333 debugl1(cs, "ICC MOR0 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]); in icc_interrupt()
334 if (cs->dc.icc.mon_rxp == 1) { in icc_interrupt()
335 cs->dc.icc.mocr |= 0x04; in icc_interrupt()
336 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
341 if (!cs->dc.icc.mon_rx) { in icc_interrupt()
342 if (!(cs->dc.icc.mon_rx = kmalloc(MAX_MON_FRAME, GFP_ATOMIC))) { in icc_interrupt()
343 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
344 debugl1(cs, "ICC MON RX out of memory!"); in icc_interrupt()
345 cs->dc.icc.mocr &= 0x0f; in icc_interrupt()
346 cs->dc.icc.mocr |= 0xa0; in icc_interrupt()
347 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
350 cs->dc.icc.mon_rxp = 0; in icc_interrupt()
352 if (cs->dc.icc.mon_rxp >= MAX_MON_FRAME) { in icc_interrupt()
353 cs->dc.icc.mocr &= 0x0f; in icc_interrupt()
354 cs->dc.icc.mocr |= 0xa0; in icc_interrupt()
355 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
356 cs->dc.icc.mon_rxp = 0; in icc_interrupt()
357 if (cs->debug & L1_DEB_WARN) in icc_interrupt()
358 debugl1(cs, "ICC MON RX overflow!"); in icc_interrupt()
361 cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp++] = cs->readisac(cs, ICC_MOR1); in icc_interrupt()
362 if (cs->debug & L1_DEB_MONITOR) in icc_interrupt()
363 debugl1(cs, "ICC MOR1 %02x", cs->dc.icc.mon_rx[cs->dc.icc.mon_rxp - 1]); in icc_interrupt()
364 cs->dc.icc.mocr |= 0x40; in icc_interrupt()
365 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
369 cs->dc.icc.mocr &= 0xf0; in icc_interrupt()
370 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
371 cs->dc.icc.mocr |= 0x0a; in icc_interrupt()
372 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
373 schedule_event(cs, D_RX_MON0); in icc_interrupt()
376 cs->dc.icc.mocr &= 0x0f; in icc_interrupt()
377 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
378 cs->dc.icc.mocr |= 0xa0; in icc_interrupt()
379 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
380 schedule_event(cs, D_RX_MON1); in icc_interrupt()
383 if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc && in icc_interrupt()
384 (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) && in icc_interrupt()
386 cs->dc.icc.mocr &= 0xf0; in icc_interrupt()
387 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
388 cs->dc.icc.mocr |= 0x0a; in icc_interrupt()
389 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
390 if (cs->dc.icc.mon_txc && in icc_interrupt()
391 (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) in icc_interrupt()
392 schedule_event(cs, D_TX_MON0); in icc_interrupt()
395 if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) { in icc_interrupt()
396 schedule_event(cs, D_TX_MON0); in icc_interrupt()
399 cs->writeisac(cs, ICC_MOX0, in icc_interrupt()
400 cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]); in icc_interrupt()
401 if (cs->debug & L1_DEB_MONITOR) in icc_interrupt()
402 debugl1(cs, "ICC %02x -> MOX0", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]); in icc_interrupt()
406 if ((!cs->dc.icc.mon_tx) || (cs->dc.icc.mon_txc && in icc_interrupt()
407 (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc) && in icc_interrupt()
409 cs->dc.icc.mocr &= 0x0f; in icc_interrupt()
410 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
411 cs->dc.icc.mocr |= 0xa0; in icc_interrupt()
412 cs->writeisac(cs, ICC_MOCR, cs->dc.icc.mocr); in icc_interrupt()
413 if (cs->dc.icc.mon_txc && in icc_interrupt()
414 (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) in icc_interrupt()
415 schedule_event(cs, D_TX_MON1); in icc_interrupt()
418 if (cs->dc.icc.mon_txc && (cs->dc.icc.mon_txp >= cs->dc.icc.mon_txc)) { in icc_interrupt()
419 schedule_event(cs, D_TX_MON1); in icc_interrupt()
422 cs->writeisac(cs, ICC_MOX1, in icc_interrupt()
423 cs->dc.icc.mon_tx[cs->dc.icc.mon_txp++]); in icc_interrupt()
424 if (cs->debug & L1_DEB_MONITOR) in icc_interrupt()
425 debugl1(cs, "ICC %02x -> MOX1", cs->dc.icc.mon_tx[cs->dc.icc.mon_txp - 1]); in icc_interrupt()
436 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in ICC_l1hw() local
443 if (cs->debug & DEB_DLOG_HEX) in ICC_l1hw()
444 LogFrame(cs, skb->data, skb->len); in ICC_l1hw()
445 if (cs->debug & DEB_DLOG_VERBOSE) in ICC_l1hw()
446 dlogframe(cs, skb, 0); in ICC_l1hw()
447 spin_lock_irqsave(&cs->lock, flags); in ICC_l1hw()
448 if (cs->tx_skb) { in ICC_l1hw()
449 skb_queue_tail(&cs->sq, skb); in ICC_l1hw()
451 if (cs->debug & L1_DEB_LAPD) in ICC_l1hw()
452 Logl2Frame(cs, skb, "PH_DATA Queued", 0); in ICC_l1hw()
455 cs->tx_skb = skb; in ICC_l1hw()
456 cs->tx_cnt = 0; in ICC_l1hw()
458 if (cs->debug & L1_DEB_LAPD) in ICC_l1hw()
459 Logl2Frame(cs, skb, "PH_DATA", 0); in ICC_l1hw()
461 icc_fill_fifo(cs); in ICC_l1hw()
463 spin_unlock_irqrestore(&cs->lock, flags); in ICC_l1hw()
466 spin_lock_irqsave(&cs->lock, flags); in ICC_l1hw()
467 if (cs->tx_skb) { in ICC_l1hw()
468 if (cs->debug & L1_DEB_WARN) in ICC_l1hw()
469 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); in ICC_l1hw()
470 skb_queue_tail(&cs->sq, skb); in ICC_l1hw()
471 spin_unlock_irqrestore(&cs->lock, flags); in ICC_l1hw()
474 if (cs->debug & DEB_DLOG_HEX) in ICC_l1hw()
475 LogFrame(cs, skb->data, skb->len); in ICC_l1hw()
476 if (cs->debug & DEB_DLOG_VERBOSE) in ICC_l1hw()
477 dlogframe(cs, skb, 0); in ICC_l1hw()
478 cs->tx_skb = skb; in ICC_l1hw()
479 cs->tx_cnt = 0; in ICC_l1hw()
481 if (cs->debug & L1_DEB_LAPD) in ICC_l1hw()
482 Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); in ICC_l1hw()
484 icc_fill_fifo(cs); in ICC_l1hw()
485 spin_unlock_irqrestore(&cs->lock, flags); in ICC_l1hw()
489 if (cs->debug & L1_DEB_LAPD) in ICC_l1hw()
490 debugl1(cs, "-> PH_REQUEST_PULL"); in ICC_l1hw()
492 if (!cs->tx_skb) { in ICC_l1hw()
499 spin_lock_irqsave(&cs->lock, flags); in ICC_l1hw()
500 if ((cs->dc.icc.ph_state == ICC_IND_EI1) || in ICC_l1hw()
501 (cs->dc.icc.ph_state == ICC_IND_DR)) in ICC_l1hw()
502 ph_command(cs, ICC_CMD_DI); in ICC_l1hw()
504 ph_command(cs, ICC_CMD_RES); in ICC_l1hw()
505 spin_unlock_irqrestore(&cs->lock, flags); in ICC_l1hw()
508 spin_lock_irqsave(&cs->lock, flags); in ICC_l1hw()
509 ph_command(cs, ICC_CMD_DI); in ICC_l1hw()
510 spin_unlock_irqrestore(&cs->lock, flags); in ICC_l1hw()
513 spin_lock_irqsave(&cs->lock, flags); in ICC_l1hw()
514 ph_command(cs, ICC_CMD_AR); in ICC_l1hw()
515 spin_unlock_irqrestore(&cs->lock, flags); in ICC_l1hw()
518 spin_lock_irqsave(&cs->lock, flags); in ICC_l1hw()
519 ph_command(cs, ICC_CMD_AI); in ICC_l1hw()
520 spin_unlock_irqrestore(&cs->lock, flags); in ICC_l1hw()
523 spin_lock_irqsave(&cs->lock, flags); in ICC_l1hw()
529 if (test_bit(HW_IOM1, &cs->HW_Flags)) { in ICC_l1hw()
532 cs->writeisac(cs, ICC_SPCR, 0xa); in ICC_l1hw()
533 cs->writeisac(cs, ICC_ADF1, 0x2); in ICC_l1hw()
535 cs->writeisac(cs, ICC_SPCR, val); in ICC_l1hw()
536 cs->writeisac(cs, ICC_ADF1, 0xa); in ICC_l1hw()
540 cs->writeisac(cs, ICC_SPCR, val); in ICC_l1hw()
542 cs->writeisac(cs, ICC_ADF1, 0x8); in ICC_l1hw()
544 cs->writeisac(cs, ICC_ADF1, 0x0); in ICC_l1hw()
546 spin_unlock_irqrestore(&cs->lock, flags); in ICC_l1hw()
549 skb_queue_purge(&cs->rq); in ICC_l1hw()
550 skb_queue_purge(&cs->sq); in ICC_l1hw()
551 if (cs->tx_skb) { in ICC_l1hw()
552 dev_kfree_skb_any(cs->tx_skb); in ICC_l1hw()
553 cs->tx_skb = NULL; in ICC_l1hw()
555 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in ICC_l1hw()
556 del_timer(&cs->dbusytimer); in ICC_l1hw()
557 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in ICC_l1hw()
558 schedule_event(cs, D_CLEARBUSY); in ICC_l1hw()
561 if (cs->debug & L1_DEB_WARN) in ICC_l1hw()
562 debugl1(cs, "icc_l1hw unknown %04x", pr); in ICC_l1hw()
568 setstack_icc(struct PStack *st, struct IsdnCardState *cs) in setstack_icc() argument
574 DC_Close_icc(struct IsdnCardState *cs) { in DC_Close_icc() argument
575 kfree(cs->dc.icc.mon_rx); in DC_Close_icc()
576 cs->dc.icc.mon_rx = NULL; in DC_Close_icc()
577 kfree(cs->dc.icc.mon_tx); in DC_Close_icc()
578 cs->dc.icc.mon_tx = NULL; in DC_Close_icc()
584 struct IsdnCardState *cs = from_timer(cs, t, dbusytimer); in dbusy_timer_handler() local
588 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { in dbusy_timer_handler()
589 rbch = cs->readisac(cs, ICC_RBCH); in dbusy_timer_handler()
590 star = cs->readisac(cs, ICC_STAR); in dbusy_timer_handler()
591 if (cs->debug) in dbusy_timer_handler()
592 debugl1(cs, "D-Channel Busy RBCH %02x STAR %02x", in dbusy_timer_handler()
595 test_and_set_bit(FLG_L1_DBUSY, &cs->HW_Flags); in dbusy_timer_handler()
596 stptr = cs->stlist; in dbusy_timer_handler()
603 test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags); in dbusy_timer_handler()
604 if (cs->tx_skb) { in dbusy_timer_handler()
605 dev_kfree_skb_any(cs->tx_skb); in dbusy_timer_handler()
606 cs->tx_cnt = 0; in dbusy_timer_handler()
607 cs->tx_skb = NULL; in dbusy_timer_handler()
610 debugl1(cs, "D-Channel Busy no skb"); in dbusy_timer_handler()
612 cs->writeisac(cs, ICC_CMDR, 0x01); /* Transmitter reset */ in dbusy_timer_handler()
613 cs->irq_func(cs->irq, cs); in dbusy_timer_handler()
619 initicc(struct IsdnCardState *cs) in initicc() argument
621 cs->setstack_d = setstack_icc; in initicc()
622 cs->DC_Close = DC_Close_icc; in initicc()
623 cs->dc.icc.mon_tx = NULL; in initicc()
624 cs->dc.icc.mon_rx = NULL; in initicc()
625 cs->writeisac(cs, ICC_MASK, 0xff); in initicc()
626 cs->dc.icc.mocr = 0xaa; in initicc()
627 if (test_bit(HW_IOM1, &cs->HW_Flags)) { in initicc()
629 cs->writeisac(cs, ICC_ADF2, 0x0); in initicc()
630 cs->writeisac(cs, ICC_SPCR, 0xa); in initicc()
631 cs->writeisac(cs, ICC_ADF1, 0x2); in initicc()
632 cs->writeisac(cs, ICC_STCR, 0x70); in initicc()
633 cs->writeisac(cs, ICC_MODE, 0xc9); in initicc()
636 if (!cs->dc.icc.adf2) in initicc()
637 cs->dc.icc.adf2 = 0x80; in initicc()
638 cs->writeisac(cs, ICC_ADF2, cs->dc.icc.adf2); in initicc()
639 cs->writeisac(cs, ICC_SQXR, 0xa0); in initicc()
640 cs->writeisac(cs, ICC_SPCR, 0x20); in initicc()
641 cs->writeisac(cs, ICC_STCR, 0x70); in initicc()
642 cs->writeisac(cs, ICC_MODE, 0xca); in initicc()
643 cs->writeisac(cs, ICC_TIMR, 0x00); in initicc()
644 cs->writeisac(cs, ICC_ADF1, 0x20); in initicc()
646 ph_command(cs, ICC_CMD_RES); in initicc()
647 cs->writeisac(cs, ICC_MASK, 0x0); in initicc()
648 ph_command(cs, ICC_CMD_DI); in initicc()
652 clear_pending_icc_ints(struct IsdnCardState *cs) in clear_pending_icc_ints() argument
656 val = cs->readisac(cs, ICC_STAR); in clear_pending_icc_ints()
657 debugl1(cs, "ICC STAR %x", val); in clear_pending_icc_ints()
658 val = cs->readisac(cs, ICC_MODE); in clear_pending_icc_ints()
659 debugl1(cs, "ICC MODE %x", val); in clear_pending_icc_ints()
660 val = cs->readisac(cs, ICC_ADF2); in clear_pending_icc_ints()
661 debugl1(cs, "ICC ADF2 %x", val); in clear_pending_icc_ints()
662 val = cs->readisac(cs, ICC_ISTA); in clear_pending_icc_ints()
663 debugl1(cs, "ICC ISTA %x", val); in clear_pending_icc_ints()
665 eval = cs->readisac(cs, ICC_EXIR); in clear_pending_icc_ints()
666 debugl1(cs, "ICC EXIR %x", eval); in clear_pending_icc_ints()
668 val = cs->readisac(cs, ICC_CIR0); in clear_pending_icc_ints()
669 debugl1(cs, "ICC CIR0 %x", val); in clear_pending_icc_ints()
670 cs->dc.icc.ph_state = (val >> 2) & 0xf; in clear_pending_icc_ints()
671 schedule_event(cs, D_L1STATECHANGE); in clear_pending_icc_ints()
673 cs->writeisac(cs, ICC_MASK, 0xFF); in clear_pending_icc_ints()
676 void setup_icc(struct IsdnCardState *cs) in setup_icc() argument
678 INIT_WORK(&cs->tqueue, icc_bh); in setup_icc()
679 timer_setup(&cs->dbusytimer, dbusy_timer_handler, 0); in setup_icc()