Lines Matching refs:cs
35 static void ph_command(struct IsdnCardState *cs, unsigned int command);
36 static inline void cic_int(struct IsdnCardState *cs);
39 static void dch_empty_fifo(struct IsdnCardState *cs, int count);
40 static void dch_fill_fifo(struct IsdnCardState *cs);
41 static inline void dch_int(struct IsdnCardState *cs);
42 static void dch_setstack(struct PStack *st, struct IsdnCardState *cs);
43 static void dch_init(struct IsdnCardState *cs);
47 static void bch_int(struct IsdnCardState *cs, u_char hscx);
50 static int bch_open_state(struct IsdnCardState *cs, struct BCState *bcs);
52 static void bch_init(struct IsdnCardState *cs, int hscx);
53 static void clear_pending_ints(struct IsdnCardState *cs);
59 ph_command(struct IsdnCardState *cs, unsigned int command) in ph_command() argument
61 if (cs->debug & L1_DEB_ISAC) in ph_command()
62 debugl1(cs, "ph_command (%#x) in (%#x)", command, in ph_command()
63 cs->dc.isac.ph_state); in ph_command()
67 cs->writeisac(cs, IPACX_CIX0, (command << 4) | 0x0E); in ph_command()
74 cic_int(struct IsdnCardState *cs) in cic_int() argument
78 event = cs->readisac(cs, IPACX_CIR0) >> 4; in cic_int()
79 if (cs->debug & L1_DEB_ISAC) debugl1(cs, "cic_int(event=%#x)", event); in cic_int()
83 cs->dc.isac.ph_state = event; in cic_int()
84 schedule_event(cs, D_L1STATECHANGE); in cic_int()
97 struct IsdnCardState *cs = (struct IsdnCardState *) st->l1.hardware; in dch_l2l1() local
103 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); in dch_l2l1()
104 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); in dch_l2l1()
105 if (cs->tx_skb) { in dch_l2l1()
106 skb_queue_tail(&cs->sq, skb); in dch_l2l1()
108 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA Queued", 0); in dch_l2l1()
111 cs->tx_skb = skb; in dch_l2l1()
112 cs->tx_cnt = 0; in dch_l2l1()
114 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA", 0); in dch_l2l1()
116 dch_fill_fifo(cs); in dch_l2l1()
121 if (cs->tx_skb) { in dch_l2l1()
122 if (cs->debug & L1_DEB_WARN) in dch_l2l1()
123 debugl1(cs, " l2l1 tx_skb exist this shouldn't happen"); in dch_l2l1()
124 skb_queue_tail(&cs->sq, skb); in dch_l2l1()
127 if (cs->debug & DEB_DLOG_HEX) LogFrame(cs, skb->data, skb->len); in dch_l2l1()
128 if (cs->debug & DEB_DLOG_VERBOSE) dlogframe(cs, skb, 0); in dch_l2l1()
129 cs->tx_skb = skb; in dch_l2l1()
130 cs->tx_cnt = 0; in dch_l2l1()
132 if (cs->debug & L1_DEB_LAPD) Logl2Frame(cs, skb, "PH_DATA_PULLED", 0); in dch_l2l1()
134 dch_fill_fifo(cs); in dch_l2l1()
139 if (cs->debug & L1_DEB_LAPD) debugl1(cs, "-> PH_REQUEST_PULL"); in dch_l2l1()
141 if (!cs->tx_skb) { in dch_l2l1()
150 if ((cs->dc.isac.ph_state == IPACX_IND_RES) || in dch_l2l1()
151 (cs->dc.isac.ph_state == IPACX_IND_DR) || in dch_l2l1()
152 (cs->dc.isac.ph_state == IPACX_IND_DC)) in dch_l2l1()
153 ph_command(cs, IPACX_CMD_TIM); in dch_l2l1()
155 ph_command(cs, IPACX_CMD_RES); in dch_l2l1()
159 ph_command(cs, IPACX_CMD_AR8); in dch_l2l1()
163 cs->writeisac(cs, IPACX_CDA_TSDP10, 0x80); // Timeslot 0 is B1 in dch_l2l1()
164 cs->writeisac(cs, IPACX_CDA_TSDP11, 0x81); // Timeslot 0 is B1 in dch_l2l1()
165 cda1_cr = cs->readisac(cs, IPACX_CDA1_CR); in dch_l2l1()
166 (void) cs->readisac(cs, IPACX_CDA2_CR); in dch_l2l1()
168 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x0a); in dch_l2l1()
171 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x0a); in dch_l2l1()
174 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr | 0x14); in dch_l2l1()
177 cs->writeisac(cs, IPACX_CDA1_CR, cda1_cr & ~0x14); in dch_l2l1()
182 skb_queue_purge(&cs->rq); in dch_l2l1()
183 skb_queue_purge(&cs->sq); in dch_l2l1()
184 if (cs->tx_skb) { in dch_l2l1()
185 dev_kfree_skb_any(cs->tx_skb); in dch_l2l1()
186 cs->tx_skb = NULL; in dch_l2l1()
188 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in dch_l2l1()
189 del_timer(&cs->dbusytimer); in dch_l2l1()
193 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_l2l1 unknown %04x", pr); in dch_l2l1()
203 struct IsdnCardState *cs = from_timer(cs, t, dbusytimer); in dbusy_timer_handler() local
207 if (test_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { in dbusy_timer_handler()
208 rbchd = cs->readisac(cs, IPACX_RBCHD); in dbusy_timer_handler()
209 stard = cs->readisac(cs, IPACX_STARD); in dbusy_timer_handler()
210 if (cs->debug) in dbusy_timer_handler()
211 debugl1(cs, "D-Channel Busy RBCHD %02x STARD %02x", rbchd, stard); in dbusy_timer_handler()
213 set_bit(FLG_L1_DBUSY, &cs->HW_Flags); in dbusy_timer_handler()
214 for (st = cs->stlist; st; st = st->next) { in dbusy_timer_handler()
219 clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags); in dbusy_timer_handler()
220 if (cs->tx_skb) { in dbusy_timer_handler()
221 dev_kfree_skb_any(cs->tx_skb); in dbusy_timer_handler()
222 cs->tx_cnt = 0; in dbusy_timer_handler()
223 cs->tx_skb = NULL; in dbusy_timer_handler()
226 debugl1(cs, "D-Channel Busy no skb"); in dbusy_timer_handler()
228 cs->writeisac(cs, IPACX_CMDRD, 0x01); // Tx reset, generates XPR in dbusy_timer_handler()
237 dch_empty_fifo(struct IsdnCardState *cs, int count) in dch_empty_fifo() argument
241 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) in dch_empty_fifo()
242 debugl1(cs, "dch_empty_fifo()"); in dch_empty_fifo()
245 if ((cs->rcvidx + count) >= MAX_DFRAME_LEN_L1) { in dch_empty_fifo()
246 if (cs->debug & L1_DEB_WARN) in dch_empty_fifo()
247 debugl1(cs, "dch_empty_fifo() incoming message too large"); in dch_empty_fifo()
248 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC in dch_empty_fifo()
249 cs->rcvidx = 0; in dch_empty_fifo()
253 ptr = cs->rcvbuf + cs->rcvidx; in dch_empty_fifo()
254 cs->rcvidx += count; in dch_empty_fifo()
256 cs->readisacfifo(cs, ptr, count); in dch_empty_fifo()
257 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC in dch_empty_fifo()
259 if (cs->debug & L1_DEB_ISAC_FIFO) { in dch_empty_fifo()
260 char *t = cs->dlog; in dch_empty_fifo()
264 debugl1(cs, "%s", cs->dlog); in dch_empty_fifo()
272 dch_fill_fifo(struct IsdnCardState *cs) in dch_fill_fifo() argument
277 if ((cs->debug & L1_DEB_ISAC) && !(cs->debug & L1_DEB_ISAC_FIFO)) in dch_fill_fifo()
278 debugl1(cs, "dch_fill_fifo()"); in dch_fill_fifo()
280 if (!cs->tx_skb) return; in dch_fill_fifo()
281 count = cs->tx_skb->len; in dch_fill_fifo()
291 ptr = cs->tx_skb->data; in dch_fill_fifo()
292 skb_pull(cs->tx_skb, count); in dch_fill_fifo()
293 cs->tx_cnt += count; in dch_fill_fifo()
294 cs->writeisacfifo(cs, ptr, count); in dch_fill_fifo()
295 cs->writeisac(cs, IPACX_CMDRD, cmd); in dch_fill_fifo()
298 if (test_and_set_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) { in dch_fill_fifo()
299 debugl1(cs, "dch_fill_fifo dbusytimer running"); in dch_fill_fifo()
300 del_timer(&cs->dbusytimer); in dch_fill_fifo()
302 cs->dbusytimer.expires = jiffies + ((DBUSY_TIMER_VALUE * HZ)/1000); in dch_fill_fifo()
303 add_timer(&cs->dbusytimer); in dch_fill_fifo()
305 if (cs->debug & L1_DEB_ISAC_FIFO) { in dch_fill_fifo()
306 char *t = cs->dlog; in dch_fill_fifo()
310 debugl1(cs, "%s", cs->dlog); in dch_fill_fifo()
318 dch_int(struct IsdnCardState *cs) in dch_int() argument
324 istad = cs->readisac(cs, IPACX_ISTAD); in dch_int()
330 rstad = cs->readisac(cs, IPACX_RSTAD); in dch_int()
333 if (cs->debug & L1_DEB_WARN) in dch_int()
334 debugl1(cs, "dch_int(): invalid frame"); in dch_int()
336 if (cs->debug & L1_DEB_WARN) in dch_int()
337 debugl1(cs, "dch_int(): RDO"); in dch_int()
339 if (cs->debug & L1_DEB_WARN) in dch_int()
340 debugl1(cs, "dch_int(): CRC error"); in dch_int()
341 cs->writeisac(cs, IPACX_CMDRD, 0x80); // RMC in dch_int()
343 count = cs->readisac(cs, IPACX_RBCLD); in dch_int()
347 dch_empty_fifo(cs, count); in dch_int()
348 if ((count = cs->rcvidx) > 0) { in dch_int()
349 cs->rcvidx = 0; in dch_int()
353 skb_put_data(skb, cs->rcvbuf, count); in dch_int()
354 skb_queue_tail(&cs->rq, skb); in dch_int()
358 cs->rcvidx = 0; in dch_int()
359 schedule_event(cs, D_RCVBUFREADY); in dch_int()
363 dch_empty_fifo(cs, D_FIFO_SIZE); in dch_int()
367 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): RFO"); in dch_int()
368 cs->writeisac(cs, IPACX_CMDRD, 0x40); //RRES in dch_int()
372 if (test_and_clear_bit(FLG_DBUSY_TIMER, &cs->HW_Flags)) in dch_int()
373 del_timer(&cs->dbusytimer); in dch_int()
374 if (test_and_clear_bit(FLG_L1_DBUSY, &cs->HW_Flags)) in dch_int()
375 schedule_event(cs, D_CLEARBUSY); in dch_int()
376 if (cs->tx_skb) { in dch_int()
377 if (cs->tx_skb->len) { in dch_int()
378 dch_fill_fifo(cs); in dch_int()
382 dev_kfree_skb_irq(cs->tx_skb); in dch_int()
383 cs->tx_skb = NULL; in dch_int()
384 cs->tx_cnt = 0; in dch_int()
387 if ((cs->tx_skb = skb_dequeue(&cs->sq))) { in dch_int()
388 cs->tx_cnt = 0; in dch_int()
389 dch_fill_fifo(cs); in dch_int()
392 schedule_event(cs, D_XMTBUFREADY); in dch_int()
398 if (cs->debug & L1_DEB_WARN) debugl1(cs, "dch_int(): XDU"); in dch_int()
399 if (cs->tx_skb) { in dch_int()
400 skb_push(cs->tx_skb, cs->tx_cnt); // retransmit in dch_int()
401 cs->tx_cnt = 0; in dch_int()
402 dch_fill_fifo(cs); in dch_int()
405 debugl1(cs, "ISAC XDU no skb"); in dch_int()
413 dch_setstack(struct PStack *st, struct IsdnCardState *cs) in dch_setstack() argument
421 dch_init(struct IsdnCardState *cs) in dch_init() argument
425 cs->setstack_d = dch_setstack; in dch_init()
427 timer_setup(&cs->dbusytimer, dbusy_timer_handler, 0); in dch_init()
429 cs->writeisac(cs, IPACX_TR_CONF0, 0x00); // clear LDD in dch_init()
430 cs->writeisac(cs, IPACX_TR_CONF2, 0x00); // enable transmitter in dch_init()
431 cs->writeisac(cs, IPACX_MODED, 0xC9); // transparent mode 0, RAC, stop/go in dch_init()
432 cs->writeisac(cs, IPACX_MON_CR, 0x00); // disable monitor channel in dch_init()
452 spin_lock_irqsave(&bcs->cs->lock, flags); in bch_l2l1()
461 spin_unlock_irqrestore(&bcs->cs->lock, flags); in bch_l2l1()
464 spin_lock_irqsave(&bcs->cs->lock, flags); in bch_l2l1()
473 spin_unlock_irqrestore(&bcs->cs->lock, flags); in bch_l2l1()
483 spin_lock_irqsave(&bcs->cs->lock, flags); in bch_l2l1()
486 spin_unlock_irqrestore(&bcs->cs->lock, flags); in bch_l2l1()
493 spin_lock_irqsave(&bcs->cs->lock, flags); in bch_l2l1()
497 spin_unlock_irqrestore(&bcs->cs->lock, flags); in bch_l2l1()
510 struct IsdnCardState *cs; in bch_empty_fifo() local
513 cs = bcs->cs; in bch_empty_fifo()
515 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) in bch_empty_fifo()
516 debugl1(cs, "bch_empty_fifo()"); in bch_empty_fifo()
520 if (cs->debug & L1_DEB_WARN) in bch_empty_fifo()
521 debugl1(cs, "bch_empty_fifo() incoming packet too large"); in bch_empty_fifo()
522 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC in bch_empty_fifo()
529 while (cnt--) *ptr++ = cs->BC_Read_Reg(cs, hscx, IPACX_RFIFOB); in bch_empty_fifo()
530 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC in bch_empty_fifo()
535 if (cs->debug & L1_DEB_HSCX_FIFO) { in bch_empty_fifo()
540 debugl1(cs, "%s", bcs->blog); in bch_empty_fifo()
550 struct IsdnCardState *cs; in bch_fill_fifo() local
554 cs = bcs->cs; in bch_fill_fifo()
555 if ((cs->debug & L1_DEB_HSCX) && !(cs->debug & L1_DEB_HSCX_FIFO)) in bch_fill_fifo()
556 debugl1(cs, "bch_fill_fifo()"); in bch_fill_fifo()
575 while (cnt--) cs->BC_Write_Reg(cs, hscx, IPACX_XFIFOB, *p++); in bch_fill_fifo()
576 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, (more ? 0x08 : 0x0a)); in bch_fill_fifo()
578 if (cs->debug & L1_DEB_HSCX_FIFO) { in bch_fill_fifo()
583 debugl1(cs, "%s", bcs->blog); in bch_fill_fifo()
591 bch_int(struct IsdnCardState *cs, u_char hscx) in bch_int() argument
599 bcs = cs->bcs + hscx; in bch_int()
600 istab = cs->BC_Read_Reg(cs, hscx, IPACX_ISTAB); in bch_int()
607 rstab = cs->BC_Read_Reg(cs, hscx, IPACX_RSTAB); in bch_int()
610 if (cs->debug & L1_DEB_WARN) in bch_int()
611 debugl1(cs, "bch_int() B-%d: invalid frame", hscx); in bch_int()
613 if (cs->debug & L1_DEB_WARN) in bch_int()
614 debugl1(cs, "bch_int() B-%d: RDO mode=%d", hscx, bcs->mode); in bch_int()
616 if (cs->debug & L1_DEB_WARN) in bch_int()
617 debugl1(cs, "bch_int() B-%d: CRC error", hscx); in bch_int()
618 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x80); // RMC in bch_int()
621 count = cs->BC_Read_Reg(cs, hscx, IPACX_RBCLB) & (B_FIFO_SIZE - 1); in bch_int()
625 if (cs->debug & L1_DEB_HSCX_FIFO) in bch_int()
626 debugl1(cs, "bch_int Frame %d", count); in bch_int()
658 if (cs->debug & L1_DEB_WARN) in bch_int()
659 debugl1(cs, "bch_int() B-%d: RFO error", hscx); in bch_int()
660 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x40); // RRES in bch_int()
703 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x01); // XRES in bch_int()
704 if (cs->debug & L1_DEB_WARN) in bch_int()
705 debugl1(cs, "bch_int() B-%d XDU error", hscx); in bch_int()
715 struct IsdnCardState *cs = bcs->cs; in bch_mode() local
719 if (cs->debug & L1_DEB_HSCX) in bch_mode()
720 debugl1(cs, "mode_bch() switch B-%d mode %d chan %d", hscx, mode, bc); in bch_mode()
727 cs->writeisac(cs, IPACX_BCHA_TSDP_BC1, 0x80 | bc); in bch_mode()
728 cs->writeisac(cs, IPACX_BCHA_CR, 0x88); in bch_mode()
732 cs->writeisac(cs, IPACX_BCHB_TSDP_BC1, 0x80 | bc); in bch_mode()
733 cs->writeisac(cs, IPACX_BCHB_CR, 0x88); in bch_mode()
738 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC0); // rec off in bch_mode()
739 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x30); // std adj. in bch_mode()
740 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, 0xFF); // ints off in bch_mode()
741 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments in bch_mode()
744 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0x88); // ext transp mode in bch_mode()
745 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x00); // xxx00000 in bch_mode()
746 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments in bch_mode()
747 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); in bch_mode()
750 cs->BC_Write_Reg(cs, hscx, IPACX_MODEB, 0xC8); // transp mode 0 in bch_mode()
751 cs->BC_Write_Reg(cs, hscx, IPACX_EXMB, 0x01); // idle=hdlc flags crc enabled in bch_mode()
752 cs->BC_Write_Reg(cs, hscx, IPACX_CMDRB, 0x41); // validate adjustments in bch_mode()
753 cs->BC_Write_Reg(cs, hscx, IPACX_MASKB, _MASKB_IMASK); in bch_mode()
782 bch_open_state(struct IsdnCardState *cs, struct BCState *bcs) in bch_open_state() argument
828 bch_init(struct IsdnCardState *cs, int hscx) in bch_init() argument
830 cs->bcs[hscx].BC_SetStack = bch_setstack; in bch_init()
831 cs->bcs[hscx].BC_Close = bch_close_state; in bch_init()
832 cs->bcs[hscx].hw.hscx.hscx = hscx; in bch_init()
833 cs->bcs[hscx].cs = cs; in bch_init()
834 bch_mode(cs->bcs + hscx, 0, hscx); in bch_init()
846 interrupt_ipacx(struct IsdnCardState *cs) in interrupt_ipacx() argument
850 while ((ista = cs->readisac(cs, IPACX_ISTA))) { in interrupt_ipacx()
854 if (ista & 0x80) bch_int(cs, 0); // B channel interrupts in interrupt_ipacx()
855 if (ista & 0x40) bch_int(cs, 1); in interrupt_ipacx()
857 if (ista & 0x01) dch_int(cs); // D channel in interrupt_ipacx()
858 if (ista & 0x10) cic_int(cs); // Layer 1 state in interrupt_ipacx()
866 clear_pending_ints(struct IsdnCardState *cs) in clear_pending_ints() argument
871 cs->writeisac(cs, IPACX_MASK, 0xff); in clear_pending_ints()
872 cs->writeisac(cs, IPACX_MASKD, 0xff); in clear_pending_ints()
873 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, 0xff); in clear_pending_ints()
874 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, 0xff); in clear_pending_ints()
876 ista = cs->readisac(cs, IPACX_ISTA); in clear_pending_ints()
877 if (ista & 0x80) cs->BC_Read_Reg(cs, 0, IPACX_ISTAB); in clear_pending_ints()
878 if (ista & 0x40) cs->BC_Read_Reg(cs, 1, IPACX_ISTAB); in clear_pending_ints()
879 if (ista & 0x10) cs->readisac(cs, IPACX_CIR0); in clear_pending_ints()
880 if (ista & 0x01) cs->readisac(cs, IPACX_ISTAD); in clear_pending_ints()
888 init_ipacx(struct IsdnCardState *cs, int part) in init_ipacx() argument
894 clear_pending_ints(cs); in init_ipacx()
895 bch_init(cs, 0); in init_ipacx()
896 bch_init(cs, 1); in init_ipacx()
897 dch_init(cs); in init_ipacx()
900 cs->BC_Write_Reg(cs, 0, IPACX_MASKB, _MASKB_IMASK); in init_ipacx()
901 cs->BC_Write_Reg(cs, 1, IPACX_MASKB, _MASKB_IMASK); in init_ipacx()
902 cs->writeisac(cs, IPACX_MASKD, _MASKD_IMASK); in init_ipacx()
903 cs->writeisac(cs, IPACX_MASK, _MASK_IMASK); // global mask register in init_ipacx()
906 cs->writeisac(cs, IPACX_CMDRD, 0x41); in init_ipacx()
907 cs->BC_Write_Reg(cs, 0, IPACX_CMDRB, 0x41); in init_ipacx()
908 cs->BC_Write_Reg(cs, 1, IPACX_CMDRB, 0x41); in init_ipacx()
909 ph_command(cs, IPACX_CMD_RES); in init_ipacx()