Lines Matching +full:pdc +full:- +full:global
18 * Broadcom PDC Mailbox Driver
19 * The PDC provides a ring based programming interface to one or more hardware
20 * offload engines. For example, the PDC driver works with both SPU-M and SPU2
21 * cryptographic offload hardware. In some chips the PDC is referred to as MDE,
22 * and in others the FA2/FA+ hardware is used with this PDC driver.
24 * The PDC driver registers with the Linux mailbox framework as a mailbox
25 * controller, once for each PDC instance. Ring 0 for each PDC is registered as
26 * a mailbox channel. The PDC driver uses interrupts to determine when data
27 * transfers to and from an offload engine are complete. The PDC driver uses
31 * The PDC driver allows multiple messages to be pending in the descriptor
35 * an rx interrupt indicates a response is ready, the PDC driver processes numd
53 #include <linux/mailbox/brcm-message.h>
55 #include <linux/dma-direction.h>
56 #include <linux/dma-mapping.h>
63 /* # entries in PDC dma ring */
84 #define PREVTXD(i, max_mask) TXD((i) - 1, (max_mask))
86 #define PREVRXD(i, max_mask) RXD((i) - 1, (max_mask))
87 #define NTXDACTIVE(h, t, max_mask) TXD((t) - (h), (max_mask))
88 #define NRXDACTIVE(h, t, max_mask) RXD((t) - (h), (max_mask))
94 * PDC driver reserves ringset 0 on each SPU for its own use. The driver does
95 * not currently support use of multiple ringsets on a single PDC engine.
126 * 11 - PtyChkDisable - parity check is disabled
127 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
136 * 7:1 - RcvOffset - size in bytes of status region at start of rx frame buf
137 * 9 - SepRxHdrDescEn - place start of new frames only in descriptors
139 * 10 - OflowContinue - on rx FIFO overflow, clear rx fifo, discard all
142 * 11 - PtyChkDisable - parity check is disabled
143 * 20:18 - BurstLen = 3 -> 2^7 = 128 byte data reads from memory
150 #define CRYPTO_D64_RS0_CD_MASK ((PDC_RING_ENTRIES * RING_ENTRY_SIZE) - 1)
169 PDC_HW /* PDC/MDE hardware (i.e. Northstar 2, Pegasus) */
188 u32 addrlow; /* descriptor ring base address low 32-bits */
209 /* PDC registers */
221 u32 intrcvlazy_0; /* 0x030 (Only in PDC, not FA2) */
222 u32 intrcvlazy_1; /* 0x034 (Only in PDC, not FA2) */
223 u32 intrcvlazy_2; /* 0x038 (Only in PDC, not FA2) */
224 u32 intrcvlazy_3; /* 0x03c (Only in PDC, not FA2) */
227 u32 fa_intrecvlazy; /* 0x100 (Only in FA2, not PDC) */
251 u32 PAD[11]; /* 0x1b4-1dc */
253 u32 hw_war; /* 0x1e4 (Only in PDC, not FA2) */
258 struct dma64 dmaregs[PDC_NUM_DMA_RINGS]; /* 0x0200 - 0x2fc */
291 /* PDC state structure */
293 /* Index of the PDC whose state is in this structure instance */
296 /* Platform device for this PDC instance */
300 * Each PDC instance has a mailbox controller. PDC receives request
334 struct pdc_regs *regs; /* start of PDC registers */
409 struct dentry *debugfs_stats; /* debug FS stats file for this PDC */
421 /* hardware type - FA2 or PDC/MDE */
425 /* Global variables */
434 /* top level debug FS directory for PDC driver */
448 return -ENOMEM; in pdc_debugfs_read()
450 pdcs = filp->private_data; in pdc_debugfs_read()
452 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
453 "SPU %u stats:\n", pdcs->pdc_idx); in pdc_debugfs_read()
454 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
455 "PDC requests....................%u\n", in pdc_debugfs_read()
456 pdcs->pdc_requests); in pdc_debugfs_read()
457 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
458 "PDC responses...................%u\n", in pdc_debugfs_read()
459 pdcs->pdc_replies); in pdc_debugfs_read()
460 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
462 pdcs->last_tx_not_done); in pdc_debugfs_read()
463 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
465 pdcs->tx_ring_full); in pdc_debugfs_read()
466 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
468 pdcs->rx_ring_full); in pdc_debugfs_read()
469 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
471 pdcs->txnobuf); in pdc_debugfs_read()
472 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
474 pdcs->rxnobuf); in pdc_debugfs_read()
475 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
477 pdcs->rx_oflow); in pdc_debugfs_read()
478 out_offset += snprintf(buf + out_offset, out_count - out_offset, in pdc_debugfs_read()
480 NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, in pdc_debugfs_read()
481 pdcs->nrxpost)); in pdc_debugfs_read()
498 * pdc_setup_debugfs() - Create the debug FS directories. If the top-level
501 * @pdcs: PDC state structure
510 snprintf(spu_stats_name, 16, "pdc%d_stats", pdcs->pdc_idx); in pdc_setup_debugfs()
515 pdcs->debugfs_stats = debugfs_create_file(spu_stats_name, 0400, in pdc_setup_debugfs()
527 * pdc_build_rxd() - Build DMA descriptor to receive SPU result.
528 * @pdcs: PDC state for SPU that will generate result
537 struct device *dev = &pdcs->pdev->dev; in pdc_build_rxd()
538 struct dma64dd *rxd = &pdcs->rxd_64[pdcs->rxout]; in pdc_build_rxd()
541 "Writing rx descriptor for PDC %u at index %u with length %u. flags %#x\n", in pdc_build_rxd()
542 pdcs->pdc_idx, pdcs->rxout, buf_len, flags); in pdc_build_rxd()
544 rxd->addrlow = cpu_to_le32(lower_32_bits(dma_addr)); in pdc_build_rxd()
545 rxd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); in pdc_build_rxd()
546 rxd->ctrl1 = cpu_to_le32(flags); in pdc_build_rxd()
547 rxd->ctrl2 = cpu_to_le32(buf_len); in pdc_build_rxd()
550 pdcs->rxout = NEXTRXD(pdcs->rxout, pdcs->nrxpost); in pdc_build_rxd()
554 * pdc_build_txd() - Build a DMA descriptor to transmit a SPU request to
556 * @pdcs: PDC state for the SPU that will process this request
565 struct device *dev = &pdcs->pdev->dev; in pdc_build_txd()
566 struct dma64dd *txd = &pdcs->txd_64[pdcs->txout]; in pdc_build_txd()
569 "Writing tx descriptor for PDC %u at index %u with length %u, flags %#x\n", in pdc_build_txd()
570 pdcs->pdc_idx, pdcs->txout, buf_len, flags); in pdc_build_txd()
572 txd->addrlow = cpu_to_le32(lower_32_bits(dma_addr)); in pdc_build_txd()
573 txd->addrhigh = cpu_to_le32(upper_32_bits(dma_addr)); in pdc_build_txd()
574 txd->ctrl1 = cpu_to_le32(flags); in pdc_build_txd()
575 txd->ctrl2 = cpu_to_le32(buf_len); in pdc_build_txd()
578 pdcs->txout = NEXTTXD(pdcs->txout, pdcs->ntxpost); in pdc_build_txd()
582 * pdc_receive_one() - Receive a response message from a given SPU.
583 * @pdcs: PDC state for the SPU to receive from
589 * -EAGAIN indicates that no response message is available
590 * -EIO an error occurred
595 struct device *dev = &pdcs->pdev->dev; in pdc_receive_one()
607 mbc = &pdcs->mbc; in pdc_receive_one()
608 chan = &mbc->chans[0]; in pdc_receive_one()
616 frags_rdy = NRXDACTIVE(pdcs->rxin, pdcs->last_rx_curr, pdcs->nrxpost); in pdc_receive_one()
618 (frags_rdy < pdcs->rx_ctx[pdcs->rxin].rxin_numd)) in pdc_receive_one()
620 return -EAGAIN; in pdc_receive_one()
622 num_frags = pdcs->txin_numd[pdcs->txin]; in pdc_receive_one()
625 dma_unmap_sg(dev, pdcs->src_sg[pdcs->txin], in pdc_receive_one()
626 sg_nents(pdcs->src_sg[pdcs->txin]), DMA_TO_DEVICE); in pdc_receive_one()
628 pdcs->txin = (pdcs->txin + num_frags) & pdcs->ntxpost; in pdc_receive_one()
630 dev_dbg(dev, "PDC %u reclaimed %d tx descriptors", in pdc_receive_one()
631 pdcs->pdc_idx, num_frags); in pdc_receive_one()
633 rx_idx = pdcs->rxin; in pdc_receive_one()
634 rx_ctx = &pdcs->rx_ctx[rx_idx]; in pdc_receive_one()
635 num_frags = rx_ctx->rxin_numd; in pdc_receive_one()
637 mssg.ctx = rx_ctx->rxp_ctx; in pdc_receive_one()
638 rx_ctx->rxp_ctx = NULL; in pdc_receive_one()
639 resp_hdr = rx_ctx->resp_hdr; in pdc_receive_one()
640 resp_hdr_daddr = rx_ctx->resp_hdr_daddr; in pdc_receive_one()
641 dma_unmap_sg(dev, rx_ctx->dst_sg, sg_nents(rx_ctx->dst_sg), in pdc_receive_one()
644 pdcs->rxin = (pdcs->rxin + num_frags) & pdcs->nrxpost; in pdc_receive_one()
646 dev_dbg(dev, "PDC %u reclaimed %d rx descriptors", in pdc_receive_one()
647 pdcs->pdc_idx, num_frags); in pdc_receive_one()
650 "PDC %u txin %u, txout %u, rxin %u, rxout %u, last_rx_curr %u\n", in pdc_receive_one()
651 pdcs->pdc_idx, pdcs->txin, pdcs->txout, pdcs->rxin, in pdc_receive_one()
652 pdcs->rxout, pdcs->last_rx_curr); in pdc_receive_one()
654 if (pdcs->pdc_resp_hdr_len == PDC_SPUM_RESP_HDR_LEN) { in pdc_receive_one()
656 * For SPU-M, get length of response msg and rx overflow status. in pdc_receive_one()
666 pdcs->rx_oflow++; in pdc_receive_one()
670 return -EIO; in pdc_receive_one()
674 dma_pool_free(pdcs->rx_buf_pool, resp_hdr, resp_hdr_daddr); in pdc_receive_one()
678 pdcs->pdc_replies++; in pdc_receive_one()
683 * pdc_receive() - Process as many responses as are available in the rx ring.
684 * @pdcs: PDC state
695 pdcs->last_rx_curr = in pdc_receive()
696 (ioread32(&pdcs->rxregs_64->status0) & in pdc_receive()
708 * pdc_tx_list_sg_add() - Add the buffers in a scatterlist to the transmit
738 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, in pdc_tx_list_sg_add()
739 pdcs->ntxpost); in pdc_tx_list_sg_add()
741 pdcs->txnobuf++; in pdc_tx_list_sg_add()
742 return -ENOSPC; in pdc_tx_list_sg_add()
746 if (pdcs->tx_msg_start == pdcs->txout) { in pdc_tx_list_sg_add()
748 pdcs->txin_numd[pdcs->tx_msg_start] = 0; in pdc_tx_list_sg_add()
749 pdcs->src_sg[pdcs->txout] = sg; in pdc_tx_list_sg_add()
754 if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) in pdc_tx_list_sg_add()
760 * If sg buffer larger than PDC limit, split across in pdc_tx_list_sg_add()
769 bufcnt -= PDC_DMA_BUF_MAX; in pdc_tx_list_sg_add()
771 if (unlikely(pdcs->txout == (pdcs->ntxd - 1))) in pdc_tx_list_sg_add()
785 pdcs->txin_numd[pdcs->tx_msg_start] += desc_w; in pdc_tx_list_sg_add()
791 * pdc_tx_list_final() - Initiate DMA transfer of last frame written to tx
793 * @pdcs: PDC state for SPU to process the request
806 iowrite32(pdcs->rxout << 4, &pdcs->rxregs_64->ptr); in pdc_tx_list_final()
807 iowrite32(pdcs->txout << 4, &pdcs->txregs_64->ptr); in pdc_tx_list_final()
808 pdcs->pdc_requests++; in pdc_tx_list_final()
814 * pdc_rx_list_init() - Start a new receive descriptor list for a given PDC.
815 * @pdcs: PDC state for SPU handling request
821 * response. For example, with SPU-M, the metadata is a 32-byte DMA header and
822 * an 8-byte BCM header. Moves the msg_start descriptor indexes for both tx and
838 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rx_list_init()
839 pdcs->nrxpost); in pdc_rx_list_init()
841 pdcs->rxnobuf++; in pdc_rx_list_init()
842 return -ENOSPC; in pdc_rx_list_init()
846 vaddr = dma_pool_zalloc(pdcs->rx_buf_pool, GFP_ATOMIC, &daddr); in pdc_rx_list_init()
848 return -ENOMEM; in pdc_rx_list_init()
855 pdcs->rx_msg_start = pdcs->rxout; in pdc_rx_list_init()
856 pdcs->tx_msg_start = pdcs->txout; in pdc_rx_list_init()
860 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd = 1; in pdc_rx_list_init()
862 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_init()
865 rx_ctx = &pdcs->rx_ctx[pdcs->rxout]; in pdc_rx_list_init()
866 rx_ctx->rxp_ctx = ctx; in pdc_rx_list_init()
867 rx_ctx->dst_sg = dst_sg; in pdc_rx_list_init()
868 rx_ctx->resp_hdr = vaddr; in pdc_rx_list_init()
869 rx_ctx->resp_hdr_daddr = daddr; in pdc_rx_list_init()
870 pdc_build_rxd(pdcs, daddr, pdcs->pdc_resp_hdr_len, flags); in pdc_rx_list_init()
875 * pdc_rx_list_sg_add() - Add the buffers in a scatterlist to the receive
904 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rx_list_sg_add()
905 pdcs->nrxpost); in pdc_rx_list_sg_add()
907 pdcs->rxnobuf++; in pdc_rx_list_sg_add()
908 return -ENOSPC; in pdc_rx_list_sg_add()
912 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_sg_add()
918 * If sg buffer larger than PDC limit, split across in pdc_rx_list_sg_add()
926 bufcnt -= PDC_DMA_BUF_MAX; in pdc_rx_list_sg_add()
928 if (unlikely(pdcs->rxout == (pdcs->nrxd - 1))) in pdc_rx_list_sg_add()
937 pdcs->rx_ctx[pdcs->rx_msg_start].rxin_numd += desc_w; in pdc_rx_list_sg_add()
943 * pdc_irq_handler() - Interrupt handler called in interrupt context.
958 u32 intstatus = ioread32(pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); in pdc_irq_handler()
964 iowrite32(0, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_irq_handler()
967 iowrite32(intstatus, pdcs->pdc_reg_vbase + PDC_INTSTATUS_OFFSET); in pdc_irq_handler()
970 tasklet_schedule(&pdcs->rx_tasklet); in pdc_irq_handler()
975 * pdc_tasklet_cb() - Tasklet callback that runs the deferred processing after
977 * @data: PDC state structure
986 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_tasklet_cb()
990 * pdc_ring_init() - Allocate DMA rings and initialize constant fields of
992 * @pdcs: PDC instance state
1003 struct device *dev = &pdcs->pdev->dev; in pdc_ring_init()
1008 tx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &tx.dmabase); in pdc_ring_init()
1010 err = -ENOMEM; in pdc_ring_init()
1015 rx.vbase = dma_pool_zalloc(pdcs->ring_pool, GFP_KERNEL, &rx.dmabase); in pdc_ring_init()
1017 err = -ENOMEM; in pdc_ring_init()
1021 dev_dbg(dev, " - base DMA addr of tx ring %pad", &tx.dmabase); in pdc_ring_init()
1022 dev_dbg(dev, " - base virtual addr of tx ring %p", tx.vbase); in pdc_ring_init()
1023 dev_dbg(dev, " - base DMA addr of rx ring %pad", &rx.dmabase); in pdc_ring_init()
1024 dev_dbg(dev, " - base virtual addr of rx ring %p", rx.vbase); in pdc_ring_init()
1026 memcpy(&pdcs->tx_ring_alloc, &tx, sizeof(tx)); in pdc_ring_init()
1027 memcpy(&pdcs->rx_ring_alloc, &rx, sizeof(rx)); in pdc_ring_init()
1029 pdcs->rxin = 0; in pdc_ring_init()
1030 pdcs->rx_msg_start = 0; in pdc_ring_init()
1031 pdcs->last_rx_curr = 0; in pdc_ring_init()
1032 pdcs->rxout = 0; in pdc_ring_init()
1033 pdcs->txin = 0; in pdc_ring_init()
1034 pdcs->tx_msg_start = 0; in pdc_ring_init()
1035 pdcs->txout = 0; in pdc_ring_init()
1038 pdcs->txd_64 = (struct dma64dd *)pdcs->tx_ring_alloc.vbase; in pdc_ring_init()
1039 pdcs->rxd_64 = (struct dma64dd *)pdcs->rx_ring_alloc.vbase; in pdc_ring_init()
1042 dma_reg = &pdcs->regs->dmaregs[ringset]; in pdc_ring_init()
1045 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_ring_init()
1046 iowrite32((PDC_RX_CTL + (pdcs->rx_status_len << 1)), in pdc_ring_init()
1047 &dma_reg->dmarcv.control); in pdc_ring_init()
1048 iowrite32(0, &dma_reg->dmaxmt.ptr); in pdc_ring_init()
1049 iowrite32(0, &dma_reg->dmarcv.ptr); in pdc_ring_init()
1052 iowrite32(lower_32_bits(pdcs->tx_ring_alloc.dmabase), in pdc_ring_init()
1053 &dma_reg->dmaxmt.addrlow); in pdc_ring_init()
1054 iowrite32(upper_32_bits(pdcs->tx_ring_alloc.dmabase), in pdc_ring_init()
1055 &dma_reg->dmaxmt.addrhigh); in pdc_ring_init()
1057 iowrite32(lower_32_bits(pdcs->rx_ring_alloc.dmabase), in pdc_ring_init()
1058 &dma_reg->dmarcv.addrlow); in pdc_ring_init()
1059 iowrite32(upper_32_bits(pdcs->rx_ring_alloc.dmabase), in pdc_ring_init()
1060 &dma_reg->dmarcv.addrhigh); in pdc_ring_init()
1062 /* Re-enable DMA */ in pdc_ring_init()
1063 iowrite32(PDC_TX_CTL | PDC_TX_ENABLE, &dma_reg->dmaxmt.control); in pdc_ring_init()
1064 iowrite32((PDC_RX_CTL | PDC_RX_ENABLE | (pdcs->rx_status_len << 1)), in pdc_ring_init()
1065 &dma_reg->dmarcv.control); in pdc_ring_init()
1070 if (i != pdcs->ntxpost) { in pdc_ring_init()
1072 &pdcs->txd_64[i].ctrl1); in pdc_ring_init()
1076 D64_CTRL1_EOT, &pdcs->txd_64[i].ctrl1); in pdc_ring_init()
1080 if (i != pdcs->nrxpost) { in pdc_ring_init()
1082 &pdcs->rxd_64[i].ctrl1); in pdc_ring_init()
1086 &pdcs->rxd_64[i].ctrl1); in pdc_ring_init()
1092 dma_pool_free(pdcs->ring_pool, tx.vbase, tx.dmabase); in pdc_ring_init()
1099 if (pdcs->tx_ring_alloc.vbase) { in pdc_ring_free()
1100 dma_pool_free(pdcs->ring_pool, pdcs->tx_ring_alloc.vbase, in pdc_ring_free()
1101 pdcs->tx_ring_alloc.dmabase); in pdc_ring_free()
1102 pdcs->tx_ring_alloc.vbase = NULL; in pdc_ring_free()
1105 if (pdcs->rx_ring_alloc.vbase) { in pdc_ring_free()
1106 dma_pool_free(pdcs->ring_pool, pdcs->rx_ring_alloc.vbase, in pdc_ring_free()
1107 pdcs->rx_ring_alloc.dmabase); in pdc_ring_free()
1108 pdcs->rx_ring_alloc.vbase = NULL; in pdc_ring_free()
1113 * pdc_desc_count() - Count the number of DMA descriptors that will be required
1123 cnt += ((sg->length / PDC_DMA_BUF_MAX) + 1); in pdc_desc_count()
1130 * pdc_rings_full() - Check whether the tx ring has room for tx_cnt descriptors
1132 * @pdcs: PDC state
1146 rx_avail = pdcs->nrxpost - NRXDACTIVE(pdcs->rxin, pdcs->rxout, in pdc_rings_full()
1147 pdcs->nrxpost); in pdc_rings_full()
1149 pdcs->rx_ring_full++; in pdc_rings_full()
1154 tx_avail = pdcs->ntxpost - NTXDACTIVE(pdcs->txin, pdcs->txout, in pdc_rings_full()
1155 pdcs->ntxpost); in pdc_rings_full()
1157 pdcs->tx_ring_full++; in pdc_rings_full()
1165 * pdc_last_tx_done() - If both the tx and rx rings have at least
1169 * Return: true if PDC can accept another message on this channel
1173 struct pdc_state *pdcs = chan->con_priv; in pdc_last_tx_done()
1178 pdcs->last_tx_not_done++; in pdc_last_tx_done()
1187 * pdc_send_data() - mailbox send_data function
1204 * -ENOTSUPP if the mailbox message is a type this driver does not
1210 struct pdc_state *pdcs = chan->con_priv; in pdc_send_data()
1211 struct device *dev = &pdcs->pdev->dev; in pdc_send_data()
1220 if (unlikely(mssg->type != BRCM_MESSAGE_SPU)) in pdc_send_data()
1221 return -ENOTSUPP; in pdc_send_data()
1223 src_nent = sg_nents(mssg->spu.src); in pdc_send_data()
1225 nent = dma_map_sg(dev, mssg->spu.src, src_nent, DMA_TO_DEVICE); in pdc_send_data()
1227 return -EIO; in pdc_send_data()
1230 dst_nent = sg_nents(mssg->spu.dst); in pdc_send_data()
1232 nent = dma_map_sg(dev, mssg->spu.dst, dst_nent, in pdc_send_data()
1235 dma_unmap_sg(dev, mssg->spu.src, src_nent, in pdc_send_data()
1237 return -EIO; in pdc_send_data()
1250 tx_desc_req = pdc_desc_count(mssg->spu.src); in pdc_send_data()
1251 rx_desc_req = pdc_desc_count(mssg->spu.dst); in pdc_send_data()
1253 return -ENOSPC; in pdc_send_data()
1256 err = pdc_rx_list_init(pdcs, mssg->spu.dst, mssg->ctx); in pdc_send_data()
1257 err |= pdc_rx_list_sg_add(pdcs, mssg->spu.dst); in pdc_send_data()
1260 err |= pdc_tx_list_sg_add(pdcs, mssg->spu.src); in pdc_send_data()
1264 dev_err(&pdcs->pdev->dev, in pdc_send_data()
1272 return pdc_ring_init(chan->con_priv, PDC_RINGSET); in pdc_startup()
1277 struct pdc_state *pdcs = chan->con_priv; in pdc_shutdown()
1282 dev_dbg(&pdcs->pdev->dev, in pdc_shutdown()
1283 "Shutdown mailbox channel for PDC %u", pdcs->pdc_idx); in pdc_shutdown()
1288 * pdc_hw_init() - Use the given initialization parameters to initialize the
1290 * @pdcs: state of the PDC
1300 pdev = pdcs->pdev; in pdc_hw_init()
1301 dev = &pdev->dev; in pdc_hw_init()
1303 dev_dbg(dev, "PDC %u initial values:", pdcs->pdc_idx); in pdc_hw_init()
1306 dev_dbg(dev, " - base virtual addr of hw regs %p", in pdc_hw_init()
1307 pdcs->pdc_reg_vbase); in pdc_hw_init()
1310 pdcs->regs = (struct pdc_regs *)pdcs->pdc_reg_vbase; in pdc_hw_init()
1311 pdcs->txregs_64 = (struct dma64_regs *) in pdc_hw_init()
1312 (((u8 *)pdcs->pdc_reg_vbase) + in pdc_hw_init()
1314 pdcs->rxregs_64 = (struct dma64_regs *) in pdc_hw_init()
1315 (((u8 *)pdcs->pdc_reg_vbase) + in pdc_hw_init()
1318 pdcs->ntxd = PDC_RING_ENTRIES; in pdc_hw_init()
1319 pdcs->nrxd = PDC_RING_ENTRIES; in pdc_hw_init()
1320 pdcs->ntxpost = PDC_RING_ENTRIES - 1; in pdc_hw_init()
1321 pdcs->nrxpost = PDC_RING_ENTRIES - 1; in pdc_hw_init()
1322 iowrite32(0, &pdcs->regs->intmask); in pdc_hw_init()
1324 dma_reg = &pdcs->regs->dmaregs[ringset]; in pdc_hw_init()
1327 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_hw_init()
1329 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), in pdc_hw_init()
1330 &dma_reg->dmarcv.control); in pdc_hw_init()
1333 iowrite32(0, &dma_reg->dmaxmt.ptr); in pdc_hw_init()
1334 iowrite32(0, &dma_reg->dmarcv.ptr); in pdc_hw_init()
1336 if (pdcs->pdc_resp_hdr_len == PDC_SPU2_RESP_HDR_LEN) in pdc_hw_init()
1338 pdcs->pdc_reg_vbase + PDC_CKSUM_CTRL_OFFSET); in pdc_hw_init()
1342 * pdc_hw_disable() - Disable the tx and rx control in the hw.
1343 * @pdcs: PDC state structure
1350 dma_reg = &pdcs->regs->dmaregs[PDC_RINGSET]; in pdc_hw_disable()
1351 iowrite32(PDC_TX_CTL, &dma_reg->dmaxmt.control); in pdc_hw_disable()
1352 iowrite32(PDC_RX_CTL + (pdcs->rx_status_len << 1), in pdc_hw_disable()
1353 &dma_reg->dmarcv.control); in pdc_hw_disable()
1357 * pdc_rx_buf_pool_create() - Pool of receive buffers used to catch the metadata
1359 * @pdcs: PDC state structure
1361 * The metadata is not returned to the mailbox client. So the PDC driver
1365 * -ENOMEM if pool creation fails
1372 pdev = pdcs->pdev; in pdc_rx_buf_pool_create()
1373 dev = &pdev->dev; in pdc_rx_buf_pool_create()
1375 pdcs->pdc_resp_hdr_len = pdcs->rx_status_len; in pdc_rx_buf_pool_create()
1376 if (pdcs->use_bcm_hdr) in pdc_rx_buf_pool_create()
1377 pdcs->pdc_resp_hdr_len += BCM_HDR_LEN; in pdc_rx_buf_pool_create()
1379 pdcs->rx_buf_pool = dma_pool_create("pdc rx bufs", dev, in pdc_rx_buf_pool_create()
1380 pdcs->pdc_resp_hdr_len, in pdc_rx_buf_pool_create()
1382 if (!pdcs->rx_buf_pool) in pdc_rx_buf_pool_create()
1383 return -ENOMEM; in pdc_rx_buf_pool_create()
1389 * pdc_interrupts_init() - Initialize the interrupt configuration for a PDC and
1392 * @pdcs: PDC state
1402 struct platform_device *pdev = pdcs->pdev; in pdc_interrupts_init()
1403 struct device *dev = &pdev->dev; in pdc_interrupts_init()
1404 struct device_node *dn = pdev->dev.of_node; in pdc_interrupts_init()
1408 iowrite32(PDC_INTMASK, pdcs->pdc_reg_vbase + PDC_INTMASK_OFFSET); in pdc_interrupts_init()
1410 if (pdcs->hw_type == FA_HW) in pdc_interrupts_init()
1411 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + in pdc_interrupts_init()
1414 iowrite32(PDC_LAZY_INT, pdcs->pdc_reg_vbase + in pdc_interrupts_init()
1418 pdcs->pdc_irq = irq_of_parse_and_map(dn, 0); in pdc_interrupts_init()
1419 dev_dbg(dev, "pdc device %s irq %u for pdcs %p", in pdc_interrupts_init()
1420 dev_name(dev), pdcs->pdc_irq, pdcs); in pdc_interrupts_init()
1422 err = devm_request_irq(dev, pdcs->pdc_irq, pdc_irq_handler, 0, in pdc_interrupts_init()
1426 pdcs->pdc_irq, err); in pdc_interrupts_init()
1440 * pdc_mb_init() - Initialize the mailbox controller.
1441 * @pdcs: PDC state
1443 * Each PDC is a mailbox controller. Each ringset is a mailbox channel. Kernel
1444 * driver only uses one ringset and thus one mb channel. PDC uses the transmit
1453 struct device *dev = &pdcs->pdev->dev; in pdc_mb_init()
1458 mbc = &pdcs->mbc; in pdc_mb_init()
1459 mbc->dev = dev; in pdc_mb_init()
1460 mbc->ops = &pdc_mbox_chan_ops; in pdc_mb_init()
1461 mbc->num_chans = 1; in pdc_mb_init()
1462 mbc->chans = devm_kcalloc(dev, mbc->num_chans, sizeof(*mbc->chans), in pdc_mb_init()
1464 if (!mbc->chans) in pdc_mb_init()
1465 return -ENOMEM; in pdc_mb_init()
1467 mbc->txdone_irq = false; in pdc_mb_init()
1468 mbc->txdone_poll = true; in pdc_mb_init()
1469 mbc->txpoll_period = 1; in pdc_mb_init()
1470 for (chan_index = 0; chan_index < mbc->num_chans; chan_index++) in pdc_mb_init()
1471 mbc->chans[chan_index].con_priv = pdcs; in pdc_mb_init()
1477 "Failed to register PDC mailbox controller. Error %d.", in pdc_mb_init()
1489 {.compatible = "brcm,iproc-pdc-mbox", .data = &pdc_hw},
1490 {.compatible = "brcm,iproc-fa2-mbox", .data = &fa_hw},
1496 * pdc_dt_read() - Read application-specific data from device tree.
1498 * @pdcs: PDC state
1501 * Reads whether transmit and received frames should be preceded by an 8-byte
1505 * -ENODEV if device not available
1509 struct device *dev = &pdev->dev; in pdc_dt_read()
1510 struct device_node *dn = pdev->dev.of_node; in pdc_dt_read()
1515 err = of_property_read_u32(dn, "brcm,rx-status-len", in pdc_dt_read()
1516 &pdcs->rx_status_len); in pdc_dt_read()
1522 pdcs->use_bcm_hdr = of_property_read_bool(dn, "brcm,use-bcm-hdr"); in pdc_dt_read()
1524 pdcs->hw_type = PDC_HW; in pdc_dt_read()
1528 hw_type = match->data; in pdc_dt_read()
1529 pdcs->hw_type = *hw_type; in pdc_dt_read()
1536 * pdc_probe() - Probe function for PDC driver.
1537 * @pdev: PDC platform device
1541 * Initialize a mailbox controller for each PDC.
1549 struct device *dev = &pdev->dev; in pdc_probe()
1553 /* PDC state for one SPU */ in pdc_probe()
1556 err = -ENOMEM; in pdc_probe()
1560 pdcs->pdev = pdev; in pdc_probe()
1562 pdcs->pdc_idx = pdcg.num_spu; in pdc_probe()
1567 dev_warn(dev, "PDC device cannot perform DMA. Error %d.", err); in pdc_probe()
1572 pdcs->ring_pool = dma_pool_create("pdc rings", dev, PDC_RING_SIZE, in pdc_probe()
1574 if (!pdcs->ring_pool) { in pdc_probe()
1575 err = -ENOMEM; in pdc_probe()
1585 err = -ENODEV; in pdc_probe()
1588 dev_dbg(dev, "PDC register region res.start = %pa, res.end = %pa", in pdc_probe()
1589 &pdc_regs->start, &pdc_regs->end); in pdc_probe()
1591 pdcs->pdc_reg_vbase = devm_ioremap_resource(&pdev->dev, pdc_regs); in pdc_probe()
1592 if (IS_ERR(pdcs->pdc_reg_vbase)) { in pdc_probe()
1593 err = PTR_ERR(pdcs->pdc_reg_vbase); in pdc_probe()
1594 dev_err(&pdev->dev, "Failed to map registers: %d\n", err); in pdc_probe()
1606 tasklet_init(&pdcs->rx_tasklet, pdc_tasklet_cb, (unsigned long)pdcs); in pdc_probe()
1617 pdcs->debugfs_stats = NULL; in pdc_probe()
1624 tasklet_kill(&pdcs->rx_tasklet); in pdc_probe()
1625 dma_pool_destroy(pdcs->rx_buf_pool); in pdc_probe()
1628 dma_pool_destroy(pdcs->ring_pool); in pdc_probe()
1640 tasklet_kill(&pdcs->rx_tasklet); in pdc_remove()
1644 mbox_controller_unregister(&pdcs->mbc); in pdc_remove()
1646 dma_pool_destroy(pdcs->rx_buf_pool); in pdc_remove()
1647 dma_pool_destroy(pdcs->ring_pool); in pdc_remove()
1655 .name = "brcm-iproc-pdc-mbox",
1662 MODULE_DESCRIPTION("Broadcom PDC mailbox driver");