Lines Matching +full:mu +full:- +full:side +full:- +full:b
1 // SPDX-License-Identifier: GPL-2.0
21 #define IMX_MU_xSR_GIPn(x) BIT(28 + (3 - (x)))
22 #define IMX_MU_xSR_RFn(x) BIT(24 + (3 - (x)))
23 #define IMX_MU_xSR_TEn(x) BIT(20 + (3 - (x)))
29 #define IMX_MU_xCR_GIEn(x) BIT(28 + (3 - (x)))
31 #define IMX_MU_xCR_RIEn(x) BIT(24 + (3 - (x)))
33 #define IMX_MU_xCR_TIEn(x) BIT(20 + (3 - (x)))
35 #define IMX_MU_xCR_GIRn(x) BIT(16 + (3 - (x)))
77 iowrite32(val, priv->base + offs); in imx_mu_write()
82 return ioread32(priv->base + offs); in imx_mu_read()
90 spin_lock_irqsave(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
95 spin_unlock_irqrestore(&priv->xcr_lock, flags); in imx_mu_xcr_rmw()
104 mbox_chan_txdone(cp->chan, 0); in imx_mu_txdb_tasklet()
110 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_isr()
111 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_isr()
117 switch (cp->type) { in imx_mu_isr()
119 val &= IMX_MU_xSR_TEn(cp->idx) & in imx_mu_isr()
120 (ctrl & IMX_MU_xCR_TIEn(cp->idx)); in imx_mu_isr()
123 val &= IMX_MU_xSR_RFn(cp->idx) & in imx_mu_isr()
124 (ctrl & IMX_MU_xCR_RIEn(cp->idx)); in imx_mu_isr()
127 val &= IMX_MU_xSR_GIPn(cp->idx) & in imx_mu_isr()
128 (ctrl & IMX_MU_xCR_GIEn(cp->idx)); in imx_mu_isr()
137 if (val == IMX_MU_xSR_TEn(cp->idx)) { in imx_mu_isr()
138 imx_mu_xcr_rmw(priv, 0, IMX_MU_xCR_TIEn(cp->idx)); in imx_mu_isr()
140 } else if (val == IMX_MU_xSR_RFn(cp->idx)) { in imx_mu_isr()
141 dat = imx_mu_read(priv, IMX_MU_xRRn(cp->idx)); in imx_mu_isr()
143 } else if (val == IMX_MU_xSR_GIPn(cp->idx)) { in imx_mu_isr()
144 imx_mu_write(priv, IMX_MU_xSR_GIPn(cp->idx), IMX_MU_xSR); in imx_mu_isr()
147 dev_warn_ratelimited(priv->dev, "Not handled interrupt\n"); in imx_mu_isr()
156 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_send_data()
157 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_send_data()
160 switch (cp->type) { in imx_mu_send_data()
162 imx_mu_write(priv, *arg, IMX_MU_xTRn(cp->idx)); in imx_mu_send_data()
163 imx_mu_xcr_rmw(priv, IMX_MU_xCR_TIEn(cp->idx), 0); in imx_mu_send_data()
166 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIRn(cp->idx), 0); in imx_mu_send_data()
167 tasklet_schedule(&cp->txdb_tasklet); in imx_mu_send_data()
170 dev_warn_ratelimited(priv->dev, "Send data on wrong channel type: %d\n", cp->type); in imx_mu_send_data()
171 return -EINVAL; in imx_mu_send_data()
179 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_startup()
180 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_startup()
183 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_startup()
185 tasklet_init(&cp->txdb_tasklet, imx_mu_txdb_tasklet, in imx_mu_startup()
190 ret = request_irq(priv->irq, imx_mu_isr, IRQF_SHARED, cp->irq_desc, in imx_mu_startup()
193 dev_err(priv->dev, in imx_mu_startup()
194 "Unable to acquire IRQ %d\n", priv->irq); in imx_mu_startup()
198 switch (cp->type) { in imx_mu_startup()
200 imx_mu_xcr_rmw(priv, IMX_MU_xCR_RIEn(cp->idx), 0); in imx_mu_startup()
203 imx_mu_xcr_rmw(priv, IMX_MU_xCR_GIEn(cp->idx), 0); in imx_mu_startup()
214 struct imx_mu_priv *priv = to_imx_mu_priv(chan->mbox); in imx_mu_shutdown()
215 struct imx_mu_con_priv *cp = chan->con_priv; in imx_mu_shutdown()
217 if (cp->type == IMX_MU_TYPE_TXDB) { in imx_mu_shutdown()
218 tasklet_kill(&cp->txdb_tasklet); in imx_mu_shutdown()
223 IMX_MU_xCR_TIEn(cp->idx) | IMX_MU_xCR_RIEn(cp->idx)); in imx_mu_shutdown()
225 free_irq(priv->irq, chan); in imx_mu_shutdown()
239 if (sp->args_count != 2) { in imx_mu_xlate()
240 dev_err(mbox->dev, "Invalid argument count %d\n", sp->args_count); in imx_mu_xlate()
241 return ERR_PTR(-EINVAL); in imx_mu_xlate()
244 type = sp->args[0]; /* channel type */ in imx_mu_xlate()
245 idx = sp->args[1]; /* index */ in imx_mu_xlate()
248 if (chan >= mbox->num_chans) { in imx_mu_xlate()
249 dev_err(mbox->dev, "Not supported channel number: %d. (type: %d, idx: %d)\n", chan, type, idx); in imx_mu_xlate()
250 return ERR_PTR(-EINVAL); in imx_mu_xlate()
253 return &mbox->chans[chan]; in imx_mu_xlate()
258 if (priv->side_b) in imx_mu_init_generic()
261 /* Set default MU configuration */ in imx_mu_init_generic()
267 struct device *dev = &pdev->dev; in imx_mu_probe()
268 struct device_node *np = dev->of_node; in imx_mu_probe()
276 return -ENOMEM; in imx_mu_probe()
278 priv->dev = dev; in imx_mu_probe()
281 priv->base = devm_ioremap_resource(&pdev->dev, iomem); in imx_mu_probe()
282 if (IS_ERR(priv->base)) in imx_mu_probe()
283 return PTR_ERR(priv->base); in imx_mu_probe()
285 priv->irq = platform_get_irq(pdev, 0); in imx_mu_probe()
286 if (priv->irq < 0) in imx_mu_probe()
287 return priv->irq; in imx_mu_probe()
289 priv->clk = devm_clk_get(dev, NULL); in imx_mu_probe()
290 if (IS_ERR(priv->clk)) { in imx_mu_probe()
291 if (PTR_ERR(priv->clk) != -ENOENT) in imx_mu_probe()
292 return PTR_ERR(priv->clk); in imx_mu_probe()
294 priv->clk = NULL; in imx_mu_probe()
297 ret = clk_prepare_enable(priv->clk); in imx_mu_probe()
304 struct imx_mu_con_priv *cp = &priv->con_priv[i]; in imx_mu_probe()
306 cp->idx = i % 4; in imx_mu_probe()
307 cp->type = i >> 2; in imx_mu_probe()
308 cp->chan = &priv->mbox_chans[i]; in imx_mu_probe()
309 priv->mbox_chans[i].con_priv = cp; in imx_mu_probe()
310 snprintf(cp->irq_desc, sizeof(cp->irq_desc), in imx_mu_probe()
311 "imx_mu_chan[%i-%i]", cp->type, cp->idx); in imx_mu_probe()
314 priv->side_b = of_property_read_bool(np, "fsl,mu-side-b"); in imx_mu_probe()
316 spin_lock_init(&priv->xcr_lock); in imx_mu_probe()
318 priv->mbox.dev = dev; in imx_mu_probe()
319 priv->mbox.ops = &imx_mu_ops; in imx_mu_probe()
320 priv->mbox.chans = priv->mbox_chans; in imx_mu_probe()
321 priv->mbox.num_chans = IMX_MU_CHANS; in imx_mu_probe()
322 priv->mbox.of_xlate = imx_mu_xlate; in imx_mu_probe()
323 priv->mbox.txdone_irq = true; in imx_mu_probe()
329 return mbox_controller_register(&priv->mbox); in imx_mu_probe()
336 mbox_controller_unregister(&priv->mbox); in imx_mu_remove()
337 clk_disable_unprepare(priv->clk); in imx_mu_remove()
343 { .compatible = "fsl,imx6sx-mu" },