26 	0x01, 0x15,   /* XTAL = 4MHz, VCO = 352 MHz */
27 	0x02, 0x30,   /* MCLK = 88 MHz */
28 	0x03, 0x00,   /* ACR output 0 */
29 	0x04, 0x7d,   /* F22FR = 0x7d, F22 = f_VCO / 128 / 0x7d = 22 kHz */
30 	0x05, 0x05,   /* I2CT = 0, SCLT = 1, SDAT = 1 */
31 	0x06, 0x00,   /* DAC output 0 */
32 	0x08, 0x40,   /* DiSEqC off, LNB power on OP2/LOCK pin on */
33 	0x09, 0x00,   /* FIFO */
34 	0x0c, 0x51,   /* OP1/OP0 normal, val = 1 (LNB power on) */
35 	0x0d, 0x82,   /* DC offset compensation = on, beta_agc1 = 2 */
36 	0x0f, 0x92,   /* AGC1R */
37 	0x10, 0x34,   /* AGC2O */
38 	0x11, 0x84,   /* TLSR */
39 	0x12, 0xb9,   /* CFD */
40 	0x15, 0xc9,   /* lock detector threshold */
41 	0x28, 0x00,   /* out imp: normal, type: parallel, FEC mode: QPSK */
42 	0x33, 0xfc,   /* RS control */
43 	0x34, 0x93,   /* count viterbi bit errors per 2E18 bytes */
44 	0xff, 0xff
50 	u8 aclk = 0;  in alps_bsbe1_set_symbol_rate()
51 	u8 bclk = 0;  in alps_bsbe1_set_symbol_rate()
53 	if (srate < 1500000) { aclk = 0xb7; bclk = 0x47; }  in alps_bsbe1_set_symbol_rate()
54 	else if (srate < 3000000) { aclk = 0xb7; bclk = 0x4b; }  in alps_bsbe1_set_symbol_rate()
55 	else if (srate < 7000000) { aclk = 0xb7; bclk = 0x4f; }  in alps_bsbe1_set_symbol_rate()
56 	else if (srate < 14000000) { aclk = 0xb7; bclk = 0x53; }  in alps_bsbe1_set_symbol_rate()
57 	else if (srate < 30000000) { aclk = 0xb6; bclk = 0x53; }  in alps_bsbe1_set_symbol_rate()
58 	else if (srate < 45000000) { aclk = 0xb4; bclk = 0x51; }  in alps_bsbe1_set_symbol_rate()
60 	stv0299_writereg(fe, 0x13, aclk);  in alps_bsbe1_set_symbol_rate()
61 	stv0299_writereg(fe, 0x14, bclk);  in alps_bsbe1_set_symbol_rate()
62 	stv0299_writereg(fe, 0x1f, (ratio >> 16) & 0xff);  in alps_bsbe1_set_symbol_rate()
63 	stv0299_writereg(fe, 0x20, (ratio >>  8) & 0xff);  in alps_bsbe1_set_symbol_rate()
64 	stv0299_writereg(fe, 0x21, (ratio      ) & 0xf0);  in alps_bsbe1_set_symbol_rate()
66 	return 0;  in alps_bsbe1_set_symbol_rate()
75 	struct i2c_msg msg = { .addr = 0x61, .flags = 0, .buf = data, .len = sizeof(data) };  in alps_bsbe1_tuner_set_params()
82 	data[0] = (div >> 8) & 0x7f;  in alps_bsbe1_tuner_set_params()
83 	data[1] = div & 0xff;  in alps_bsbe1_tuner_set_params()
84 	data[2] = 0x80 | ((div & 0x18000) >> 10) | 0x1;  in alps_bsbe1_tuner_set_params()
85 	data[3] = 0xe0;  in alps_bsbe1_tuner_set_params()
90 	return (ret != 1) ? -EIO : 0;  in alps_bsbe1_tuner_set_params()
94 	.demod_address = 0x68,
98 	.skip_reinit = 0,