Lines Matching +full:0 +full:x76
51 } while (0)
56 {{0x09,0x01}, /* SoftResetAll */
57 {0x09,0x00}, /* release reset */
58 {0x01,0xe8}, /* MSB of code rate 27.5MS/s */
59 {0x02,0x17}, /* middle byte " */
60 {0x03,0x29}, /* LSB " */
61 {0x05,0x03}, /* @ DVB mode, standard code rate 3/4 */
62 {0x06,0xa5}, /* @ PLL 60MHz */
63 {0x07,0x01}, /* @ Fclk, i.e. sampling clock, 60MHz */
64 {0x0a,0x00}, /* @ partial chip disables, do not set */
65 {0x0b,0x01}, /* set output clock in gapped mode, start signal low
67 {0x0c,0x11}, /* no parity bytes, large hold time, serial data out */
68 {0x0d,0x6f}, /* @ RS Sync/Unsync thresholds */
69 {0x10,0x40}, /* chip doc is misleading here: write bit 6 as 1
72 {0x15,0xff}, /* @ size of the limited time window for RS BER
75 {0x16,0x00}, /* @ enable all RS output ports */
76 {0x17,0x04}, /* @ time window allowed for the RS to sync */
77 {0x18,0xae}, /* @ allow all standard DVB code rates to be scanned
81 {0x21,0x10}, /* @ during AutoAcq, search each viterbi setting
83 {0x23,0x18}, /* @ size of the limited time window for Viterbi BER
86 {0x24,0x24}, /* do not trigger Viterbi CRC test. Finite count window */
89 {0x35,0x40}, /* disable all interrupts. They are not connected anyway */
90 {0x36,0xff}, /* clear all interrupt pending flags */
91 {0x37,0x00}, /* @ fully enable AutoAcqq state machine */
92 {0x38,0x07}, /* @ enable fade recovery, but not autostart AutoAcq */
95 {0x41,0x00}, /* @ MSB of front-end derotator frequency */
96 {0x42,0x00}, /* @ middle bytes " */
97 {0x43,0x00}, /* @ LSB " */
100 {0x56,0x4d}, /* set the filtune voltage to 2.7V, as recommended by */
102 {0x57,0x00}, /* @ Filter sigma delta enabled, positive */
103 {0x61,0x95}, /* GPIO pins 1-4 have special function */
104 {0x62,0x05}, /* GPIO pin 5 has special function, pin 6 is GPIO */
105 {0x63,0x00}, /* All GPIO pins use CMOS output characteristics */
106 {0x64,0x20}, /* GPIO 6 is input, all others are outputs */
107 {0x6d,0x30}, /* tuner auto mode clock freq 62kHz */
108 {0x70,0x15}, /* use auto mode, tuner word is 21 bits long */
109 {0x73,0x00}, /* @ disable several demod bypasses */
110 {0x74,0x00}, /* @ " */
111 {0x75,0x00} /* @ " */
119 struct i2c_msg msg = { .addr = state->config->demod_address, .flags = 0, .buf = buf, .len = 2 }; in cx24110_writereg()
123 dprintk("%s: writereg error (err == %i, reg == 0x%02x, data == 0x%02x)\n", in cx24110_writereg()
128 return 0; in cx24110_writereg()
135 u8 b1 [] = { 0 }; in cx24110_readreg()
136 …struct i2c_msg msg [] = { { .addr = state->config->demod_address, .flags = 0, .buf = b0, .len = 1 … in cx24110_readreg()
143 return b1[0]; in cx24110_readreg()
153 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1); in cx24110_set_inversion()
155 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)&0xf7); in cx24110_set_inversion()
156 /* Initial value 0 at start of acq */ in cx24110_set_inversion()
157 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)&0xef); in cx24110_set_inversion()
158 /* current value 0 */ in cx24110_set_inversion()
163 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)|0x1); in cx24110_set_inversion()
165 cx24110_writereg(state,0x5,cx24110_readreg(state,0x5)|0x08); in cx24110_set_inversion()
167 cx24110_writereg(state,0x22,cx24110_readreg(state,0x22)|0x10); in cx24110_set_inversion()
171 cx24110_writereg(state,0x37,cx24110_readreg(state,0x37)&0xfe); in cx24110_set_inversion()
178 return 0; in cx24110_set_inversion()
184 static const int g1[FEC_AUTO] = {-1, 0x01, 0x02, 0x05, 0x15, 0x45, -1}; in cx24110_set_fec()
185 static const int g2[FEC_AUTO] = {-1, 0x01, 0x03, 0x06, 0x1a, 0x7a, -1}; in cx24110_set_fec()
195 cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) & 0xdf); in cx24110_set_fec()
197 cx24110_writereg(state, 0x18, 0xae); in cx24110_set_fec()
199 cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | 0x3); in cx24110_set_fec()
201 cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | 0x3); in cx24110_set_fec()
203 cx24110_writereg(state, 0x1a, 0x05); in cx24110_set_fec()
204 cx24110_writereg(state, 0x1b, 0x06); in cx24110_set_fec()
206 return 0; in cx24110_set_fec()
208 cx24110_writereg(state, 0x37, cx24110_readreg(state, 0x37) | 0x20); in cx24110_set_fec()
210 if (rate[fec] < 0) in cx24110_set_fec()
213 cx24110_writereg(state, 0x05, (cx24110_readreg(state, 0x05) & 0xf0) | rate[fec]); in cx24110_set_fec()
215 cx24110_writereg(state, 0x22, (cx24110_readreg(state, 0x22) & 0xf0) | rate[fec]); in cx24110_set_fec()
217 cx24110_writereg(state, 0x1a, g1[fec]); in cx24110_set_fec()
218 cx24110_writereg(state, 0x1b, g2[fec]); in cx24110_set_fec()
221 return 0; in cx24110_set_fec()
228 i=cx24110_readreg(state,0x22)&0x0f; in cx24110_get_fec()
229 if(!(i&0x08)) { in cx24110_get_fec()
255 for(i = 0; (i < ARRAY_SIZE(bands)) && (srate>bands[i]); i++) in cx24110_set_symbolrate()
258 and set the PLL accordingly (R07[1:0] Fclk, R06[7:4] PLLmult, in cx24110_set_symbolrate()
259 R06[3:0] PLLphaseDetGain */ in cx24110_set_symbolrate()
260 tmp=cx24110_readreg(state,0x07)&0xfc; in cx24110_set_symbolrate()
262 cx24110_writereg(state,0x07,tmp); in cx24110_set_symbolrate()
263 cx24110_writereg(state,0x06,0x78); in cx24110_set_symbolrate()
266 cx24110_writereg(state,0x07,tmp|0x1); in cx24110_set_symbolrate()
267 cx24110_writereg(state,0x06,0xa5); in cx24110_set_symbolrate()
270 cx24110_writereg(state,0x07,tmp|0x2); in cx24110_set_symbolrate()
271 cx24110_writereg(state,0x06,0x87); in cx24110_set_symbolrate()
274 cx24110_writereg(state,0x07,tmp|0x3); in cx24110_set_symbolrate()
275 cx24110_writereg(state,0x06,0x78); in cx24110_set_symbolrate()
281 /* the maximum dividend is 90999000/2, 0x02b6446c, this number is in cx24110_set_symbolrate()
304 cx24110_writereg(state, 0x1, (ratio>>16)&0xff); in cx24110_set_symbolrate()
305 cx24110_writereg(state, 0x2, (ratio>>8)&0xff); in cx24110_set_symbolrate()
306 cx24110_writereg(state, 0x3, (ratio)&0xff); in cx24110_set_symbolrate()
308 return 0; in cx24110_set_symbolrate()
323 cx24110_writereg(state,0x6d,0x30); /* auto mode at 62kHz */ in _cx24110_pll_write()
324 cx24110_writereg(state,0x70,0x15); /* auto mode 21 bits */ in _cx24110_pll_write()
327 while (cx24110_readreg(state,0x6d)&0x80) in _cx24110_pll_write()
328 cx24110_writereg(state,0x72,0); in _cx24110_pll_write()
331 cx24110_writereg(state,0x72,buf[0]); in _cx24110_pll_write()
334 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) in _cx24110_pll_write()
338 cx24110_writereg(state,0x72,buf[1]); in _cx24110_pll_write()
339 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) in _cx24110_pll_write()
343 cx24110_writereg(state,0x72,buf[2]); in _cx24110_pll_write()
344 while ((cx24110_readreg(state,0x6d)&0xc0)==0x80) in _cx24110_pll_write()
348 cx24110_writereg(state,0x6d,0x32); in _cx24110_pll_write()
349 cx24110_writereg(state,0x6d,0x30); in _cx24110_pll_write()
351 return 0; in _cx24110_pll_write()
362 for(i = 0; i < ARRAY_SIZE(cx24110_regdata); i++) { in cx24110_initfe()
366 return 0; in cx24110_initfe()
376 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0xc0); in cx24110_set_voltage()
378 return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&0x3b)|0x40); in cx24110_set_voltage()
392 bit = 0x00; in cx24110_diseqc_send_burst()
394 bit = 0x08; in cx24110_diseqc_send_burst()
398 rv = cx24110_readreg(state, 0x77); in cx24110_diseqc_send_burst()
399 if (!(rv & 0x04)) in cx24110_diseqc_send_burst()
400 cx24110_writereg(state, 0x77, rv | 0x04); in cx24110_diseqc_send_burst()
402 rv = cx24110_readreg(state, 0x76); in cx24110_diseqc_send_burst()
403 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40 | bit)); in cx24110_diseqc_send_burst()
405 while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40)) in cx24110_diseqc_send_burst()
408 return 0; in cx24110_diseqc_send_burst()
421 for (i = 0; i < cmd->msg_len; i++) in cx24110_send_diseqc_msg()
422 cx24110_writereg(state, 0x79 + i, cmd->msg[i]); in cx24110_send_diseqc_msg()
424 rv = cx24110_readreg(state, 0x77); in cx24110_send_diseqc_msg()
425 if (rv & 0x04) { in cx24110_send_diseqc_msg()
426 cx24110_writereg(state, 0x77, rv & ~0x04); in cx24110_send_diseqc_msg()
430 rv = cx24110_readreg(state, 0x76); in cx24110_send_diseqc_msg()
432 cx24110_writereg(state, 0x76, ((rv & 0x90) | 0x40) | ((cmd->msg_len-3) & 3)); in cx24110_send_diseqc_msg()
434 while (!time_after(jiffies, timeout) && !(cx24110_readreg(state, 0x76) & 0x40)) in cx24110_send_diseqc_msg()
437 return 0; in cx24110_send_diseqc_msg()
445 int sync = cx24110_readreg (state, 0x55); in cx24110_read_status()
447 *status = 0; in cx24110_read_status()
449 if (sync & 0x10) in cx24110_read_status()
452 if (sync & 0x08) in cx24110_read_status()
455 sync = cx24110_readreg (state, 0x08); in cx24110_read_status()
457 if (sync & 0x40) in cx24110_read_status()
460 if (sync & 0x20) in cx24110_read_status()
463 if ((sync & 0x60) == 0x60) in cx24110_read_status()
466 return 0; in cx24110_read_status()
474 if(cx24110_readreg(state,0x24)&0x10) { in cx24110_read_ber()
476 cx24110_writereg(state,0x24,0x04); /* select the ber reg */ in cx24110_read_ber()
477 state->lastber=cx24110_readreg(state,0x25)| in cx24110_read_ber()
478 (cx24110_readreg(state,0x26)<<8); in cx24110_read_ber()
479 cx24110_writereg(state,0x24,0x04); /* start new count window */ in cx24110_read_ber()
480 cx24110_writereg(state,0x24,0x14); in cx24110_read_ber()
484 return 0; in cx24110_read_ber()
492 u8 signal = cx24110_readreg (state, 0x27)+128; in cx24110_read_signal_strength()
495 return 0; in cx24110_read_signal_strength()
503 if(cx24110_readreg(state,0x6a)&0x80) { in cx24110_read_snr()
505 state->lastesn0=cx24110_readreg(state,0x69)| in cx24110_read_snr()
506 (cx24110_readreg(state,0x68)<<8); in cx24110_read_snr()
507 cx24110_writereg(state,0x6a,0x84); /* start new count window */ in cx24110_read_snr()
511 return 0; in cx24110_read_snr()
518 if(cx24110_readreg(state,0x10)&0x40) { in cx24110_read_ucblocks()
520 cx24110_writereg(state,0x10,0x60); /* select the byer reg */ in cx24110_read_ucblocks()
521 (void)(cx24110_readreg(state, 0x12) | in cx24110_read_ucblocks()
522 (cx24110_readreg(state, 0x13) << 8) | in cx24110_read_ucblocks()
523 (cx24110_readreg(state, 0x14) << 16)); in cx24110_read_ucblocks()
524 cx24110_writereg(state,0x10,0x70); /* select the bler reg */ in cx24110_read_ucblocks()
525 state->lastbler=cx24110_readreg(state,0x12)| in cx24110_read_ucblocks()
526 (cx24110_readreg(state,0x13)<<8)| in cx24110_read_ucblocks()
527 (cx24110_readreg(state,0x14)<<16); in cx24110_read_ucblocks()
528 cx24110_writereg(state,0x10,0x20); /* start new count window */ in cx24110_read_ucblocks()
532 return 0; in cx24110_read_ucblocks()
542 if (fe->ops.i2c_gate_ctrl) fe->ops.i2c_gate_ctrl(fe, 0); in cx24110_set_frontend()
548 cx24110_writereg(state,0x04,0x05); /* start acquisition */ in cx24110_set_frontend()
550 return 0; in cx24110_set_frontend()
561 sclk = cx24110_readreg (state, 0x07) & 0x03; in cx24110_get_frontend()
564 if (sclk==0) sclk=90999000L/2L; in cx24110_get_frontend()
569 afc = sclk*(cx24110_readreg (state, 0x44)&0x1f)+ in cx24110_get_frontend()
570 ((sclk*cx24110_readreg (state, 0x45))>>8)+ in cx24110_get_frontend()
571 ((sclk*cx24110_readreg (state, 0x46))>>16); in cx24110_get_frontend()
574 p->inversion = (cx24110_readreg (state, 0x22) & 0x10) ? in cx24110_get_frontend()
578 return 0; in cx24110_get_frontend()
586 …return cx24110_writereg(state,0x76,(cx24110_readreg(state,0x76)&~0x10)|(((tone==SEC_TONE_ON))?0x10… in cx24110_set_tone()
610 state->lastber = 0; in cx24110_attach()
611 state->lastbler = 0; in cx24110_attach()
612 state->lastesn0 = 0; in cx24110_attach()
615 ret = cx24110_readreg(state, 0x00); in cx24110_attach()
616 if ((ret != 0x5a) && (ret != 0x69)) goto error; in cx24110_attach()